1233690 玖、發明說明： 【發明所屬之技術領域】 結構及其製備方法，特別 之快閃記憶體結構及其製 本發明係關於一種快閃記憶體 係關於一種具有尖錐狀選擇閘極 備方法。 【先前技術】 圖1係—習知快閃記憶體結構’揭示於美國專利第 6,355,524號。如圖i所示’堆疊結構71〇側邊具有一多晶 (polysUicon spacer) 520 ^ P, ^ It ^ it 擇閘極。該多晶梦間_ 52〇之製備方法係先在一半導體 基板上形成該堆疊結構71〇冑，沈積—多晶石夕層於該半導 體基板表面。然後，非等向㈣該多晶碎層以形成該多晶 矽間隙壁520，再佈植摻質（d〇pant)於該多晶矽間隙壁 520以形成該選擇閘極。惟，隨後在該選擇閘極旁形成一連 接摻雜區134之接觸洞時，該多晶矽間隙壁52〇(即該選擇 閘極）極易於因微影製程之光罩對位不準而被蝕刻，導致 該選擇閘極與後續形成於該接觸洞中之插塞形成電氣接觸 而導致記憶元件之失效。 為了解決前述之缺點，目前積體電路製造產業之標準製 程在形成該選擇閘極520後另沈積一氮化矽層覆蓋於該堆 疊結構710與該選擇閘極52〇之側邊，並對該氮化矽層進 行一非等向性蝕刻製程以形成一第二間隙壁於該選擇閘極 520之側邊。該第二間隙壁係用以在該選擇閘極520與後續 形成於該接觸洞中之插塞提供電氣隔絕。1233690 发明 Description of the invention: [Technical field to which the invention belongs] Structure and preparation method thereof, particularly flash memory structure and manufacturing method The present invention relates to a flash memory system, and relates to a method for preparing a gate with a tapered selection gate. [Prior Art] Figure 1 is a conventional flash memory structure 'disclosed in U.S. Patent No. 6,355,524. As shown in FIG. I, the side of the stacked structure 71 has a polysUicon spacer 520 ^ P, ^ It ^ it. The method for preparing the polycrystalline dream_52 is to first form the stacked structure 7101 on a semiconductor substrate, and deposit a polycrystalline layer on the surface of the semiconductor substrate. Then, the polycrystalline debris layer is anisotropically formed to form the polycrystalline silicon spacer 520, and then dopant is implanted on the polycrystalline silicon spacer 520 to form the selective gate. However, when a contact hole connecting the doped region 134 is formed next to the selective gate, the polycrystalline silicon spacer wall 52 (that is, the selective gate) is extremely easy to be misaligned due to the misalignment of the mask of the lithography process Etching results in electrical contact between the selection gate and a plug formed subsequently in the contact hole, resulting in failure of the memory element. In order to solve the aforementioned shortcomings, the current standard process of the integrated circuit manufacturing industry, after forming the selection gate 520, deposits another silicon nitride layer to cover the sides of the stacked structure 710 and the selection gate 52, and The silicon nitride layer is subjected to an anisotropic etching process to form a second gap wall on the side of the selection gate 520. The second partition wall is used to provide electrical isolation between the selection gate 520 and a plug formed in the contact hole.
H:\HU\HYGM德科技 丨513\91513.DOC 1233690 惟’利用前述製程形成之第二間隙壁的高度較小且厚度 較薄m因微影製程之光罩對位4而被钱刻去除二 因此，為避免連接該汲極134之插塞與該選擇閘極52〇間 形成紐路，習知技藝必須採用較寬鬆之設計準則來設計相 關於該汲才圣134之尺寸，因而記憶體元件具有較大的元件 尺寸。相對地，若設計相關於該汲極134之尺寸未採用較 寬鬆之設計準則，連接該汲極134之插塞與該選擇閘極52〇 間的電氣隔絕較差而易於形成短路。 另，美國專利公開案第2003/0215999號、中華民國專利 公告第535,265、359,879 A 232,〇97號亦揭示相關於快閃 β己j思體結構及製備方法之技術。 【發明内容】 本發明之主要目的係提供一種具有尖錐狀選擇閘極之快 閃記憶體結構及其製備方法。 為達成上述目❸’本發明冑示一㈣閃記憶體結構及其 製備方法。該快閃記憶體結構包含一矽基板、一設置於該 矽基板上之堆疊結構、一設置於該堆疊結構側邊之第一間 隙壁、一設置於該第一間隙壁側邊之選擇閘極以及一設^ 於該選擇閘極側邊之第二間隙壁。該選擇閘極具有一凹表 面，且其與該第二間隙壁之連接處呈一尖錐狀。該選擇間 極與該第-㈣壁連接處的高度小於與該帛二㈣壁連接 處的高度。 豐結構於一矽基板上以 。接著沈積一多晶石夕層 本發明之製備方法首先形成一堆 及一第一間隙壁於該堆疊結構側邊H: \ HU \ HYGM German Technology 丨 513 \ 91513.DOC 1233690 However, the height of the second partition wall formed by the aforementioned process is smaller and the thickness is thinner. M was removed by the engraving of mask 4 in the photolithography process. Secondly, in order to avoid forming a new road between the plug of the drain electrode 134 and the selection gate 52, the conventional technique must adopt a looser design criterion to design the size related to the drainer 134, so the memory The component has a larger component size. In contrast, if the design related to the size of the drain electrode 134 does not adopt a looser design criterion, the electrical isolation between the plug connecting the drain electrode 134 and the selection gate 52 is poor and it is easy to form a short circuit. In addition, U.S. Patent Publication No. 2003/0215999 and Republic of China Patent Publication No. 535,265, 359,879 A 232, 〇97 also disclose the technology related to the structure and preparation method of flash β-β. SUMMARY OF THE INVENTION The main object of the present invention is to provide a flash memory structure with a tapered selection gate and a method for preparing the same. To achieve the above object, the present invention shows a flash memory structure and a preparation method thereof. The flash memory structure includes a silicon substrate, a stacked structure disposed on the silicon substrate, a first gap wall disposed on a side of the stacked structure, and a selection gate disposed on a side of the first gap wall. And a second partition wall provided on the side of the selection gate. The selection gate has a concave surface, and a connection point between the selection gate and the second gap wall is a sharp cone. The height of the junction between the selection pole and the second sacral wall is smaller than the height of the junction with the second sacral wall. Fung structure on a silicon substrate. Next, a polycrystalline stone layer is deposited. In the preparation method of the present invention, a pile and a first partition wall are formed on the side of the stacked structure.
H AHU\H YG\ 茂德科技\9 丨 5 丨 3\91513. DOC 1233690 ==表：、該堆疊結構表面與該第-間隙壁側邊。 夕y 我對準之氧化物遮罩於該第-間隙壁旁之 :夕=並利用該氧化物遮罩進行，刻製程以 門二==邊形成—第> 間隙壁於该選擇閘極側邊。 氧化物遮罩之方法係先沈積—第-氧化層於該多 ;曰=面，然後進行-非等向性乾姓刻以去除該多晶梦 層局《面之第一氧化層，而殘留於該第一間隙壁旁之多 :曰石夕層側邊之第一氧化層則形成該自我對準之氧化物遮 罩。此外1氧化物遮罩亦可在非等向性乾姓刻後，另沈 積第一乳化層於該多晶石夕層與該第一氧化層之表面。之 後再進二另進行一非等向性乾姓刻，去除該多晶石夕層居 部表面之第二氧化& 層而殘留於該多晶矽層側邊之第一氧 化層及第二氧化層則形成該氧化物遮罩。 【實施方式】 圖 圖1 1例7^本發明之快閃記憶體結構之製備方法。 如圖2所不’本發明首先於一石夕基板^上形成二堆疊結構 2 0 ’其中各堆疊結才盖9 4人 且、、口構20包含一設置於該矽基板12上之穿 隧氧化層22、一号罟於办α斤 °置於牙隨氧化層22上之浮置閘極24、 -設置於該浮置閑極24上之介電層％、一設置於該介電 層26上之控制閘極LV供 < w 28以及一没置於該控制閘極28上之氮 化石夕層3 0。之德，带士、 咕 更$成一弟一間隙壁32於該堆疊結構20 側邊。 如圖3所示，本發明之製備方法接著形成-具有-開口H AHU \ H YG \ Maode Technology \ 9 丨 5 丨 3 \ 91513. DOC 1233690 == Table: The surface of the stacked structure and the side of the -gap wall. Xi y The oxide mask that I aligned is next to the-gap wall: Xi = and use this oxide mask to carry out the engraving process with gate two == side formation-the > gap wall at the selection gate Side. The method of oxide masking is to first deposit-the first-oxide layer on the surface; said = surface, and then-anisotropic dry engraving to remove the polycrystalline dream layer "the first oxide layer on the surface, and the residue As many as near the first gap wall: the first oxide layer on the side of the Shi Xi layer forms the self-aligned oxide mask. In addition, the 1 oxide mask can also deposit a first emulsion layer on the surface of the polycrystalline stone layer and the first oxide layer after the anisotropic dry name is engraved. Then proceed to another non-isotropic dry engraving to remove the second oxide & layer on the surface of the polycrystalline silicon layer and leave the first oxide layer and the second oxide layer on the side of the polycrystalline silicon layer. The oxide mask is formed. [Embodiment] FIG. 11 illustrates a method for preparing the flash memory structure of the present invention. As shown in FIG. 2, the present invention first forms a two-stacked structure 20 on a stone substrate ^, where each stacked junction is covered by 94, and the mouth structure 20 includes a tunnel oxidation disposed on the silicon substrate 12. Layer 22, No. 1 办 α floating gate 24 placed on the dental oxide layer 22, a dielectric layer% disposed on the floating idler 24, one disposed on the dielectric layer 26 The above control gate LV is provided for < w 28 and a nitride layer 30 which is not placed on the control gate 28. The virtues, belts, and goo become a brother and a partition wall 32 on the side of the stacked structure 20. As shown in FIG. 3, the preparation method of the present invention is followed by forming-having-opening
Η.\H U\H YG\茂德科技⑼5丨3\9丨5丨3. DOC 1233690 36之光阻層34於該石夕基板12上。之後，進 以經由該開口 36將換所 佈植製程 12内，以形成一、㈣W於二堆疊結構2〇間之石夕基板 成源極摻雜區38。完成該佈植 該光阻層34去除。 植1軽後，即將 如圖4所示，、、女接_々 沈積一夕晶矽層4〇於該矽基板 =;:。表面與該第一間隙壁32側邊後，再： 第一乳化層42於兮炙曰a « …亥夕日日矽層40表面。然後，進行一 =乾#刻製程’去除該多晶矽層4〇局部表 留於該第—間隙壁32旁之多晶㈣側邊之第 —。士 \ Μ成—自我對準之氧化物遮罩，如圖5所 示。s亥非等向性乾韻刻穿 之混合氣體為餘刻氣體地可使用四氣化碳與氯氣 時本發明亦可藉由增加該非等向性乾-刻之 ， °P刀多晶矽層4〇而形成-尖錐部44後，再另 =第二氧化層46於該多晶…。及殘留第一氧化層 晶石夕層f再進行另—料向性乾_，去除該多 ^ θ ° 表面之第二氧化層46，而殘留部分之第一 及第二氧化層46於該多晶石夕層40側邊（即該尖 錐邛44)，如圖7所示。 化物j圖8 W用圖5所示之殘留第-氧化層42作為氧 1 =，進行，刻製程以形成-具有-凹…4 之選擇閘極50於嗜笛—Μ扯、批1 製程亦可利用圖、/所示之㈣;側邊。此外，該㈣刻 如作為氧化物μ，二 氣化層42及第二氧化層 … 以形成"亥選擇閘極50之凹表面54。Η. \ H U \ H YG \ Maode Technology⑼5 丨 3 \ 9 丨 5 丨 3. The photoresist layer 34 of DOC 1233690 36 is on the stone substrate 12. After that, the replanting process 12 is performed through the opening 36 to form a silicon doped substrate with a thickness of 20 to a stack structure of 20 to form a source doped region 38. The implantation is completed and the photoresist layer 34 is removed. After the implantation, as shown in FIG. 4, a silicon layer 40 is deposited on the silicon substrate as shown in FIG. 4; After the surface and the side of the first gap wall 32, the first emulsified layer 42 is on the surface of the silicon layer 40. Then, a dry etching process is performed to remove the polycrystalline silicon layer 40, and the polycrystalline silicon layer 40 is partially left on the polycrystalline silicon side next to the first spacer 32. Taxi \ Μ 成 —Self-aligned oxide mask, as shown in Figure 5. When the mixed gas engraved with anisotropic dry rhyme is used as an off-gas, the present invention can also increase the anisotropic dry-engraving by adding the anisotropic dry-etched polycrystalline silicon layer 4 °. After the -spike portion 44 is formed, a second oxide layer 46 is formed on the polycrystalline silicon. And the remaining first oxide layer, the spar layer, and then perform another material-oriented drying, to remove the second oxide layer 46 on the surface of the multiple θ °, and the remaining first and second oxide layers 46 on the multiple The side of the spar evening layer 40 (that is, the sharp cone 44) is shown in FIG. Compound J Figure 8 W The remaining first oxide layer 42 shown in Figure 5 is used as oxygen 1 =, and the process is engraved to form -with-concave ... 4 selection gates 50 are used in the mute-M, batch 1 process. Available in the picture, / shown ㈣; side. In addition, the engraving serves as the oxide μ, the second gasification layer 42 and the second oxide layer to form the concave surface 54 of the " Hier select gate 50.
HAHLAH YG\茂德科技\9丨5丨3 \9丨5 ί 3 DOC 1233690 之後’形成-第二間隙壁60於該選擇閘極5〇側邊，其中 該第二間隙壁60可由氮化石夕構成。 由於該氧化物遮罩可避免其覆蓋之多晶碎在該㈣刻製 程中被蝕刻去除，因此該選擇問極5〇與該第一間隙壁32 連接處之高度小於與該第二間隙壁6〇連接處（即由該氧化 物遮罩覆蓋之尖錐部44 )之高度。該濕蝕刻製程使用之蝕 刻液對多晶石夕與氧化物二者具有高選擇比（即 polysilicon/oxide )，以便選擇性地去除在該堆疊結構2〇及 矽基板12上之多晶矽，而保留在該氧化物遮罩下方之多晶 矽。該濕蝕刻製程較佳地可使用氫氟酸（HF)、硝酸（hn〇3) 及乙酸（CH3COOH )之混合液為敍刻液。 如圖9所示，進行矽化物製程以分別形成一矽化物電極 62於該選擇閘極50之凹表面54、一矽化物電極64於源極 摻雜區38上之多晶矽表面以及二矽化物電極66於矽基板 12表面。之後，進行一佈植製程以形成汲極摻雜區68於 該矽化物電極66下方。 如圖10所示，形成一内層介電層7〇及進行一化學機械 研磨製程以平坦化該内層介電層70後，於該内層介電層 7 〇中形成連接該汲極摻雜區6 8之接觸洞8 0。之後，於該 接觸洞80中沈積導電物質以形成連接該矽化物電極68之 插塞82，如圖11所示。 相較於習知技藝，本發明之快閃記憶體結構具有較大的 製程裕度（process window )。由於該第二間隙壁60完全 覆蓋该選擇閘極5 0之侧邊，因此後續形成該接觸洞8 〇之 德科技\915丨3\915丨3 D〇c -9- !233690 製程即使有些許對位誤差（例 ¥、 、例如锨影製程之光罩對位钽 ’該第二間隙壁60亦可避免該選擇閘極5。在該接觸 洞80之姓刻過程被姓刻去除，用以確保該選擇問極50之 電氣特性。 夂 此外，由於該選擇問極50之側邊由該氧化物遮罩覆蓋， 可㈣在祕刻製程中被去除而得以保有較大的高度，因 此後績形成於該選擇閘極5G側邊之第二間隙壁Μ亦 較大的高度及寬度。第二間隙壁60具有較大的高度可：分 地避免該選擇閘極50在後續_製程中被去除因而可縮 小插塞82之設計準則，且藉以減小記憶胞之尺寸。而該第 二間隙壁60具有較大的寬度則可在該選擇電極％與該汲 極摻雜區6 8之間提供較佳的電氣隔絕。 本發明之技術内容及技術特點已揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修飾。因此，本發明之保護範圍 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡要說明】 圖1係一習知快閃記憶體結構之示意圖；以及 圖2至圖11例示本發明之快閃記憶體結構之製備方法。 【元件符號說明】 12矽基板 20堆疊結構 22穿隧氧化層 24浮置閘極 26介電層 28浮置閘極 H:\HU\HYi 茂德科技\9 丨513\91513.DOC -10- 1233690 30 氮化矽層 32 第一間隙壁 34 光阻層 36 開口 38 源極摻雜區 40 多晶矽層 42 第一氧化層 44 尖錐部 46 第二氧化層 50 選擇閘極 54 凹表面 60 第二間隙壁 62 矽化物電極 64 矽化物電極 68 矽化物電極 70 内層介電層 80 接觸洞 82 插塞 HAHU\HYG\ 茂德科技\9丨513\91513.〇〇0 - 11 -HAHLAH YG \ Maode Technology \ 9 丨 5 丨 3 \ 9 丨 5 ′ 3 DOC 1233690 after the formation-the second spacer 60 on the side of the selection gate 50, wherein the second spacer 60 can be composed of nitride stone . Since the oxide mask can prevent the polycrystalline debris covered by it from being etched away during the engraving process, the height of the connection between the selection question 50 and the first spacer 32 is less than that with the second spacer 6 〇 The height of the connection (ie, the tapered portion 44 covered by the oxide mask). The etching solution used in the wet etching process has a high selectivity ratio (ie polysilicon / oxide) to both polycrystalline stone and oxide, so as to selectively remove polycrystalline silicon on the stacked structure 20 and the silicon substrate 12 while retaining Polycrystalline silicon under the oxide mask. In the wet etching process, a mixed solution of hydrofluoric acid (HF), nitric acid (hn03), and acetic acid (CH3COOH) is preferably used as the etching solution. As shown in FIG. 9, a silicide process is performed to form a silicide electrode 62 on the concave surface 54 of the selection gate 50, a silicide electrode 64 on the polycrystalline silicon surface on the source doped region 38, and a silicide electrode, respectively. 66 on the surface of the silicon substrate 12. Thereafter, a implantation process is performed to form a drain doped region 68 under the silicide electrode 66. As shown in FIG. 10, after forming an inner dielectric layer 70 and performing a chemical mechanical polishing process to planarize the inner dielectric layer 70, a connection to the drain doped region 6 is formed in the inner dielectric layer 70. Contact hole of 8 8 0. Thereafter, a conductive substance is deposited in the contact hole 80 to form a plug 82 connected to the silicide electrode 68, as shown in FIG. Compared with the conventional art, the flash memory structure of the present invention has a larger process window. Since the second gap wall 60 completely covers the side of the selection gate 50, the contact hole 80 is formed in the subsequent process. Detech \ 915 丨 3 \ 915 丨 3 D〇c -9-! 233690 Alignment error (for example, ¥, for example, the photomask alignment of tantalum process, the second spacer 60 can also avoid the selection gate 5. The last name engraving process in the contact hole 80 is removed by the last name engraving to Ensures the electrical characteristics of the selection interrogator 50. 夂 In addition, since the side of the selection interrogator 50 is covered by the oxide mask, it can be removed during the secret engraving process to maintain a large height, so the performance The second gap wall M formed on the side of the 5G of the selection gate also has a larger height and width. The second gap wall 60 has a larger height to prevent the selection gate 50 from being removed in subsequent processes separately. Therefore, the design criterion of the plug 82 can be reduced, and the size of the memory cell can be reduced. The second spacer 60 having a larger width can be provided between the selection electrode% and the drain doped region 68. Better electrical isolation. The technical content and technical features of the present invention have been disclosed above. However, those familiar with the technology may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention should not be limited to those disclosed in the embodiments, but should include various Departures and modifications of the present invention are covered by the following patent applications. [Brief Description of the Drawings] FIG. 1 is a schematic diagram of a conventional flash memory structure; and FIG. 2 to FIG. 11 illustrate the flash memory of the present invention. Preparation method of memory structure. [Element symbol description] 12 Silicon substrate 20 Stacked structure 22 Tunneling oxide layer 24 Floating gate 26 Dielectric layer 28 Floating gate H: \ HU \ HYi Maude Technology \ 9 丨 513 \ 91513.DOC -10- 1233690 30 silicon nitride layer 32 first spacer 34 photoresist layer 36 opening 38 source doped region 40 polycrystalline silicon layer 42 first oxide layer 44 tapered portion 46 second oxide layer 50 selection gate 54 Concave surface 60 Second gap wall 62 Silicide electrode 64 Silicide electrode 68 Silicide electrode 70 Inner dielectric layer 80 Contact hole 82 Plug HAHU \ HYG \ Maode Technology \ 9 丨 513 \ 91513.〇〇0-11-