CN109935547A - A kind of 3D nand memory part and its manufacturing method - Google Patents
A kind of 3D nand memory part and its manufacturing method Download PDFInfo
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Abstract
The application provides a kind of 3D nand memory part and its manufacturing method, grid layer and the alternately stacked stack layer of insulating layer and the common source groove through stack layer is formed on the substrate, filled layer and wall are formed in common source groove, the wall is between the grid layer and filled layer, remove the wall between stack layer and filled layer, sidewall spacers can be formed, sidewall dielectric layers are formed in the sidewall spacers, air gap is formed in the sidewall dielectric layers, since the dielectric constant of air is smaller, parasitic capacitance then between grid layer and filled layer is smaller, to reduce the RC retardation ratio of memory device, improve device performance.
Description
Technical field
This application involves semiconductor devices and its manufacturing field, in particular to a kind of 3D nand memory part and its manufacture
Method.
Background technique
Nand memory part is the non-volatile memory product with low in energy consumption, light weight and excellent performance, under power blackout situation still
It is so able to maintain the data information of storage, is widely used in electronic product.The NAND device of planar structure is closely real
The limit of border extension reduces the carrying cost of every bit to further improve memory capacity, proposes 3D NAND storage
Device.
In 3D nand memory part structure, by the way of vertical stacking stacked gate, in memory device, substrate
On can form the stack layer of conductive layer and silicon oxide layer, the conductive layer in stack layer is as grid line, the core memory of stack layer
Area is formed with channel structure, drain electrode is formed at the top of channel structure, the core memory area of different memory part is by running through heap
The common source trench separation of lamination is opened, and source electrode of the filled layer as memory device can be formed in common source groove.
However, in the prior art, in order to increase storage density, the size of memory device is smaller and smaller, cause each in device
The distance between conductive layer also reduces therewith, and the parasitic capacitance between conductive layer is caused to increase with it, so that memory device be made to have
There is biggish RC delay effect, influences device performance.
Summary of the invention
In view of this, the application's is designed to provide a kind of 3D nand memory part and its manufacturing method, it is effectively reduced
The RC delay effect of memory device improves device performance.
To achieve the above object, this application provides a kind of manufacturing method of 3D nand memory part, the method packets
It includes:
Substrate is provided, grid layer and the alternately stacked stack layer of insulating layer are formed on the substrate, and through described
The common source groove of stack layer, filled layer and wall are formed in the common source groove, and the wall is located at described
Between stack layer and filled layer；
The wall is removed to form sidewall spacers；
Sidewall dielectric layers are formed in the sidewall spacers, are formed with air gap in the sidewall dielectric layers.
Optionally, the removal wall is to form sidewall spacers, comprising: the wall is removed using acid system,
Or the wall is removed using heat treatment mode, or the wall is removed by aqueous slkali.
Optionally, described to form sidewall dielectric layers in the sidewall spacers, comprising: by chemical vapor deposition manner or
Person's atomic layer deposition mode deposited sidewalls dielectric layer.
Optionally, the stack layer includes the lower selecting pipe bsg layer of bottom, and the removal wall is to form side wall
Interval, comprising: removal is located at the wall on the side wall of the stack layer of the bsg layer or more to form sidewall spacers.
Optionally, the filled layer is metal layer and/or polysilicon layer.
Optionally, dielectric layer is formed between the grid layer and the insulating layer, the dielectric layer also covers the grid
Pole level runs through the stack layer to the side of channel structure, the channel structure.
Optionally, the insulating layer is protruding from the grid layer along the direction for being parallel to the substrate surface.
The embodiment of the present application also provides a kind of 3D nand memory parts, comprising:
Substrate；
Stack layer on the substrate and the common source groove through the stack layer, the stack layer include alternating layer
Folded grid layer and insulating layer is filled with filled layer and sidewall dielectric layers, the sidewall dielectric layers in the common source groove
Between the filled layer and stack layer, and it is formed with air gap.
Optionally, the stack layer includes the lower selecting pipe bsg layer of bottom, is formed with wall on the bsg layer side wall.
Optionally, the filled layer is metal layer and/or polysilicon layer.
Optionally, dielectric layer is formed between the grid layer and the insulating layer, the dielectric layer also covers the grid
Pole level runs through the stack layer to the side of channel structure, the channel structure.
Optionally, the insulating layer is protruding from the grid layer along the direction for being parallel to the substrate surface.
In a kind of 3D nand memory part provided by the embodiments of the present application and its manufacturing method, grid have been formed on the substrate
Pole layer and the alternately stacked stack layer of insulating layer and the common source groove through stack layer, are formed with filling in common source groove
Layer and wall, the wall is between the grid layer and filled layer, between removing between stack layer and filled layer
Interlayer can form sidewall spacers, form sidewall dielectric layers in the sidewall spacers, be formed with gas in the sidewall dielectric layers
Gap, since the dielectric constant of air is smaller, then the parasitic capacitance between grid layer and filled layer is smaller, to reduce memory device
RC retardation ratio, improve device performance.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the application
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the flow diagram of the manufacturing method according to the embodiment of the present application 3D nand memory part；
Fig. 2-4 shows the structure formed during 3D nand memory part according to the manufacturing method of the embodiment of the present application
Schematic diagram.
Specific embodiment
In order to make the above objects, features, and advantages of the present application more apparent, with reference to the accompanying drawing to the application
Specific embodiment be described in detail.
Many details are explained in the following description in order to fully understand the application, but the application can be with
It is different from other way described herein using other and implements, those skilled in the art can be without prejudice to the application intension
In the case of do similar popularization, therefore the application is not limited by the specific embodiments disclosed below.
Secondly, the application combination schematic diagram is described in detail, when the embodiment of the present application is described in detail, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the range of the application protection.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technique, 3D nand memory part is constituted more by the way of vertical stacking stacked gate
Different devices can be passed through the common source groove through stack layer in the horizontal direction by the vertical stacking of a memory device
It separates, while forming public source of the filled layer as memory device in common source trench interiors.
However as the increase of storage density, the size of memory device is smaller and smaller, in memory device between each conductive layer
Distance also with reduction, cause the parasitic capacitance between conductive layer to increase with it, for example, grid and drain electrode between parasitism electricity
Hold, the parasitic capacitance between grid and grid, the parasitic capacitance between grid and source electrode.Parasitic capacitance between these conductive layers
Memory device be will result directly in biggish RC delay effect, influence device performance.
Based on the above technical problem, the embodiment of the present application provides a kind of 3D nand memory part and its manufacturing method, has
Effect reduces the parasitic capacitance between the filled layer in grid and common source groove, to reduce the RC delay effect of memory device
It answers, improves device performance.Specifically, grid layer and the alternately stacked stack layer of insulating layer has been formed on the substrate and through heap
The common source groove of lamination is formed with filled layer and wall in common source groove, and the wall is located at the stack layer
Between filled layer, the wall between stack layer and filled layer is removed, sidewall spacers can be formed, in the sidewall spacers
Sidewall dielectric layers are formed, are formed with air gap in the sidewall dielectric layers, since the dielectric constant of air is smaller, then grid layer and are filled out
The parasitic capacitance filled between layer is smaller, to reduce the RC retardation ratio of memory device, improves device performance.
In order to make it easy to understand, with reference to the accompanying drawing to a kind of 3D nand memory part provided by the embodiments of the present application and its
Manufacturing method is described in detail.A kind of system of 3D nand memory part provided by the embodiments of the present application is shown with reference to Fig. 1
The flow chart of method is made, this method may comprise steps of.
S101 provides substrate 100, and grid layer 110 and the alternately stacked stack layer of insulating layer 120 are formed on substrate 100,
And the common source groove 130 through stack layer, filled layer 150 and wall 140 are formed in common source groove 130,
Interlayer 140 is between stack layer and filled layer 150, with reference to shown in Fig. 2.
In the embodiment of the present application, substrate 100 is semiconductor substrate, such as can be Si substrate, Ge substrate, SiGe lining
Bottom, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..In other embodiments, the semiconductor substrate can also be include other elements semiconductor or compound
The substrate of semiconductor, such as GaAs, InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can also be other
Epitaxial structure, such as SGOI (silicon germanium on insulator) etc..Refering to what is shown in Fig. 2, in the present embodiment, substrate 100 is monocrystalline silicon lining
Bottom is used to support device architecture on it.
It, can be first in substrate in order to form grid layer 110 and the alternately stacked stack layer of insulating layer 120 on substrate 100
Upper formation sacrificial layer (not shown go out) and the alternately stacked stack layer of insulating layer 120, wherein sacrificial layer can be silicon nitride, insulate
Layer 120 can be silica.The number of plies of stack layer determines the number of the storage unit in vertical direction, for example, can for 8 layers,
32 layers, 64 layers etc., the number of plies is more, and the integrated level of device is higher.It can be using chemical vapor deposition, atomic layer deposition or other conjunctions
Suitable deposition method, successively alternating deposit sacrificial layer and insulating layer 120, form stack layer.
After forming sacrificial layer and the alternately stacked stack layer of insulating layer 120, formation can be etched on stack layer and is run through
The channel structure 160 of stack layer and exposure substrate, and accumulation layer is formed in channel structure 160, accumulation layer includes charge-trapping
Layer and channel layer, charge-trapping can be oxide-nitride-oxide-polysilicon-oxide layer by layer, and channel layer can be
Polysilicon can also be adjusted according to the actual situation.
After forming accumulation layer in channel structure 160, the common source to be formed through stack layer can be performed etching to stack layer
Pole groove 130, specifically, can on stack layer spin coating photoresist layer, pass through exposure development and form patterned light
Photoresist layer, the pattern of the photoresist layer is by being used to form the mask plate of common source groove in 3D nand memory manufacturing process
It determines, is masking with the patterned photoresist layer, etching stack layer forms the common source groove 130 of exposed substrate, etching
Method can use RIE (reactive ion etching), other suitable etching modes also can be used, and finally remove photoresist layer simultaneously
Carry out the cleaning of chip.
After forming common source groove 130, the sacrificial layer in stack layer is exposed in common source groove 130, can be with
Sacrificial layer in removal stack layer removes to form hollowed out area, specifically, insulating layer 120 is silica, sacrificial layer is silicon nitride
When, it can be carried out by the acid solution to silicon nitride and the high selectivity ratio of silica, such as usually phosphoric acid (H3PO4), later to acid
Liquid is cleaned.
After removing sacrificial layer, grid layer 110 can be formed in the hollowed out area of formation, to pass through grid layer 110
Original sacrificial layer is replaced, to form upper selecting pipe (the Top Selective of multiple memory cell transistors in memory block
Gate, TSG) grid, source selection area under control formed lower selecting pipe (Bottom Selective Gate, a BSG) grid,
String select transistor grid is formed in string selection area under control.
Specifically, the deposition of gate layer material can be carried out first, it is filled with gate layer material between such insulating layer, right
Gate layer material carve, and exists only in gate layer material in the hollowed out area formed after removal sacrificial layer, specific implementation
When, gate layer material can be recessed on the direction for be parallel to substrate surface relative to insulating layer, grid layer 110 is constituted,
I.e. insulating layer 120 protrudes from grid layer 110.When it is implemented, gate layer material can be tungsten, to the Hui Keke of gate layer material
To use the mixed solution of acid solution and organic solvent, in order to remove influence of the residual solution to grid layer, after returning quarter, may be used also
To carry out the cleaning on 130 surface of common source groove.Certainly, gate layer material is also possible to other metals that can do grid,
This is without limitation.
After removing grid line sacrificial layer, dielectric layer 170 can also be formed on the surface of hollowed out area, for separating insulating layer
120 and hollowed out area in the grid layer 110 that is formed, specifically, dielectric layer 170 be formed in grid layer 110 and insulating layer 120 it
Between, side of the grid layer 110 towards channel structure 160 is also covered, with reference to shown in Fig. 2.The presence of dielectric layer 170 can be to avoid grid
The atom of pole layer 110 is diffused into insulating layer 120, is equivalent to and is formed protective effect to insulating layer 120.Dielectric layer 170 can be
By at least one of transition metal (for example, titanium or tantalum) and the metal nitride (for example, titanium nitride or tantalum nitride) of conduction structure
At.Specifically, can be with deposition medium layer material, and remove the dielectric layer of 130 bottom of 120 side wall of insulating layer and common source groove
Material forms dielectric layer 170.
By above step, so that it may form grid layer 110 and the alternately stacked stack layer of insulating layer 120 and through heap
The common source groove 130 of lamination.When it is implemented, the grid layer 110 in common source groove 130 can be relative to insulating layer 120
Constitute concave inward structure.
It, can also be sudden and violent in common source groove 130 after forming grid layer 110 and the alternately stacked stack layer of insulating layer 120
Wall 140 is formed on the side wall of dew.Specifically, the material of wall 140 can be oxide；Such as silica, wall
140 material is also possible to organic material, such as silicon rubber or silane etc.；When grid layer 110 is tungsten layer, wall 140
Material may be polysilicon.The deposition of wall 140 can be carried out using CVD (chemical vapor deposition), can also be using original
Sublayer depositional mode, or it is also possible to other depositional modes, after depositing spacer material, etches and remove common source groove
The material spacer layer of 130 bottom surfaces forms wall 140.
After forming wall 140, filled layer 150 can also be formed in common source groove 130, filled layer 150 can be with
As public source, and wall 140 separates filled layer 150 and stack layer, with reference to shown in Fig. 2.Filled layer 150 can be gold
Belong to and/or polysilicon, metal for example can be tungsten, doped region can also be formed in the bottom of common source groove 130, formation
Filled layer 150 is connect with doped region, therefore the filled layer 150 in common source groove 130 can also play common source (common
Source effect).
S102 removes wall 140 to form sidewall spacers 180, with reference to shown in Fig. 3.
Wall 140 is formed between filled layer 150 and stack layer, can be in 140 He of wall after removal wall 140
The formation sidewall spacers 180 of stack layer, with reference to shown in Fig. 3.
When wall 140 is oxide, removal wall 140 can be by way of wet etching, such as can pass through
Acid system removes wall 140, specifically, can remove wall 140 by hydrofluoric acid.When wall 140 is organic material,
Wall 140 can be removed by way of heat treatment.When wall 140 is polysilicon, can also be removed by aqueous slkali
Wall 140, such as wall 140 can be removed by ammonium hydroxide.
In the embodiment of the present application, stack layer can also include the lower selecting pipe bsg layer of bottom, in the embodiment of the present application,
When removing wall 140, the wall on the side wall of the stack layer 150 of bsg layer or more can also be only removed, retains bsg layer
The wall of side wall, so that only sidewall spacers are formed between the stack layer more than bsg layer and filled layer 150, with reference to Fig. 3 institute
Show.
Specifically, the time of contact that can control acid solution and wall comes in acid system or aqueous slkali removal wall 140
Control removal progress.Wall on the bsg layer side wall of reservation is conducive to keep the three-dimensional structure of stack layer and filled layer 150,
The oxide layer below bsg layer can also be protected not by acid solution or alkali soluble corrosion simultaneously, in order to avoid influence the performance of BSG.?
When interlayer 140 is organic material, wall 140 can be removed by way of heat treatment, since heat treatment will not influence under BSG
The oxide layer of side, can not retain the wall on BSG side wall.
S103 forms sidewall dielectric layers 190 in sidewall spacers 180, is formed with air gap 200 in sidewall dielectric layers 180, joins
It examines shown in Fig. 4.
In the embodiment of the present application, air gap 200 is formed in the sidewall dielectric layers between stack layer and filled layer 150, and it is empty
The dielectric constant of gas is smaller, then the parasitic capacitance between the grid layer 110 in stack layer and filled layer 150 is smaller, in such manner, it is possible to
Effectively reduce the parasitic capacitance between the grid of memory device and source electrode.
Sidewall dielectric layers 190 can be oxide layer, is also possible to the dielectric layer of other dielectric materials composition, does not limit herein
It is fixed.
Sidewall dielectric layers 190 are formed in sidewall spacers, can be realized by deposited sidewalls dielectric layer 190.Deposit side
Wall dielectric layer 190 can pass through chemical vapor deposition manner or atomic layer deposition mode, the more uniform life of sidewall dielectric layers 190
The side wall in stack layer and filled layer 150 is grown, sidewall dielectric layers 190 are formed.In practical operation, the sidewall dielectric layers 190 of deposition
It generally can not uniformly be grown on the side wall of stack layer and filled layer 150, in fact, close to 130 bottom of common source groove
The sidewall dielectric layers 190 of position, formation can be relatively thin, in this way, the side on the stack layer side wall on top and on 150 side wall of filled layer
When the thickness of wall dielectric layer 190 is respectively the half of the distance of stack layer and filled layer 150, sidewall dielectric layers 190 start to contact,
The continued growth of the sidewall dielectric layers 150 in sidewall spacers has been blocked, and has been located on the stack layer side wall of bottom, common source ditch
Sidewall dielectric layers 190 on 150 side wall of 130 bottom of slot and filled layer are relatively thin, do not constitute contact, therefore form side wall and be situated between
Air gap 200 in electric layer.
In the embodiment of the present application, insulating layer can protrude from grid layer along the direction for being parallel to substrate surface, this
When sidewall dielectric layers 190 of the sample on 150 surface of sidewall dielectric layers 190 and filled layer on 120 surface of insulating layer contact, side wall dielectric
The half of the distance with a thickness of insulating layer 120 and filled layer 150 of layer 190, and grid layer 110 is constituted relative to insulating layer 120
Concave inward structure, relatively far away from, then the sidewall dielectric layers 190 of same thickness are not for the distance between grid layer 110 and filled layer 150
It is enough to fill up the gap of grid layer 110 and filled layer 150, therefore air can be formed between grid layer 110 and filled layer 150
Gap 200.
In practical operation, sidewall dielectric layers 190 generally can not uniformly be grown in the side wall of stack layer and filled layer 150
On, in fact, the sidewall dielectric layers 190 of formation can be relatively thin, therefore, in top layer close to the position of 130 bottom of common source groove
120 surface of insulating layer 150 surface of sidewall dielectric layers 190 and filled layer sidewall dielectric layers 190 contact when, positioned at lower layer
The sidewall dielectric layers 190 on 150 surface of sidewall dielectric layers 190 and filled layer on 120 surface of insulating layer and not in contact with grid layer 110
The sidewall dielectric layers 190 on 150 surface of sidewall dielectric layers 190 and filled layer on surface are also not in contact with therefore can forming more substantially
Long-pending the air gap 200, with reference to shown in Fig. 4.
After deposited sidewalls dielectric layer, the sidewall dielectric layers of stack layer upper surface can be removed, specifically, can carry out flat
Smoothization processing, flushes sidewall dielectric layers and stack layer.
In a kind of manufacturing method of 3D nand memory part provided by the embodiments of the present application, grid has been formed on the substrate
Layer and the alternately stacked stack layer of insulating layer and the common source groove through stack layer are formed with filled layer in common source groove
And wall, the wall remove the interval between stack layer and filled layer between the stack layer and filled layer
Layer, can form sidewall spacers, form sidewall dielectric layers in the sidewall spacers, be formed with gas in the sidewall dielectric layers
Gap, since the dielectric constant of air is smaller, then the parasitic capacitance between grid layer and filled layer is smaller, to reduce memory device
RC retardation ratio, improve device performance.
Based on the manufacturing method of the above 3D nand memory part, the embodiment of the present application also provides a kind of 3D NAND storages
Device, refering to what is shown in Fig. 4, the memory device includes:
Substrate 100；
Stack layer on the substrate 100 and the common source groove 130 through the stack layer, the stack layer include
Alternately stacked grid layer 110 and insulating layer 120 are filled with filled layer 150 and side wall dielectric in the common source groove 130
Layer, the sidewall dielectric layers are formed with air gap between the filled layer and grid layer.
Optionally, the stack layer includes the BSG of bottom, is formed with wall 140 on the bsg layer side wall.
Optionally, the filled layer 150 is metal layer and/or polysilicon layer.
Optionally, dielectric layer is formed between the grid layer 110 and the insulating layer 120, the dielectric layer also covers
Side of the grid layer towards channel structure, the channel structure run through the stack layer.
Optionally, the insulating layer is protruding from the grid layer along the direction for being parallel to the substrate surface.
In a kind of 3D nand memory part provided by the embodiments of the present application, grid layer and insulating layer has been formed on the substrate
Alternately stacked stack layer and common source groove through stack layer are formed with filled layer in common source groove and side wall are situated between
Electric layer, sidewall dielectric layers are formed with air gap between the filled layer and stack layer, due to air dielectric constant compared with
Small, then the parasitic capacitance between grid layer and filled layer is smaller, to reduce the RC retardation ratio of memory device, improves device performance.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and the highlights of each of the examples are differences from other embodiments.Especially for memory
For part embodiment, since it is substantially similar to the method embodiment, so describing fairly simple, related place is referring to method reality
Apply the part explanation of example.
The above is only the preferred embodiment of the application, although the application has been disclosed in the preferred embodiments as above, so
And it is not limited to the application.Anyone skilled in the art is not departing from technical scheme ambit
Under, many possible changes and modifications all are made to technical scheme using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, all contents without departing from technical scheme, according to the application's
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within present techniques side
In the range of case protection.
Claims (12)
1. a kind of manufacturing method of 3D nand memory part, which is characterized in that the described method includes:
Substrate is provided, grid layer and the alternately stacked stack layer of insulating layer are formed on the substrate, and run through the stacking
The common source groove of layer is formed with filled layer and wall in the common source groove, and the wall is located at the stacking
Between layer and filled layer；
The wall is removed to form sidewall spacers；
Sidewall dielectric layers are formed in the sidewall spacers, are formed with air gap in the sidewall dielectric layers.
2. the method according to claim 1, wherein the removal wall is wrapped with forming sidewall spacers
It includes: removing the wall using acid system, or remove the wall using heat treatment mode, or by described in aqueous slkali removal
Wall.
3. the method according to claim 1, wherein described form sidewall dielectric layers in the sidewall spacers,
It include: by chemical vapor deposition manner or atomic layer deposition mode deposited sidewalls dielectric layer.
4. method according to claim 1 to 3, which is characterized in that the stack layer includes the lower selection of bottom
Pipe bsg layer, the removal wall is to form sidewall spacers, comprising: removal is located at the stack layer of the bsg layer or more
Wall on side wall is to form sidewall spacers.
5. method according to claim 1 to 3, which is characterized in that the filled layer is metal layer and/or more
Crystal silicon layer.
6. method according to claim 1 to 3, which is characterized in that between the grid layer and the insulating layer
It is formed with dielectric layer, the dielectric layer also covers side of the grid layer towards channel structure, and the channel structure runs through institute
State stack layer.
7. method according to claim 1 to 3, which is characterized in that the insulating layer is parallel to the lining on edge
The grid layer is protruded from the direction of bottom surface.
8. a kind of 3D nand memory part characterized by comprising
Substrate；
Stack layer on the substrate and the common source groove through the stack layer, the stack layer include alternately stacked
Grid layer and insulating layer, filled layer and sidewall dielectric layers are filled in the common source groove, and the sidewall dielectric layers are located at
Between the filled layer and stack layer, and it is formed with air gap.
9. memory device according to claim 8, which is characterized in that the stack layer includes the lower selecting pipe BSG of bottom
Layer, wall is formed on the bsg layer side wall.
10. memory device according to claim 8 or claim 9, which is characterized in that the filled layer is metal layer and/or polycrystalline
Silicon layer.
11. memory device according to claim 8 or claim 9, which is characterized in that shape between the grid layer and the insulating layer
At there is dielectric layer, the dielectric layer also covers side of the grid layer towards channel structure, and the channel structure is through described
Stack layer.
12. memory device according to claim 8 or claim 9, which is characterized in that the insulating layer is parallel to the substrate on edge
The grid layer is protruded from the direction on surface.
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| CN111758159A (en) * | 2020-05-25 | 2020-10-09 | 长江存储科技有限责任公司 | Memory device and method of forming the same |
| CN111758159B (en) * | 2020-05-25 | 2021-04-27 | 长江存储科技有限责任公司 | Memory device and method of forming the same |
| US11239247B2 (en) | 2020-05-25 | 2022-02-01 | Yangtze Memory Technologies Co., Ltd. | Memory device and method for forming the same |
| WO2023236243A1 (en) * | 2022-06-07 | 2023-12-14 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
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