CN109411475A - Memory and forming method thereof - Google Patents

Memory and forming method thereof Download PDF

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Publication number
CN109411475A
CN109411475A CN201811335682.6A CN201811335682A CN109411475A CN 109411475 A CN109411475 A CN 109411475A CN 201811335682 A CN201811335682 A CN 201811335682A CN 109411475 A CN109411475 A CN 109411475A
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layer
stressor layers
memory according
contact portion
source contact
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CN201811335682.6A
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CN109411475B (en
Inventor
姚兰
吕震宇
胡禺石
陈俊
郭美澜
方原
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The present invention relates to a kind of memory and forming method thereof, the memory includes: substrate, and the substrate surface is formed with storage stack structure, and the storage stack structure includes the insulating layer being alternately stacked and control gate structure sheaf；Through the common source contact portion of the storage stack structure；Separation layer between the storage stack structure and the common source contact portion, the separation layer include at least one layer of dielectric layer that F can be stopped to spread.The performance of the memory is improved.

Description

Memory and forming method thereof
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of memory and forming method thereof.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill Art is rapidly developed.
In 3D NAND flash memory structure, the memory array structure including being located at substrate surface, the memory array structure In, it will form the array common source contact portion through memory array structure.The array common source contact portion and storage array knot Pass through insulator separation between structure.
But in the prior art, the insulating layer between array common source contact portion and memory array structure is easy to be damaged Wound leads to that short circuit occurs between the control grid in the array common source contact portion and memory array structure, leads to memory Reliability decrease.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of memories and forming method thereof, improve the property of memory Energy.
To solve the above problems, technical solution of the present invention provides a kind of memory, comprising: substrate, the substrate surface It is formed with storage stack structure, the storage stack structure includes the insulating layer being alternately stacked and control gate structure sheaf；Through institute State the common source contact portion of storage stack structure；Being isolated between the storage stack structure and the common source contact portion Layer, the separation layer include at least one layer of dielectric layer that F can be stopped to spread.
Optionally, the material of the dielectric layer includes at least one of silicon nitride or aluminium oxide.
Optionally, the dielectric layer with a thickness of 2nm~10nm.
Optionally, the separation layer includes at least one layer of stressor layers adjacent with the dielectric layer, the stressor layers and institute Give an account of the stress that electric layer has opposite direction.
Optionally, the separation layer includes the first stressor layers and the second stressor layers, and the dielectric layer is located at described first and answers Between power layer and the second stressor layers.
Optionally, the material of first stressor layers and the second stressor layers includes silica, silicon nitride, aluminium oxide, nitrogen oxygen At least one of SiClx.
Optionally, the material of the common source contact portion includes tungsten.
Optionally, the part separation layer is prominent to storage stack structure, and contacts with the control gate structure sheaf.
Optionally, source doping region is formed in the substrate, the common source contact portion is connected to the source dopant Area.
Optionally, the memory is 3D nand memory.
To solve the above problems, technical solution of the present invention also provides a kind of forming method of memory, comprising: provide one Substrate；Stacked structure is formed in the substrate surface, the stacked structure includes the insulating layer and sacrificial layer being alternately stacked；It is formed Through the grid line separate slot of the storage stack structure；The sacrificial layer between adjacent insulating layer is removed along the grid line separate slot, and Control gate structure sheaf is formed between adjacent insulating layer；Separation layer is formed in the grid line separate slot sidewall surfaces, the separation layer is extremely It less include one layer of dielectric layer that F can be stopped to spread；Form the common source contact portion for filling the grid line separate slot.
Optionally, the material of the dielectric layer includes at least one of silicon nitride or aluminium oxide.
Optionally, the dielectric layer with a thickness of 2nm~10nm.
Optionally, the separation layer includes at least one layer of stressor layers adjacent with the dielectric layer, the stressor layers and institute Give an account of the stress that electric layer has opposite direction.
Optionally, the separation layer includes the first stressor layers and the second stressor layers, and the dielectric layer is located at described first and answers Between power layer and the second stressor layers.
Optionally, the material of first stressor layers and the second stressor layers includes silica, silicon nitride, aluminium oxide, nitrogen oxygen At least one of SiClx.
It optionally, include F element in the reactant used during forming the common source contact portion.
Optionally, the material of the common source contact portion includes tungsten, is used during forming the common source contact portion Reactant include WF6。
It optionally, further include being etched back to the control gate structure sheaf, so that the grid line before forming the separation layer The side wall of separate slot protrudes from the side of the control gate structure sheaf；The part separation layer protrudes from the side wall of the grid line separate slot And it is contacted with the control gate structure sheaf.
Memory of the invention forms separation layer between storage stack structure together source contact portion, and the separation layer is extremely Less include one layer of dielectric layer that F can be stopped to spread, can be avoided the separation layer by the remaining F in common source contact portion The damage of ion and/or F atom, so that separation layer is with higher always to electrically isolate characteristic.
Detailed description of the invention
Fig. 1 to Fig. 5 is the structural schematic diagram of the memory forming process of the embodiment of the invention；
Fig. 6 is the structural schematic diagram of the memory of the embodiment of the invention；
Fig. 7 to Fig. 8 is the structural schematic diagram of the memory forming process of the embodiment of the invention.
Specific embodiment
It elaborates with reference to the accompanying drawing to the specific embodiment of memory provided by the invention and forming method thereof. In a specific embodiment of the invention, the memory is 3D nand memory.
Referring to FIG. 1, providing substrate 100, stacked structure 110 is formed on 100 surface of substrate.
The substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to the reality of device Demand can choose suitable semiconductor material as the substrate 100, be not limited thereto.In the specific embodiment, institute Stating substrate 100 is monocrystalline silicon wafer crystal.
The stacked structure 110 includes the insulating layer 111 and sacrificial layer being stacked with along 100 surface direction of vertical substrates 112.In a specific embodiment, the material of the insulating layer 111 is silica, and the material of the sacrificial layer 112 is nitrogen SiClx；In other specific embodiments, the insulating layer 111 and sacrificial layer 112 can also use other suitable materials. Chemical vapor deposition process, insulating layer 111 and sacrificial layer 112 described in 100 surface of substrate successively alternating deposit, shape can be used At the stacked structure 110.
It further include the ditch to be formed through stacked structure 110 to 100 surface of substrate after forming the stacked structure 110 Road pore structure, the channel pore structure include the channel hole through stacked structure 110,100 table of substrate positioned at channel hole bottom The epitaxial semiconductor layer 131 in face, and cover the function side wall 132 of channel hole sidewall surfaces, fill the ditch track media in channel hole Layer 133 further includes being located at 133 top of channel dielectric layer, connects the conductive plunger 134 of the function side wall 132.The ditch Road pore structure side wall is connect with the insulating layer 111 and sacrificial layer 112.
It further include that the nut cap for covering the stacked structure 110 and channel pore structure is formed at the top of the stacked structure 110 Layer 120.The material of the cap 120 is silica or other mask materials, for protecting the stacked structure 110.
Referring to FIG. 2, forming the grid line separate slot 200 for running through the storage stack structure 110.
The grid line separate slot 200 is through the stacked structure 110 to 100 surface of substrate.In a specific embodiment party In formula, dry etch process can be used and etch the stacked structure 100 to 200 surface of substrate, the shape in the stacked structure 110 At grid line separate slot 200.In this specific embodiment, it is hung down using reactive plasma etching technics to stacked structure 110 Straight etching, forms the grid line separate slot 200.
200 side wall of grid line separate slot exposes the side wall of the insulating layer 111 and sacrificial layer 112.
It is formed after the grid line separate slot 200, forms source dopant in the substrate 100 of 200 bottom of grid line separate slot Area 201, as the common source between each storage string of memory.
Referring to FIG. 3, the side wall along the grid line separate slot 200 removes the sacrificial layer 112 between adjacent insulating layer 111 (please referring to Fig. 2), and control gate structure sheaf is formed between adjacent insulating layer 111.
The sacrificial layer 112 can be removed using wet-etching technology.In the specific embodiment, the sacrificial layer 112 Material be silicon nitride, the sacrificial layer 112 is etched using phosphoric acid solution.
Due to being formed with channel pore structure, the function side wall of insulating layer 111 and channel pore structure in the stacked structure 110 132, after removing the sacrificial layer 112, the channel pore structure can play a supporting role to insulating layer 111, so that phase There is gap between adjacent insulating layer 111.
After removing the insulating layer 111, control gate structure sheaf is formed in the gap.
The control gate structure sheaf includes gate dielectric layer 301 and the full gap of filling of coverage gap inner wall surface Grid layer 302.Atom layer deposition process can be respectively adopted and form the gate dielectric layer 301 and grid layer 302.It is specific at one In embodiment, the material of the gate dielectric layer 301 is the higher medium materials of dielectric coefficients such as silica, hafnium oxide, zirconium oxide Material；The material of the grid layer 302 is conductive material, including in the conductive materials such as polysilicon, tungsten, titanium nitride, gold, silver or platinum It is at least one.
The control gate structure sheaf and insulating layer 111 being alternately stacked constitute storage stack structure 300.
Referring to FIG. 4, forming separation layer 401 in 200 sidewall surfaces of grid line separate slot, the separation layer 401 is at least wrapped Include one layer of dielectric layer that F can be stopped to spread.
In the specific embodiment, the separation layer 401 only includes the dielectric layer that single layer can stop F (fluorine) to spread, this In the specific embodiment of invention, the F (fluorine) includes at least one of F ion or F atom, and F diffusion includes F ion, F original The diffusion of at least one of son.The material of dielectric layer dielectric coefficient with higher can be used as and electrically isolate layer, and It can not react with F ion and/or F atom or atom exchanges, such as can not react with HF, avoid the corrosion by HF And isolation performance is caused to decline.
In the specific embodiment, the material of the separation layer 401 is silicon nitride.In other specific embodiments, institute The material for stating separation layer 401 can also be aluminium oxide or other dielectric materials.
In a specific embodiment of the invention, the thickness of the separation layer 401 can be 2nm~10nm.The isolation The thickness of layer 401 can be adjusted according to the dielectric coefficient of the material of use, so that the separation layer 401 is with enough Electric isolation performance.The separation layer 401 can be formed using atom layer deposition process, so as to accurately control the isolation Layer 401 deposition thickness and make the separation layer 401 step coverage with higher.
In other specific embodiments, the separation layer 401 can also include can stop for two layers or more F ion and/ Or the dielectric layer of F atom diffusion, such as the separation layer 401 is the composite layer for including silicon nitride layer and alumina layer.It is given an account of Electric layer material usually requires have higher chemical stability, and consistency can be avoided and react with F atom or ion, from And F is stopped to spread into separation layer 401.
Referring to FIG. 5, forming the common source contact portion 500 for filling the grid line separate slot 200 (please referring to Fig. 4).
500 bottom of common source contact portion is connect with the source doping region 201.The common source contact portion 500 is Conductive material, the separation layer 401 is as the grid layer 302 and the common source contact portion 500 in the control gate structure sheaf Between electrically isolate layer, avoid that short circuit problem occurs between the common source contact portion 500 and the grid layer 302.
The common source contact portion 500 is formed using chemical vapor deposition process or atom layer deposition process.The common source The material of pole contact portion 500 is usually W, during the deposition process, generallys use WF6As forerunner's reactant, in deposition process, meeting Generate the by-products containing F such as HF.During forming common source contact portion, since the depth of the grid line separate slot 200 is larger, meeting The defects of hole is generated inside the common source contact portion 500, will lead to WF6And/or HF etc. is deposited in the common source and connects Inside contact portion 500.In other specific embodiments, the common source contact portion 500 or other conductive materials, and During forming common source contact portion 500, other precursor gas containing F can be also used, will cause common source contact portion 500 Interior residual F atom and/or F ion and/or F atom, F atom and/or F ion and/or F atom are easy to spread to outside.
Since the separation layer 401 includes at least one layer of dielectric layer that F ion and/or F atom can be stopped to spread, because This, the dielectric layer can stop the diffusion of the F atom and/or F ion, the isolation characteristic of the separation layer 401 is kept, from And avoid that short circuit problem occurs between the common source contact portion 500 and grid layer 302, to improve the property of the memory of formation Energy.
In other specific embodiments, the separation layer can also lack one layer of stressor layers, the stress of the stressor layers Direction is opposite with the stress direction of dielectric layer.
Referring to FIG. 6, in another embodiment of the present invention, the common source contact portion 500 and storage stack Separation layer between structure 300 including the first stressor layers 601, the second stressor layers 602 and is located at 601 and of the first stressor layers Dielectric layer 603 between second stressor layers 602, the dielectric layer 603 can stop F ion and/or F atom to spread.
The material of the dielectric layer 603 is with higher compared with the isolated materials such as silica commonly used in the prior art Stress in order to avoid the stress of dielectric layer 603 leads to problems such as the structure of memory that warpage occurs, and further increases described The isolation performance of separation layer, in the specific embodiment, the separation layer further includes the first stressor layers 601 and the second stressor layers 602, the stress and 603 stress direction of dielectric layer of first stressor layers 601 and the second stressor layers 602 are on the contrary, to offset The stress of the dielectric layer 603.First stressor layers 601 and the second stressor layers 602 are insulating materials, are included at least At least one of silica, silicon nitride, aluminium oxide, silicon oxynitride.It can be by adjusting first stressor layers 601, second The formation process of stressor layers 602 and dielectric layer 603, to adjust stress intensity and the direction in respective material layer.
In the specific embodiment, the material of first stressor layers 601 and the second stressor layers 602 is silica, institute The material for giving an account of electric layer 603 is silicon nitride.
In another specific embodiment, the material of first stressor layers 601 and the second stressor layers 602 and the dielectric The material of layer 603 is identical, is silicon nitride.But the formation process of first stressor layers 601 and the second stressor layers 602 is joined Number is different with the formation technological parameter of dielectric layer 603 so that first stressor layers 601 and the second stressor layers 602 with given an account of Electric layer 603 has different consistency and stress.
In other specific embodiments, the materials of first stressor layers 601 and the second stressor layers 602 can be identical or not Together, at least one of silica, silicon nitride, aluminium oxide, silicon oxynitride are respectively included.
Fig. 7 to Fig. 8 is please referred to, for the structural schematic diagram of the memory forming process of another specific embodiment of the present invention.
Referring to FIG. 7, being etched back to the control gate structure sheaf in Fig. 3 structure basis, an opening 701 is formed.It is described to open The a part of mouth 701 as grid line separate slot 200, so that the side wall of the grid line separate slot 200 protrudes from the control gate structure sheaf Side.
Specifically, being etched back to the grid layer 302 in the control gate structure sheaf, shape in the specific embodiment At the opening 701.The depth of the opening 701 can be 10nm~30nm.It can be using wet-etching technology to the grid Pole layer 302 is etched back.
Referring to FIG. 8, separation layer 800 is formed in the side wall of the grid line separate slot 200 and the opening 701, and Fill the common source contact portion 801 of the full grid line separate slot 200.
The part separation layer 800 is filled in the opening 701, and the part separation layer 800 protrudes from the grid line The side wall of separate slot is simultaneously contacted with the control gate structure sheaf so that between the common source contact portion 801 and grid layer 302 every 800 thickness of absciss layer is larger, can be improved the electric isolution performance of the common source contact portion 801 and grid layer 302.
A specific embodiment of the invention also provides a kind of memory formed using the above method.The memory is 3D Nand memory.
Referring to FIG. 5, the structural schematic diagram of the memory for one specific embodiment of invention.
The memory includes: substrate 100, and 100 surface of substrate is formed with storage stack structure 300, the storage Stacked structure 300 includes the insulating layer 111 and control gate structure sheaf being alternately stacked；Through the common source of the storage stack structure Contact portion 500；Separation layer 401 between the storage stack structure 300 and the common source contact portion 500, it is described every Absciss layer 401 includes at least one layer of dielectric layer that F ion and/or F atom can be stopped to spread.
The substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to the reality of device Demand can choose suitable semiconductor material as the substrate 100, be not limited thereto.In the specific embodiment, institute Stating substrate 100 is monocrystalline silicon wafer crystal.
The material of the insulating layer 111 is silica, and the control gate structure sheaf includes gate dielectric layer 301 and grid layer 302.The material of the gate dielectric layer 301 is the higher dielectric materials of dielectric coefficients such as silica, hafnium oxide, zirconium oxide；It is described The material of grid layer 302 is conductive material, including at least one in the conductive materials such as polysilicon, tungsten, titanium nitride, gold, silver or platinum Kind.
Channel pore structure is also formed in the storage stack structure 300, the channel pore structure includes running through memory heap The channel hole of stack structure 300, positioned at channel hole bottom 100 surface of substrate epitaxial semiconductor layer 131, and covering channel hole The function side wall 132 of sidewall surfaces, the channel dielectric layer 133 for filling channel hole further include being located at the channel dielectric layer 133 to push up Portion connects the conductive plunger 134 of the function side wall 132.The channel pore structure side wall and the insulating layer 111 and control gate Structure sheaf connection.
It further include the cap 120 for covering the storage stack structure 300 and channel pore structure.The cap 300 Material is silica or other mask materials, for protecting the storage stack structure 300.
In the specific embodiment, the separation layer 401 only includes that single layer can stop F ion and/or F atom to spread Dielectric layer.The material of dielectric layer dielectric coefficient with higher can be used as and electrically isolate layer, and can not be with F ion And/or F atom reacts or atom exchange, such as can not react with HF, avoids the corrosion by HF and causes to be isolated Performance decline.
In the specific embodiment, the material of the separation layer 401 is silicon nitride.In other specific embodiments, institute The material for stating separation layer 401 can also be aluminium oxide or other dielectric materials.
In a specific embodiment of the invention, the thickness of the separation layer 401 can be 2nm~10nm.The isolation The thickness of layer 401 can be adjusted according to the dielectric coefficient of the material of use, so that the separation layer 401 is with enough Electric isolation performance.
In other specific embodiments, the separation layer 401 can also include can stop for two layers or more F ion and/ Or the dielectric layer of F atom diffusion, such as the separation layer 401 is the composite layer for including silicon nitride layer and alumina layer.It is given an account of Electric layer material usually requires have higher chemical stability, and consistency can be avoided and react with F atom or ion, from And F is stopped to spread into separation layer 401.
There is source doping region 201,500 bottom of common source contact portion and the source dopant in the substrate 100 Area 201 connects.The common source contact portion 500 is conductive material, and the separation layer 401 is as in the control gate structure sheaf Electrically isolate layer between grid layer 302 and the common source contact portion 500, avoid the common source contact portion 500 with it is described Short circuit problem occurs between grid layer 302.
The common source contact portion 500 is in forming process, it will usually use forerunner's reactant containing F, be easy in common source F atom and/or F atom are remained in pole contact portion 500.In a specific embodiment, the material of the common source contact portion 500 Material includes W, and forerunner's reactant is WF6.The separation layer 401, which includes at least one layer, can stop F ion and/or F atom to spread Dielectric layer, therefore, the dielectric layer can stop the diffusion of the F atom and/or F ion, keep the separation layer 401 Isolation characteristic, to avoid that short circuit problem occurs between the common source contact portion 500 and grid layer 302, to improve to be formed Memory performance.
In other specific embodiments, the separation layer can also lack one layer of stressor layers, the stress of the stressor layers Direction is opposite with the stress direction of dielectric layer.
Referring to FIG. 6, the structural schematic diagram of the memory for another specific embodiment of the present invention.
In the specific implementation embodiment, the storage stack structure 300 separation layer between source contact portion 500 together Including the first stressor layers 601, the second stressor layers 602 and between first stressor layers 601 and the second stressor layers 602 Dielectric layer 603, the dielectric layer 603 can stop F ion and/or F atom to spread.
The material of the dielectric layer 603 is with higher compared with the isolated materials such as silica commonly used in the prior art Stress in order to avoid the stress of dielectric layer 603 leads to problems such as the structure of memory that warpage occurs, and further increases described The isolation performance of separation layer, in the specific embodiment, the separation layer further includes the first stressor layers 601 and the second stressor layers 602, the stress and 603 stress direction of dielectric layer of first stressor layers 601 and the second stressor layers 602 are on the contrary, to offset The stress of the dielectric layer 603.First stressor layers 601 and the second stressor layers 602 are insulating materials, are included at least At least one of silica, silicon nitride, aluminium oxide, silicon oxynitride.It can be by adjusting first stressor layers 601, second The formation process of stressor layers 602 and dielectric layer 603, to adjust stress intensity and the direction in respective material layer.
In the specific embodiment, the material of first stressor layers 601 and the second stressor layers 602 is silica, institute The material for giving an account of electric layer 603 is silicon nitride.
In another specific embodiment, the material of first stressor layers 601 and the second stressor layers 602 and the dielectric The material of layer 603 is identical, is silicon nitride, but has different consistency and stress.
In other specific embodiments, the materials of first stressor layers 601 and the second stressor layers 602 can be identical or not Together, at least one of silica, silicon nitride, aluminium oxide, silicon oxynitride are respectively included.
Referring to FIG. 8, the structural schematic diagram of the memory for another specific embodiment of the present invention.
In the specific embodiment, the storage stack structure 300 is formed with separation layer between source contact portion 801 together 800.And the distance between source contact portion 801 is greater than the source contact portion together of insulating layer 111 to 302 side wall of grid layer together The distance between 801, so that 800 part of the separation layer is between adjacent insulating layer 111, it is prominent to storage stack structure Out, and with the control gate structure sheaf it contacts.
800 thickness of separation layer between the common source contact portion 801 and grid layer 302 is larger, can be improved described total The electric isolution performance of source contact portion 801 and grid layer 302.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as Protection scope of the present invention.

Claims (19)

1. a kind of memory characterized by comprising
Substrate, the substrate surface are formed with storage stack structure, and the storage stack structure includes the insulating layer being alternately stacked With control gate structure sheaf；
Through the common source contact portion of the storage stack structure；
Separation layer between the storage stack structure and the common source contact portion, the separation layer include at least one layer The dielectric layer that F can be stopped to spread.
2. memory according to claim 1, which is characterized in that the material of the dielectric layer includes silicon nitride or aluminium oxide At least one of.
3. memory according to claim 1, which is characterized in that the dielectric layer with a thickness of 2nm~10nm.
4. memory according to claim 1, which is characterized in that the separation layer include it is adjacent with the dielectric layer extremely A few ply stress layer, the stressor layers and the dielectric layer have the stress of opposite direction.
5. memory according to claim 4, which is characterized in that the separation layer includes the first stressor layers and the second stress Layer, the dielectric layer is between first stressor layers and the second stressor layers.
6. memory according to claim 4, which is characterized in that the material packet of first stressor layers and the second stressor layers Include at least one of silica, silicon nitride, aluminium oxide, silicon oxynitride.
7. memory according to claim 1, which is characterized in that the material of the common source contact portion includes tungsten.
8. memory according to claim 1, which is characterized in that the part separation layer is prominent to storage stack structure, And it is contacted with the control gate structure sheaf.
9. memory according to claim 1, which is characterized in that source doping region is formed in the substrate, it is described total Source contact portion is connected to the source doping region.
10. memory according to claim 1, which is characterized in that the memory is 3D nand memory.
11. a kind of forming method of memory characterized by comprising
One substrate is provided；
Stacked structure is formed in the substrate surface, the stacked structure includes the insulating layer and sacrificial layer being alternately stacked；
Form the grid line separate slot for running through the storage stack structure；
The sacrificial layer between adjacent insulating layer is removed along the grid line separate slot, and forms control grid structure between adjacent insulating layer Layer；
Separation layer is formed in the grid line separate slot sidewall surfaces, the separation layer includes at least one layer of Jie that F can be stopped to spread Electric layer；
Form the common source contact portion for filling the grid line separate slot.
12. the forming method of memory according to claim 11, which is characterized in that the material of the dielectric layer includes nitrogen At least one of SiClx or aluminium oxide.
13. the forming method of memory according to claim 11, which is characterized in that the dielectric layer with a thickness of 2nm ~10nm.
14. the forming method of memory according to claim 11, which is characterized in that the separation layer includes and given an account of The adjacent at least one layer of stressor layers of electric layer, the stressor layers and the dielectric layer have the stress of opposite direction.
15. the forming method of memory according to claim 14, which is characterized in that the separation layer includes the first stress Layer and the second stressor layers, the dielectric layer is between first stressor layers and the second stressor layers.
16. the forming method of memory according to claim 14, which is characterized in that first stressor layers and second are answered The material of power layer includes at least one of silica, silicon nitride, aluminium oxide, silicon oxynitride.
17. the forming method of memory according to claim 11, which is characterized in that form the common source contact portion It include F element in the reactant used in the process.
18. the forming method of memory according to claim 17, which is characterized in that the material of the common source contact portion Including tungsten, the reactant used during forming the common source contact portion includes WF6。
19. the forming method of memory according to claim 11, which is characterized in that before forming the separation layer, It further include being etched back to the control gate structure sheaf, so that the side wall of the grid line separate slot protrudes from the side of the control gate structure sheaf Face；The part separation layer protrudes from the side wall of the grid line separate slot and contacts with the control gate structure sheaf.
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