CN107731741B - A kind of process improving contact hole plug oxide recess - Google Patents
A kind of process improving contact hole plug oxide recess Download PDFInfo
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- CN107731741B CN107731741B CN201710733200.1A CN201710733200A CN107731741B CN 107731741 B CN107731741 B CN 107731741B CN 201710733200 A CN201710733200 A CN 201710733200A CN 107731741 B CN107731741 B CN 107731741B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
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Abstract
The present invention provides a kind of processes of improvement contact hole plug oxide recess, by the way that wet etching in pre-cleaning processes (DHF+SC1) is replaced with plasma dry etch, caused by the too fast etching so as to avoid the oxide skin(coating) of atom layer deposition process (ALD) deposition generated since ALD oxide is different with PECVD oxide wet etch rate the case where the aggravation of bending (Bowing Profile) pattern of contact hole (Channel Hole)；Simultaneously because the anisotropy feature of plasma dry etch, pre-cleaning processes can effectively be controlled mainly for silicon bottom surface, and it is less for the etching of contact hole side wall, so as to avoid the aggravation of bending (Bowing Profile) pattern of contact hole (Channel Hole), to improve the overall performance of 3D nand flash memory, to improve the overall performance of 3D nand flash memory.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of production methods of 3D NAND flash memory structure, specially
A kind of process improving contact hole plug oxide recess.
Background technique
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges: physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty that encounters of planar flash memory and pursue being produced into for lower unit storage unit
This, a variety of different three-dimensional (3D) flash memories structures are come into being, such as 3D NOR (3D or non-) flash memory and 3D NAND
(3D and non-) flash memory.
Wherein, storage element is used three dimensional pattern stacked in multi-layers using its small size, large capacity as starting point by 3D NAND
It is highly integrated be design concept, produce high unit area storage density, the memory of efficient storage unit performance,
The prevailing technology designed and produced as emerging memory.
However, usually using atomic layer deposition (Atomic Layer in the preparation process of current 3D NAND structure
Deposition, abbreviation ALD) method in contact hole (Channel Hole) be full of oxide, next return carve (Recess
Etch Back) oxide, the partial sidewall of the contact hole is exposed, later the deposit polycrystalline silicon in contact hole
(Poly) to form polysilicon plug (Poly Plug)；As shown in Figure 1, wherein 2 be the medium of oxides such as TEOS layer, 3 be nitrogen
SiClx sacrificial layer, since the longitudinal section of contact hole 1 is generally in bending (Bowing Profile), and wet etching removes (Wet
Etch Recess) partial oxide technique can aggravate generate gap (Seam), this will lead to the polysilicon plug deposited later
It generates gap (Seam), and then influences threshold voltage and sub-threshold slope, this is that those skilled in the art do not expect to see.
It meanwhile in current 3D NAND structure, is mentioned by the way that memory cell is three-dimensionally disposed in substrate
High density of integration, wherein channel layer are stood vertically on substrate, and grid is divided into lower layer's selection gate, middle layer control grid and top
Layer selection gate three parts, by the way that grid signal to be distributed in three groups of gate electrodes to reduce the crosstalk between signal.Wherein, lead to
It often is provided with top layer selection grid tangent line (Top Select Gate Cut) in the middle part of finger memory block, will refer to the top layer of memory block
Selection grid is divided into two parts, and top layer selection grid tangent line is usually formed by oxide material, and uses atomic layer deposition
Technique (ALD) preparation, common preparation process flow include the following steps:
S1: forming multilayer lamination structure, firstly, providing substrate, the substrate surface is formed with the layer of multi-layer intercrossed stacking
Between dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer is formed between adjacent interlayer dielectric layer；Then, using chemical machine
Tool grinding technics obtains the smooth surface of top layer interlayer dielectric layer；
S2: it is performed etching to form top layer selection grid tangent line (Top Select Gate Cut), using conventional etching work
Skill forms the channel of top layer selection grid tangent line (Top Select Gate Cut)；
S3: top layer selection grid tangent line (Top Select Gate Cut) channel is filled, using atomic layer deposition work
Skill (ALD) fills top layer selection grid tangent line oxide material in channels；
S4: deposition plug oxide enhances in the top layer selection grid tangent line oxide material surface using plasma
Vapour deposition process (PECVD) process deposits plug oxide of chemistry, and silicon nitride layer is formed in plug oxide surface.
S5: performing etching to form contact hole (Channel Hole), forms contact hole using conventional etching technics
(Channel Hole), the contact hole pass to the substrate and form the silicon slot of certain depth；
S6: silicon is carried out in the silicon slot is epitaxially-formed silicon epitaxy layer (SEG).
However, in above-mentioned technical process, because of the vapour deposition process (Plasma of using plasma enhancing chemistry
Enhanced Chemical Vapor Deposition, abbreviation PECVD) preparation plug oxide (such as ethyl orthosilicate
TEOS stand density) is high, is not easy by wet etching, in comparison, is selected using the top layer of atom layer deposition process (ALD) preparation
The wet-etch rate for selecting grid tangent line oxide is probably then vapour deposition process (PECVD) system of using plasma enhancing chemistry
2.3 times of standby TEOS layer etch rate, and in the conventional wet lay etching process for forming contact hole (Channel Hole)
In, can't ALD oxide to hole wall and PECVD oxide using protection especially, therefore due to wet etching it is each to
The operational characteristic of the same sex will exacerbate bending (Bowing Profile) feelings of the longitudinal section contact hole (Channel Hole)
Condition, so that the polysilicon plug of subsequent even more serious deposition be caused to generate gap (Seam) (referring to attached drawing 2).
In addition, the etching of silicon nitride (SiN) layer would generally in the technique of above-mentioned contact hole (Channel Hole) etching
Wet etching is carried out using phosphoric acid solution as main component, and often contains more heavy metal element in phosphoric acid solution, this
A little heavy metal elements are easy to be attached to the surface of substrate silicon slot and form the film of surface of silicon and pollute, in order to it is subsequent more
The epitaxial growth of good progress silicon, it is necessary to the prerinse step before carrying out growing epitaxial silicon to the surface of silicon slot, for example, using dilute
Hydrofluoric acid (DHF) come clean removal silicon rooved face natural oxide (Native Oxide), and use SCl solution (often for
H2O2It is formulated with HCl in certain mass concentration ratio) remove the heavy metal element and surface defect of silicon rooved face.But
It is, in prewashed technical process, the use of diluted hydrofluoric acid (DHF) and SCl solution, it will be further exacerbated by contact hole
Bending (Bowing Profile) situation of the longitudinal section (Channel Hole).
Therefore, how to improve the recess of plug oxide (Plug Oxide) caused by etch rate difference as far as possible, thus
Bending (Bowing Profile) situation for improving the longitudinal section contact hole (Channel Hole), is always those skilled in the art
Member endeavours the direction of research.
Summary of the invention
The purpose of the present invention is to provide a kind of improved preparation processes, can be avoided plug caused by etch rate difference
The recess of oxide (Plug Oxide), and then improve the bending (Bowing of the longitudinal section contact hole (Channel Hole)
Profile) situation, to improve the performance of 3D nand flash memory.
To achieve the goals above, the invention proposes it is a kind of improvement contact hole plug oxide recess process,
The following steps are included:
Multilayer lamination structure is formed, firstly, providing substrate, the interlayer that the substrate surface is formed with multi-layer intercrossed stacking is situated between
Matter layer and sacrificial dielectric layer, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；Then, it is ground using chemical machinery
Grinding process obtains the smooth surface of top layer interlayer dielectric layer；
It is performed etching to form top layer selection grid tangent line (Top Select Gate Cut), using conventional etching technics
Form the channel of top layer selection grid tangent line (Top Select Gate Cut)；
Top layer selection grid tangent line (Top Select Gate Cut) channel is filled, specifically, in the channel
Deposition filling top layer selection grid tangent line oxide material；
Plug oxide is deposited, specifically, plug oxide is deposited on the surface of top layer selection grid tangent line oxide material,
And silicon nitride layer is formed in plug oxide surface.
It is performed etching to form contact hole (Channel Hole), contact hole is formed using conventional etching technics
(Channel Hole), the contact hole pass to the substrate and form the silicon slot of certain depth；
Prerinse processing is carried out to the silicon slot, the prerinse is anisotropic etching technics；
Silicon is carried out in the silicon slot is epitaxially-formed silicon epitaxy layer (SEG).
Further, anisotropic etching technics is dry etch process in the prerinse；Preferably, described dry
Method etching technics is plasma etching.
Further, the material of the interlayer dielectric layer and sacrificial dielectric layer is respectively oxide and nitride, preferably
Ethyl orthosilicate (TEOS) and silicon nitride (SiN).
Further, in forming multilayer lamination structure step, the chemical mechanical milling tech (CMP) is grinding rate
Lower chemical mechanical grinding (Buffer CMP).
Further, top layer selection grid tangent line (Top Select Gate Cut) channel is filled, is using atom
Layer depositing operation (ALD) carries out the deposition filling of top layer selection grid tangent line oxide material.
Further, plug oxide is deposited using the vapour deposition process (PECVD) of plasma enhanced chemical.
Compared with prior art, the beneficial effects are mainly reflected as follows:
First, by the way that wet etching in pre-cleaning processes (DHF+SC1) is replaced with plasma dry etch, so as to
Enough avoid the atom layer deposition process (ALD) generated since ALD oxide is different with PECVD oxide wet etch rate heavy
Bending (Bowing Profile) shape of contact hole (Channel Hole) caused by the too fast etching of long-pending oxide skin(coating)
The case where aggravation of looks.
Second, due to the anisotropy feature of plasma dry etch, it can effectively control the main needle of pre-cleaning processes
To silicon bottom surface, and it is less for the etching of contact hole side wall, so as to avoid the curved of contact hole (Channel Hole)
The aggravation of curved (Bowing Profile) pattern, to improve the overall performance of 3D nand flash memory.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 is the structural schematic diagram of contact hole plug oxide in the prior art；
Fig. 2 is the SEM photograph that contact hole bending pattern caused by prior art preparation top layer selection grid tangent line aggravates；
Fig. 3 a-3g is the process flow diagram that top layer selection grid tangent line is prepared in the present invention.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 3 a-g is please referred to, in the present embodiment, proposes a kind of technique side of improvement contact hole plug oxide recess
Method, comprising the following steps:
S100: forming multilayer lamination structure, firstly, providing substrate, the substrate surface is formed with multi-layer intercrossed stacking
Interlayer dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；Then, using chemistry
Mechanical milling tech obtains the smooth surface of top layer interlayer dielectric layer；
S200: it is performed etching to form top layer selection grid tangent line (Top Select Gate Cut), using conventional etching
Technique forms the channel of top layer selection grid tangent line (Top Select Gate Cut)；
S300: top layer selection grid tangent line (Top Select Gate Cut) channel is filled, specifically, described
Deposition filling top layer selection grid tangent line oxide material in channel；
S400: deposition plug oxide, specifically, depositing plug oxygen on the surface of top layer selection grid tangent line oxide material
Compound, and silicon nitride layer is formed in plug oxide surface.
S500: performing etching to form contact hole (Channel Hole), forms contact hole using conventional etching technics
(Channel Hole), the contact hole pass to the substrate and form the silicon slot of certain depth；
S600: prerinse processing is carried out to the silicon slot, the prerinse is anisotropic etching technics；
S700: silicon is carried out in the silicon slot is epitaxially-formed silicon epitaxy layer (SEG).
Specifically, please referring to Fig. 3 a, in the step s 100, multilayer lamination structure is formed on the surface of substrate 100, specifically
Include the following steps, first progress step S110, provides substrate 100,100 surface of substrate is formed with multi-layer intercrossed stacking
Interlayer dielectric layer 110 and sacrificial dielectric layer 120, the sacrificial dielectric layer 120 be formed in adjacent interlayer dielectric layer 110 it
Between, wherein the substrate 100 is silicon substrate, and the interlayer dielectric layer 110 is oxide, preferably ethyl orthosilicate (TEOS),
The sacrificial dielectric layer 120 is nitride, preferably silicon nitride (SiN)；Step S120 is then carried out, using chemical mechanical grinding
Technique (CMP) obtains the smooth surface of top layer interlayer dielectric layer 110, is based on the characteristic of ethyl orthosilicate (TEOS), step
Chemical mechanical milling tech (CMP) in S120 is using the lower chemical mechanical grinding of grinding rate (Buffer CMP).
Fig. 3 b is please referred to, in step s 200, is carried out to form top layer selection grid tangent line (Top Select Gate Cut)
Etching forms the channel 130 of top layer selection grid tangent line (Top Select Gate Cut) using conventional etching process.
Fig. 3 c is please referred to, in step S300, to top layer selection grid tangent line (Top Select Gate Cut) channel 130
It is filled, specifically, deposition filling top layer selection grid tangent line oxide material 140, the deposition use in the channel
Atom layer deposition process (ALD).
Fig. 3 d is please referred to, in step S400, deposits plug oxide, specifically, step S410 is carried out first, in top layer
Plug oxide 150 is deposited on the surface of selection grid tangent line oxide material 140, what the deposition plug oxide 150 used
It is the vapour deposition process (PECVD) of plasma enhanced chemical；Step S420 is then carried out, in 150 surface shape of plug oxide
At silicon nitride layer 160.
Fig. 3 e is please referred to, in step S500, is performed etching to form contact hole (Channel Hole), using routine
Etching technics forms contact hole (Channel Hole) 170, and the contact hole 170 passes to the substrate 100 and forms a depthkeeping
The silicon slot 180 of degree.
Fig. 3 f is please referred to, in step S600, prerinse processing is carried out to the silicon slot, the prerinse is using each to different
The dry etch process of property, preferably plasma etch process.
Fig. 3 g is please referred to, in step S700, silicon is carried out in the silicon slot 180 is epitaxially-formed silicon epitaxy layer
190(SEG)。
To sum up, in the process provided in an embodiment of the present invention for improving contact hole plug oxide recess, by will be pre-
Wet etching (DHF+SC1) replaces with plasma dry etch in cleaning process, so as to avoiding due to ALD oxide and
The too fast quarter of the oxide skin(coating) for atom layer deposition process (ALD) deposition that PECVD oxide wet etch rate is different and generates
Caused by erosion the case where the aggravation of bending (Bowing Profile) pattern of contact hole (Channel Hole)；While by
In the anisotropy feature of plasma dry etch, pre-cleaning processes can be effectively controlled mainly for silicon bottom surface,
And it is less for the etching of contact hole side wall, so as to avoid the bending (Bowing of contact hole (Channel Hole)
Profile) the aggravation of pattern, so that the overall performance of 3D nand flash memory is improved, to improve the whole of 3D nand flash memory
Body performance.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (4)
1. a kind of process for improving contact hole plug oxide recess, comprising the following steps:
Multilayer lamination structure is formed, firstly, providing substrate, the substrate surface is formed with the interlayer dielectric layer of multi-layer intercrossed stacking
And sacrificial dielectric layer, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；Then, using chemical mechanical grinding work
Skill obtains the smooth surface of top layer interlayer dielectric layer；
It performs etching to form top layer selection grid tangent line (Top Select Gate Cut), is formed using conventional etching technics
The channel of top layer selection grid tangent line (Top Select Gate Cut)；
Top layer selection grid tangent line (Top Select Gate Cut) channel is filled, specifically, using atomic layer deposition work
Skill, deposition fills top layer selection grid tangent line oxide material in the channel；
Plug oxide is deposited, specifically, using plasma enhances chemical vapour deposition technique, is aoxidized in top layer selection grid tangent line
The surface of object material deposits plug oxide；
Silicon nitride layer is formed in plug oxide surface；
It is performed etching to form contact hole (Channel Hole), contact hole (Channel is formed using conventional etching technics
Hole), the contact hole passes to the substrate and forms the silicon slot of certain depth；
Prerinse processing is carried out to the silicon slot, the prerinse is plasma dry etch process；
Silicon is carried out in the silicon slot is epitaxially-formed silicon epitaxy layer (SEG).
2. process according to claim 1, it is characterised in that:
The material of the interlayer dielectric layer and sacrificial dielectric layer is respectively oxide and nitride.
3. process according to claim 2, it is characterised in that:
The oxide is ethyl orthosilicate (TEOS), and the nitride is silicon nitride (SiN).
4. process according to claim 1, it is characterised in that:
In forming multilayer lamination structure step, the chemical mechanical milling tech (CMP) is the lower chemical machine of grinding rate
Tool grinds (Buffer CMP).
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| CN108550578B (en) * | 2018-03-26 | 2020-10-02 | 长江存储科技有限责任公司 | Three-dimensional memory manufacturing method |
| CN111244100B (en) | 2018-08-16 | 2022-06-14 | 长江存储科技有限责任公司 | Method for forming structure enhanced semiconductor plug in three-dimensional memory device |
| WO2020206681A1 (en) * | 2019-04-12 | 2020-10-15 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device with deposited semiconductor plugs and methods for forming the same |
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