CN107968050B - Method for etching bottom of channel hole - Google Patents
Method for etching bottom of channel hole Download PDFInfo
- Publication number
- CN107968050B CN107968050B CN201711191821.8A CN201711191821A CN107968050B CN 107968050 B CN107968050 B CN 107968050B CN 201711191821 A CN201711191821 A CN 201711191821A CN 107968050 B CN107968050 B CN 107968050B
- Authority
- CN
- China
- Prior art keywords
- etching
- channel hole
- multilayer
- epitaxial silicon
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000005530 etching Methods 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 229920000642 polymer Polymers 0.000 claims abstract description 33
- 230000001681 protective effect Effects 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 3
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 3
- 229910003910 SiCl4 Inorganic materials 0.000 claims description 3
- 238000003486 chemical etching Methods 0.000 claims description 3
- 239000000178 monomer Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000000992 sputter etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 34
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- 238000003917 TEM image Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention relates to a method for etching the bottom of a channel hole, which specifically comprises the following steps: providing a wafer structure, wherein the wafer structure comprises a substrate and a multilayer stacking structure positioned on the substrate, a channel hole is formed in the multilayer stacking structure, epitaxial silicon grows at the bottom of the channel hole, and a multilayer film structure is deposited on the side wall of the channel hole and the upper surface of the epitaxial silicon; depositing a high polymer protective film on the upper surface of the multilayer stacked structure; etching the bottom of the channel hole until the high polymer protective film is completely consumed; repeating steps b and c at least once; depositing a high polymer protective film on the upper surface of the multilayer stacking structure again; and etching the bottom of the channel hole again until the upper surface of the epitaxial silicon is exposed. By adopting the method of circular etching, the invention can effectively reduce the loss of the hard mask at the top of the channel hole, fully open the epitaxial silicon at the bottom and improve the process window of channel hole etching and subsequent processing.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing processes, in particular to a method for etching the bottom of a channel hole.
Background
With the continuous development of semiconductor technology, memory manufacturing technology has gradually transitioned from a simple planar structure to a more complex three-dimensional structure, and the technical development of three-dimensional memories is one of the mainstream of international research and development.
In the preparation process of the three-dimensional storage, after the etching process of the channel hole is finished, a layer of epitaxial silicon is formed at the bottom of the channel hole through epitaxial growth, then silicon oxide, silicon nitride, silicon oxide, amorphous silicon and a protective oxide film are sequentially deposited on the side wall and the bottom of the channel hole, and then the bottom multilayer film is opened through the etching method of the bottom of the channel hole to be connected to the epitaxial silicon.
For the three-dimensional memory with 64 layers or more, the etching depth-to-width ratio can reach more than 90, which is a dry etching process with ultrahigh depth-to-width ratio, and in order to etch and open the epitaxial silicon at the bottom, an etching program with high bias power is mainly adopted.
As the bottom and top hard masks of the channel hole are made of the same material, and the etching rate of the top is much higher than that of the bottom, the conventional etching method often causes excessive loss of the top hard mask, specifically, as shown in fig. 1, the silicon oxide on the top of the stacked structure is consumed, the silicon nitride on the second top layer is consumed by half, and the epitaxial silicon on the bottom is only partially opened or even not opened, as shown in fig. 2, which results in reduction of the process window of the subsequent process.
Disclosure of Invention
An object of the present invention is to solve at least one of the above problems by providing a method for etching the bottom of a trench hole having a high aspect ratio.
The method for etching the bottom of the channel hole comprises the following steps:
a. providing a wafer structure, wherein the wafer structure comprises a substrate and a multilayer stacking structure positioned on the upper surface of the substrate, a channel hole is arranged in the multilayer stacking structure, the channel hole extends from the upper surface of the multilayer stacking structure to the upper surface of the substrate, epitaxial silicon grows at the bottom of the channel hole, and multilayer film structures are deposited on the side wall of the channel hole and the upper surface of the epitaxial silicon;
b. depositing a high polymer protective film on the upper surface of the multilayer stacked structure;
c. etching the bottom of the channel hole until the high polymer protective film on the upper surface of the multilayer stacking structure is completely consumed;
d. repeating step c and step d alternately at least once.
e. Depositing a high polymer protective film on the upper surface of the multilayer stacking structure again;
f. and etching the bottom of the channel hole again until the multilayer film structure on the upper surface of the epitaxial silicon is broken down and the upper surface of the epitaxial silicon is exposed in the channel hole.
Wherein, the etching method also comprises a step g after the step f: and removing the residual high polymer protective film on the upper surface of the multilayer stacked structure.
Wherein the number of layers of the multilayer stacking structure is more than or equal to 64, and the alternating repetition times of the step b and the step c is more than 5.
Wherein the monomer material of the high polymer protective film is CxFy and SiCl4One or more of (a).
Wherein, the uppermost hard mask of the multilayer stack structure is a silicon oxide layer.
The method for etching the bottom of the channel hole is one of sputter etching, chemical etching or high-density plasma etching.
The multilayer film structure sequentially comprises a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, an amorphous silicon layer and an oxide film layer.
The invention has the following beneficial effects:
the invention can effectively reduce the loss of the hard mask at the top of the channel hole by adopting a circular etching method. Meanwhile, the loss of the top hard mask is reduced in the etching process, so that the thickness of the top hard mask can be reduced, the depth-to-width ratio of etching at the bottom of the trench hole is reduced, and the process window of trench hole etching and subsequent processing can be improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 shows a TEM cross-section of the upper half of a wafer structure after etching according to a conventional process of etching the bottom of a channel hole;
FIG. 2 shows a cross-sectional TEM image of the lower half of the wafer structure after etching according to the trench bottom etching method of the conventional process;
FIG. 3 shows a flow chart of a method for bottom etching of a channel hole according to an embodiment of the invention;
FIGS. 4a to 4e are flow charts illustrating the cross-sectional structure of a wafer structure according to the method for etching the bottom of a channel hole in an embodiment of the present invention;
FIG. 5 shows a cross-sectional TEM image of the upper half of the wafer structure of the method for etching the bottom of a channel hole according to an embodiment of the invention;
FIG. 6 shows a cross-sectional TEM image of the lower half of the wafer structure of the method for bottom etching of a channel hole according to an embodiment of the invention;
wherein, 1, a substrate; 2. a multilayer stack structure; 3. a high polymer protective film; 210. epitaxial silicon; 220. a multilayer film structure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The basic idea of the invention is to perform deposition of a protective film and etching of the bottom of the channel hole alternately on the surface of the multilayer stack of the wafer structure by cycling, so that the epitaxial silicon at the bottom of the channel hole is gradually opened on the premise that the top hard mask of the wafer structure is properly protected.
As shown in fig. 3, the method for etching the bottom of the channel hole of the present invention comprises the following steps:
a. providing a wafer structure, wherein the wafer structure comprises a substrate and a multilayer stacking structure positioned on the upper surface of the substrate, a channel hole is arranged in the multilayer stacking structure, the channel hole extends from the upper surface of the multilayer stacking structure to the upper surface of the substrate, epitaxial silicon grows at the bottom of the channel hole, and multilayer film structures are deposited on the side wall of the channel hole and the upper surface of the epitaxial silicon; b. depositing a high polymer protective film on the upper surface of the multilayer stacked structure; c. etching the bottom of the channel hole until the high polymer protective film on the upper surface is completely consumed; d. alternately repeating steps b and c at least once; e. depositing a high polymer protective film on the upper surface of the multilayer stacking structure again; f. and etching the bottom of the channel hole again, so that the multilayer film structure on the upper surface of the epitaxial silicon is broken down, and the upper surface of the epitaxial silicon is exposed in the channel hole.
The following will specifically explain the manufacturing method of the three-dimensional memory provided by the present invention by way of an embodiment with reference to the drawings, wherein fig. 4a to 4e are flowcharts of the longitudinal sectional structure of the manufacturing method of the present application, and each of fig. 4a to 4e shows the structural change occurring in the corresponding step.
Fig. 4a corresponds to step a of the etching method of the present invention. As shown in fig. 4a, a wafer structure is provided, the wafer structure includes a substrate 1 and a multi-layer stack structure 2, the multi-layer stack structure 2 is located on an upper surface of the substrate 1, the multi-layer stack structure is provided with a channel hole, the channel hole penetrates through the multi-layer stack structure 2 and extends from the upper surface of the multi-layer stack structure 2 to the upper surface of the substrate 1, epitaxial silicon 210 is further grown at a bottom of the channel hole, and a multi-layer film structure 220 is deposited on a sidewall of the channel hole and the upper surface of the epitaxial silicon.
Fig. 4b corresponds to step b of the etching method of the present invention. As shown in fig. 4b, a polymer protective film 3 is deposited on the upper surface of the multilayer stack structure 2, and during the deposition process, a polymer is also deposited on the surface of a part of the multilayer film structure on the surface of the epitaxial silicon, so as to form a polymer thin layer.
Fig. 4c corresponds to step c of the etching method of the present invention. As shown in fig. 4c, the trench hole bottom etching is performed until the polymer protective film 3 is consumed. Since the material composition (including the polymer protective layer, the multilayer film layer and the hard mask) at the top of the wafer structure is basically the same as the material composition (including the polymer film layer and the multilayer film structure) at the surface of the epitaxial silicon at the bottom of the channel hole, the etching generates different degrees of loss on the material at the top of the wafer structure and the material at the surface of the epitaxial silicon. The consumption degree is mainly influenced by the depth of the channel hole, and the etching strength of the bottom of the channel hole is weaker than that of the top material due to the weakening influence of the depth of the channel hole on the etching energy, so that the loss of the material on the surface of the epitaxial silicon is less than that of the top material of the wafer structure. Therefore, when the polymer protective film 3 on the top of the wafer structure is substantially etched, only the polymer thin layer on the epitaxial silicon surface and a part of the film layer in the multi-film structure are broken down.
When the trench hole has a high aspect ratio, and particularly the stack structure is more than 64 layers, the steps of depositing the protective film and etching the bottom of the trench hole, namely step d, need to be repeated for multiple times in a circulating manner, so that the multilayer film structure is gradually etched to reach an imminent breakdown state on the premise that the top layer hard mask is always provided with the protective layer.
Fig. 4d corresponds to step e of the etching method of the present invention. After the cyclic etching, a polymer is finally deposited on the upper surface of the multi-layer stacked structure 2 to form a final polymer protective film, as shown in fig. 4 d. Similarly, during the deposition process, the polymer is deposited on the surface of the multilayer film structure near the breakdown, forming the last polymer thin layer.
Fig. 4e corresponds to step f of the etching method of the present invention. As shown in fig. 4e, after the polymer protective film is deposited for the last time, etching is performed again on the bottom of the channel hole, and the multilayer film structure and the polymer thin layer covering the surface of the multilayer film structure are completely broken down, so that the upper surface of the epitaxial silicon 210 is exposed in the channel hole, and the epitaxial silicon on the bottom is opened.
When the upper surface of the epitaxial silicon is sufficiently exposed and a part of the protective film of the high polymer remains on the multilayer stacked structure, the method of the present invention further comprises a step g of removing the remaining protective film of the high polymer.
Generally, the uppermost hard mask of the multilayer stack structure is made of silicon oxide, the multilayer film structure sequentially includes a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, an amorphous silicon layer and a protective oxide film layer, and the method for etching the bottom of the trench hole is dry etching (SONO ETCH), which may be sputter etching, chemical etching or high-density plasma etching.
Taking a 64-layer stacked structure as an example, the bottom etching method of the present invention is used to etch the bottom of the channel hole. Is selected from CxOne or more of Fy, or CxFyWith SiCl4Or SiCl alone4And depositing a monomer high polymer material, forming a high polymer protective film with a certain thickness each time, then carrying out corresponding etching, and gradually etching the bottom of the trench hole by adopting a cyclic deposition etching method of depositing and etching for multiple times until the etching is successful. After etching, the epitaxial silicon at the bottom of the channel hole of the wafer structure is fully opened, as shown in fig. 5, and simultaneously, the silicon oxide at the top layer of the stacked structure is not consumed, the silicon nitride at the second top layer is not consumed, the etching effect is good, and the influence on the top is small, as shown in fig. 6.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (6)
1. The method for etching the bottom of the channel hole is characterized by comprising the following steps of:
a. providing a wafer structure, wherein the wafer structure comprises a substrate and a multilayer stacking structure positioned on the upper surface of the substrate, a channel hole is arranged in the multilayer stacking structure, the channel hole extends from the upper surface of the multilayer stacking structure to the upper surface of the substrate, epitaxial silicon grows at the bottom of the channel hole, and multilayer film structures are deposited on the side wall surface of the channel hole, the upper surface of the multilayer stacking structure and the upper surface of the epitaxial silicon;
b. depositing a high polymer protective film on the multilayer stack structure and on the surface of the multilayer film structure on the epitaxial silicon;
c. etching the bottom of the channel hole until the high polymer protective film on the surface of the multilayer film structure on the multilayer stack structure is completely consumed;
d. repeating the steps b and c at least once circularly;
e. depositing a high polymer protective film on the surface of the multilayer film structure on the multilayer stacking structure again;
f. etching the bottom of the channel hole again to ensure that the multilayer film structure on the upper surface of the epitaxial silicon is broken down and the upper surface of the epitaxial silicon is exposed in the channel hole;
the monomer material of the high polymer protective film is CxFy and SiCl4One or more of; the number of layers of the multilayer stack structure is 64 or more.
2. The etching method according to claim 1, further comprising, after step f, step g:
and removing the residual high polymer protective film on the upper surface of the multilayer stacked structure.
3. The etching method according to claim 1,
the number of times of alternately repeating the steps b and c is 5 or more.
4. The etching method according to claim 1,
the uppermost hard mask of the multi-layer stack structure is a silicon oxide layer.
5. The etching method according to claim 1,
the method for etching the bottom of the channel hole is one of sputter etching, chemical etching and high-density plasma etching.
6. The etching method according to claim 1,
the multilayer film structure sequentially comprises a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, an amorphous silicon layer and a protective oxide film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711191821.8A CN107968050B (en) | 2017-11-24 | 2017-11-24 | Method for etching bottom of channel hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711191821.8A CN107968050B (en) | 2017-11-24 | 2017-11-24 | Method for etching bottom of channel hole |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107968050A CN107968050A (en) | 2018-04-27 |
| CN107968050B true CN107968050B (en) | 2020-03-13 |
Family
ID=62000566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711191821.8A Active CN107968050B (en) | 2017-11-24 | 2017-11-24 | Method for etching bottom of channel hole |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107968050B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110400749A (en) * | 2019-07-17 | 2019-11-01 | 上海华力微电子有限公司 | A kind of remaining method of improvement crystal column surface microparticle |
| CN113808929A (en) * | 2020-06-12 | 2021-12-17 | 中微半导体设备(上海)股份有限公司 | Method for forming semiconductor structure |
| CN113519055B (en) | 2021-06-07 | 2023-07-21 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of forming the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434447A (en) * | 1990-05-28 | 1995-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device having a trench for device isolation and method of fabricating the same |
| CN104658882A (en) * | 2013-11-25 | 2015-05-27 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method for controlling micro-loading effect of depth of shallow trench |
| CN106206507A (en) * | 2015-04-30 | 2016-12-07 | 旺宏电子股份有限公司 | Semiconductor structure and manufacture method thereof |
-
2017
- 2017-11-24 CN CN201711191821.8A patent/CN107968050B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434447A (en) * | 1990-05-28 | 1995-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device having a trench for device isolation and method of fabricating the same |
| CN104658882A (en) * | 2013-11-25 | 2015-05-27 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method for controlling micro-loading effect of depth of shallow trench |
| CN106206507A (en) * | 2015-04-30 | 2016-12-07 | 旺宏电子股份有限公司 | Semiconductor structure and manufacture method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107968050A (en) | 2018-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI700821B (en) | Substrate processing method and device manufactured by using the same | |
| US8815697B2 (en) | Method of fabricating semiconductor device | |
| CN107968050B (en) | Method for etching bottom of channel hole | |
| US8932935B2 (en) | Forming three dimensional isolation structures | |
| CN107994026B (en) | Process for protecting side wall in etching high depth-to-width ratio trench hole | |
| US20160233105A1 (en) | Method of forming a trench in a semiconductor device | |
| CN109256384B (en) | Through hole structure, preparation method thereof and three-dimensional memory | |
| EP3127156A1 (en) | Methods of tunnel oxide layer formation in 3d nand memory structures and associated devices | |
| CN108389831A (en) | The fill method of interlayer dielectric layer | |
| US20230093330A1 (en) | 3D NAND Structures with Decreased Pitch | |
| CN102610554A (en) | Method for improving isolation and filling characteristics of high aspect ratio shallow trench | |
| CN109712990A (en) | A kind of three-dimensional storage and preparation method thereof | |
| CN113496949B (en) | Method for improving electric leakage phenomenon after forming metal silicide layer on surface of gate structure | |
| CN107731750B (en) | Ultra-high aspect ratio SONO etching process | |
| US20140162453A1 (en) | Semiconductor device and method for fabricating the same | |
| CN101859725B (en) | Method for forming wafer by improving edge of shallow trench isolation structure | |
| JP2010147394A (en) | Method of manufacturing semiconductor device, and semiconductor device | |
| CN107994033B (en) | 3D NAND channel hole forming method based on oxide-polycrystalline silicon thin film stacking | |
| CN107507772B (en) | Method for etching bottom of channel hole | |
| US20200144111A1 (en) | Metal interconnection structure and method for fabricating same | |
| US20150243512A1 (en) | Method of manufacturing semiconductor device | |
| CN113035700B (en) | Preparation method of three-dimensional memory | |
| CN109817637B (en) | Semiconductor structure for three-dimensional memory element and manufacturing method thereof | |
| US11818875B2 (en) | Methods for forming memory and memory | |
| CN113471209B (en) | Method for preparing three-dimensional memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |