CN107968050A - The bottom lithographic method in raceway groove hole - Google Patents
The bottom lithographic method in raceway groove hole Download PDFInfo
- Publication number
- CN107968050A CN107968050A CN201711191821.8A CN201711191821A CN107968050A CN 107968050 A CN107968050 A CN 107968050A CN 201711191821 A CN201711191821 A CN 201711191821A CN 107968050 A CN107968050 A CN 107968050A
- Authority
- CN
- China
- Prior art keywords
- raceway groove
- groove hole
- multilayer lamination
- etching
- lithographic method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
The present invention relates to the bottom lithographic method in raceway groove hole, which specifically includes following steps：Crystal circle structure is provided, crystal circle structure includes substrate and the multilayer lamination structure on substrate, and raceway groove hole is equipped with multilayer lamination structure, and the bottom grown in raceway groove hole has epitaxial silicon, and the side wall in raceway groove hole and the upper surface deposition of epitaxial silicon have multi-layer film structure；Macromolecular protective film is deposited in the upper surface of multilayer lamination structure；Raceway groove bottom hole portion etching is carried out, until macromolecular protective film is exhausted；Repeat step b and step c at least once；Again macromolecular protective film is deposited in the upper surface of multilayer lamination structure；Raceway groove bottom hole portion etching is carried out again, until exposing the upper surface of epitaxial silicon.The present invention can effectively reduce the loss of hard mask at the top of raceway groove hole, bottom epitaxial silicon is fully opened, improve the process window of raceway groove hole etching and follow-up process by using the method for circulation etching.
Description
Technical field
The present invention relates to the manufacturing process area of semiconductor, more particularly to a kind of bottom lithographic method in raceway groove hole.
Background technology
With the continuous development of semiconductor technology, memory manufacturing technology is progressively from simple planar structure mistake at present
It is one of mainstream of international research and development to cross to complex three-dimensional structure, the technical research of three-dimensional storage.
, need to be in the bottom in raceway groove hole by outer after the etching technics of raceway groove hole in the preparation process of three-dimensional storage device
Epitaxial growth forms one layer of epitaxial silicon, and it is fixed to be then sequentially depositing silica, silicon nitride, silica, nothing in raceway groove hole side wall and bottom
Type silicon and protective oxide film, are then connected to outer by the above-described bottom multilayer film of raceway groove bottom hole portion lithographic method opening
Prolong silicon.
For stacking number in 64 layers and the three-dimensional storage of the above, for its etching depth-to-width ratio up to more than 90, this is together
The dry etch process of superelevation depth-to-width ratio, in order to which the extension silicon etching of bottom is opened, mainly by using high bias power
Etch formula.
Since the bottom in raceway groove hole is identical with the material of the hard mask at top, and the etch rate at top is much larger than bottom
Portion, therefore traditional lithographic method often causes the hard mask loss in top excessive, specifically as shown in Figure 1, the top of stacked structure
The silicon nitride in portion is depleted, the silicon nitride of secondary top layer be consumed it is more than half, and the epitaxial silicon of bottom only partially open even without
Open, specifically as shown in Fig. 2, the reduction of the process window which results in follow-up process.
The content of the invention
The purpose of the present invention is to solve at least one of problem above, the present invention provides a kind of raceway groove hole of high-aspect-ratio
Bottom lithographic method.
The bottom lithographic method in raceway groove hole, comprises the following steps：
A. crystal circle structure is provided, crystal circle structure includes substrate and the multilayer lamination structure positioned at substrate top surface, multilayer heap
Raceway groove hole is equipped with stack structure, raceway groove hole is extended to the upper surface of substrate, the bottom in raceway groove hole by the upper surface of multilayer lamination structure
Portion's growth has epitaxial silicon, and the upper surface of the side wall in raceway groove hole and epitaxial silicon deposition has multi-layer film structure；
B. macromolecular protective film is deposited in the upper surface of multilayer lamination structure；
C. bottom etching is carried out to raceway groove hole, until the macromolecular protective film consumption positioned at the upper surface of multilayer lamination structure
Finish；
D. it is alternately repeated and carries out step c and step d at least once.
E. macromolecular protective film is deposited in the upper surface of multilayer lamination structure again；
F. bottom etching is carried out to raceway groove hole again, until the multi-layer film structure positioned at epitaxial silicon upper surface is breakdown, outside
Prolong the upper surface of silicon in raceway groove hole.
Wherein, which further includes the step g after step e：The upper surface for removing multilayer lamination structure is remaining
Macromolecular protective film.
Wherein, the number of plies of multilayer lamination structure is more than or equal to 64 layers, step b and step c be alternately repeated number for 5 times with
On.
Wherein, the monomer material of macromolecular protective film is CxFy and SiCl4In one or more.
Wherein, the hard mask of the superiors of multilayer lamination structure is silicon oxide layer.
Wherein, the method for raceway groove bottom hole portion etching is in sputter etching, chemical etching or high density plasma etch
It is a kind of.
Wherein, multi-layer film structure includes silicon oxide layer, silicon nitride layer, silicon oxide layer, unformed silicon layer and oxide-film successively
Layer.
The invention has the advantages that：
The present invention can effectively reduce the loss of the hard mask at the top of raceway groove hole by using the method for circulation etching.Together
When, since the loss of the hard mask in top in etching technics is reduced, the thickness of the hard mask in top can be thinned, so as to reduce
The depth-to-width ratio of raceway groove bottom hole portion etching, can improve the process window of raceway groove hole etching and follow-up process.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Attached drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole attached drawing, identical component is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 shows the upper half of the crystal circle structure after being etched according to the bottom lithographic method in the raceway groove hole of traditional handicraft
The section TEM figures in portion；
Fig. 2 shows the lower half of the crystal circle structure after being etched according to the raceway groove bottom hole portion lithographic method of traditional handicraft
Section TEM figure；
Fig. 3 shows the flow chart of the bottom lithographic method in the raceway groove hole of embodiment according to the present invention；
Fig. 4 a~Fig. 4 e show the crystal circle structure of the bottom lithographic method in the raceway groove hole of embodiment according to the present invention
Cross section structure flow chart；
Fig. 5 shows the first half of the crystal circle structure of the bottom lithographic method in the raceway groove hole of embodiment according to the present invention
Section TEM schemes；
Fig. 6 shows the lower half of the crystal circle structure of the bottom lithographic method in the raceway groove hole of embodiment according to the present invention
Section TEM schemes；
Wherein, 1. substrate；2. multilayer lamination structure；3. macromolecular protective film；210. epitaxial silicon；220. multi-layer film structure.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
The basic thought of the present invention is to carry out deposition protection by cycle alternation on the surface of the multiple-level stack of crystal circle structure
Film and raceway groove bottom hole portion etch step, make the epitaxial silicon positioned at raceway groove bottom hole portion appropriate in the hard mask in the top of crystal circle structure
Progressively opened on the premise of protection.
As shown in figure 3, the bottom lithographic method in the raceway groove hole of the present invention comprises the following steps：
A. crystal circle structure is provided, crystal circle structure includes substrate and the multilayer lamination structure positioned at the upper surface of substrate, multilayer
Raceway groove hole is equipped with stacked structure, raceway groove hole is extended to the upper surface of substrate, the bottom in raceway groove hole by multilayer lamination structure upper surface
Portion's growth has epitaxial silicon, and the upper surface of the side wall in raceway groove hole and epitaxial silicon deposition has multi-layer film structure；B. in multiple-level stack
The upper surface deposition macromolecular protective film of structure；C. bottom etching is carried out to raceway groove hole, until the macromolecular protective film of upper surface
It is exhausted；D. it is alternately repeated and carries out step b and step c at least once；E. deposited again in the upper surface of multilayer lamination structure
Macromolecular protective film；F. bottom etching is carried out to raceway groove hole again, the multi-layer film structure positioned at epitaxial silicon upper surface is breakdown, outside
Prolong the upper surface of silicon in raceway groove hole.
Below in conjunction with attached drawing, by way of specific embodiment, to the manufacturer of three-dimensional storage provided by the invention
Method specifically explained, wherein attached drawing 4a~4e is the vertical section structure flow chart of the manufacture method of the application, attached drawing 4a~
Each attached drawing in 4e represents the structure change occurred in corresponding step.
Fig. 4 a correspond to the step a of the lithographic method of the present invention.As shown in fig. 4 a, there is provided a crystal circle structure, the crystal circle structure
Including substrate 1 and multilayer lamination structure 2, multilayer lamination structure 2 is located at the upper surface of substrate 1, and multilayer lamination structure is equipped with raceway groove
Multilayer lamination structure 2 is run through in hole, raceway groove hole, and the upper surface of substrate 1, raceway groove are extended to by the upper surface of multilayer lamination structure 2
The bottom in hole, which is also grown, epitaxial silicon 210, has multi-layer film structure 220 in the side wall in raceway groove hole and the upper surface deposition of epitaxial silicon.
Fig. 4 b correspond to the step b of the lithographic method of the present invention.As shown in Figure 4 b, sink in the upper surface of multilayer lamination structure 2
Product macromolecular protective film 3, in deposition process, high polymer can also be deposited on the table of the part multi-layer film structure positioned at extension silicon face
Face, forms high polymer thin layer.
Fig. 4 c correspond to the step c of the lithographic method of the present invention.As illustrated in fig. 4 c, raceway groove bottom hole portion etching is carried out, until high
Polymers protective film 3 is exhausted.Due at the top of crystal circle structure material composition (including high polymer protective layer, multilayer film thin layer and
Hard mask) it is essentially identical with the material composition (including high polymer thin layer, multi-layer film structure) of the extension silicon face in raceway groove bottom hole portion,
Therefore etching produces different degrees of loss to the material of the material at the top of crystal circle structure and extension silicon face.The degree of consumption
Mainly influenced by raceway groove hole depth, since raceway groove hole depth influences the decrease for etching energy so that the quarter in raceway groove bottom hole portion
Erosion intensity is weaker than the etching intensity of top material, therefore the loss of the material of extension silicon face is less than the top material of crystal circle structure
Loss.Therefore, finished when the macromolecular protective film 3 at the top of crystal circle structure is etched substantially, only positioned at epitaxial silicon table
Part film layer in the high polymer thin layer and multi-layer film structure in face is breakdown.
When raceway groove hole have compared with high-aspect-ratio, particularly stacked structure is more than 64 layers when, need circulating repetition to carry out multiple
The step of protective film deposits and raceway groove bottom hole portion etches, i.e. step d so that there is the premise of protective layer all the time in the hard mask of top layer
Under, multi-layer film structure reaches the state for being on the verge of breakdown by progressively etching.
Fig. 4 d correspond to the step e of the lithographic method of the present invention.As shown in figure 4d, after circulation is etched, for the last time more
The upper surface deposition high polymer of layer stacked structure 2, forms last macromolecular protective film.Similarly, in deposition process, high polymer
Also the surface for the multi-layer film structure for being on the verge of breakdown can be deposited on, forms last high polymer thin layer.
Fig. 4 e correspond to the step f of the lithographic method of the present invention.As shown in fig 4e, last time deposition macromolecular protective film it
Afterwards, the bottom etching in raceway groove hole is carried out again, and multi-layer film structure thoroughly punctures with the high polymer thin layer for being covered in its surface, makes outer
Prolong the upper surface of silicon 210 in raceway groove hole, the epitaxial silicon of bottom is opened.
When the upper surface of epitaxial silicon fully exposes, still there is part macromolecular protective film to remain in multilayer lamination structure
When, method of the invention further includes the step g for removing remaining macromolecular protective film.
Under normal conditions, the material of the hard mask of the superiors of multilayer lamination structure is silica, and multi-layer film structure wraps successively
Include silicon oxide layer, silicon nitride layer, silicon oxide layer, unformed silicon layer and protective oxide film layer, the method for raceway groove bottom hole portion etching
For dry etching (SONO ETCH), one be specifically as follows in sputter etching, chemical etching or high density plasma etch
Kind.
By taking 64 layers of stacked structure as an example, the bottom in raceway groove hole is performed etching using the bottom lithographic method of the present invention.Choosing
Take with CxOne or more in Fy or be CxOne or more and SiCl in Fy4Mixture, again either individually
SiCl4High polymer material as monomer is deposited, and is formed every time after certain thickness macromolecular protective film with progress phase
The etching answered, progressively etches raceway groove bottom hole portion using the cyclic deposition lithographic method that etches again is repeatedly first deposited, until
Etch successfully.The epitaxial silicon in the raceway groove bottom hole portion of crystal circle structure is fully opened after etching, specifically as shown in figure 5, stacking at the same time
The silica of the top layer of structure does not run out of, and the silicon nitride of secondary top layer is not consumed, and etching effect is good, and top influences micro-
It is small, it is specific as shown in Figure 6.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (7)
1. the bottom lithographic method in raceway groove hole, it is characterised in that comprise the following steps：
A. crystal circle structure is provided, crystal circle structure includes substrate and the multilayer lamination structure positioned at substrate top surface, multiple-level stack knot
Raceway groove hole is equipped with structure, raceway groove hole is extended to the upper surface of substrate, the bottom life in raceway groove hole by the upper surface of multilayer lamination structure
With epitaxial silicon, and the upper surface of the side wall in raceway groove hole and epitaxial silicon deposition has multi-layer film structure；
B. macromolecular protective film is deposited in the upper surface of multilayer lamination structure；
C. bottom etching is carried out to raceway groove hole, until the macromolecular protective film positioned at the upper surface of multilayer lamination structure runs out of
Finish；
D. it is alternately repeated and carries out step b and step c at least once；
E. macromolecular protective film is deposited in the upper surface of multilayer lamination structure again；
F. bottom etching is carried out to raceway groove hole again, until the multi-layer film structure positioned at epitaxial silicon upper surface is breakdown, epitaxial silicon
Upper surface in the raceway groove hole.
2. lithographic method as claimed in claim 1, it is characterised in that the lithographic method further includes the step after step e
Rapid g：
Remove the remaining macromolecular protective film in upper surface of multilayer lamination structure.
3. lithographic method as claimed in claim 1, it is characterised in that
For the number of plies of multilayer lamination structure more than or equal to 64 layers, the number that is alternately repeated of step b and step c are more than 5 times.
4. lithographic method as claimed in claim 1, it is characterised in that
The monomer material of macromolecular protective film is CxFy and SiCl4In one or more.
5. lithographic method as claimed in claim 1, it is characterised in that
The hard mask of the superiors of multilayer lamination structure is silicon oxide layer.
6. lithographic method as claimed in claim 1, it is characterised in that
The method of the raceway groove bottom hole portion etching is one kind in sputter etching, chemical etching and high density plasma etch.
7. lithographic method as claimed in claim 1, it is characterised in that
Multi-layer film structure includes silicon oxide layer, silicon nitride layer, silicon oxide layer, unformed silicon layer and oxidation film layer successively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711191821.8A CN107968050B (en) | 2017-11-24 | 2017-11-24 | Method for etching bottom of channel hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711191821.8A CN107968050B (en) | 2017-11-24 | 2017-11-24 | Method for etching bottom of channel hole |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107968050A true CN107968050A (en) | 2018-04-27 |
| CN107968050B CN107968050B (en) | 2020-03-13 |
Family
ID=62000566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711191821.8A Active CN107968050B (en) | 2017-11-24 | 2017-11-24 | Method for etching bottom of channel hole |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107968050B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110400749A (en) * | 2019-07-17 | 2019-11-01 | 上海华力微电子有限公司 | A kind of remaining method of improvement crystal column surface microparticle |
| CN113808929A (en) * | 2020-06-12 | 2021-12-17 | 中微半导体设备(上海)股份有限公司 | Method for forming semiconductor structure |
| US11935862B2 (en) | 2021-06-07 | 2024-03-19 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and methods for forming the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434447A (en) * | 1990-05-28 | 1995-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device having a trench for device isolation and method of fabricating the same |
| CN104658882A (en) * | 2013-11-25 | 2015-05-27 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method for controlling micro-loading effect of depth of shallow trench |
| CN106206507A (en) * | 2015-04-30 | 2016-12-07 | 旺宏电子股份有限公司 | Semiconductor structure and manufacture method thereof |
-
2017
- 2017-11-24 CN CN201711191821.8A patent/CN107968050B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434447A (en) * | 1990-05-28 | 1995-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device having a trench for device isolation and method of fabricating the same |
| CN104658882A (en) * | 2013-11-25 | 2015-05-27 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method for controlling micro-loading effect of depth of shallow trench |
| CN106206507A (en) * | 2015-04-30 | 2016-12-07 | 旺宏电子股份有限公司 | Semiconductor structure and manufacture method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110400749A (en) * | 2019-07-17 | 2019-11-01 | 上海华力微电子有限公司 | A kind of remaining method of improvement crystal column surface microparticle |
| CN113808929A (en) * | 2020-06-12 | 2021-12-17 | 中微半导体设备(上海)股份有限公司 | Method for forming semiconductor structure |
| US11935862B2 (en) | 2021-06-07 | 2024-03-19 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and methods for forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107968050B (en) | 2020-03-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107731846B (en) | Improve the three-dimensional storage forming method of channel through-hole homogeneity | |
| CN103594336B (en) | A kind of Double-patterning method | |
| CN107968050A (en) | The bottom lithographic method in raceway groove hole | |
| CN102629559B (en) | Manufacture method of stacked gate SiC-metal insulator semiconductor (MIS) capacitor | |
| CN102130045B (en) | Processing method of through holes | |
| JP2008205180A (en) | Semiconductor device and its manufacturing method | |
| US20220216134A1 (en) | Air bridge structure and manufacturing method thereof, and superconducting quantum chip and manufacturing method thereof | |
| CN108389831A (en) | The fill method of interlayer dielectric layer | |
| CN113496949B (en) | Method for improving electric leakage phenomenon after forming metal silicide layer on surface of gate structure | |
| CN101339902B (en) | high-voltage semiconductor device and method of fabricating semiconductor high-voltage device | |
| CN108461465A (en) | A kind of through-silicon via structure and preparation method thereof | |
| CN107731750A (en) | Superelevation depth-to-width ratio SONO etching technics | |
| CN105336593B (en) | The preparation method of grid and the preparation method of memory | |
| CN101859725B (en) | Method for forming wafer by improving edge of shallow trench isolation structure | |
| CN106952911B (en) | The forming method of fin semiconductor devices | |
| CN109411474B (en) | Method for forming three-dimensional memory step structure | |
| CN107742608A (en) | Double-pattern side wall mask etching technique | |
| CN209045527U (en) | Fleet plough groove isolation structure | |
| CN102779729B (en) | A kind of process route forming multilayer steps structure | |
| CN105244259A (en) | Structure and fabrication method of multiple patterning mask layer | |
| CN103972056B (en) | Method for forming self-aligned double-layer graph | |
| CN104779162B (en) | A kind of method for improving trench VDMOS device gate oxide breakdown voltage | |
| CN110085514B (en) | Double exposure method of NAND flash memory structure | |
| TW202017061A (en) | Semiconductor structure and method for preparing the same | |
| KR20130063089A (en) | Method for forming trench of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |