CN209045527U - Fleet plough groove isolation structure - Google Patents
Fleet plough groove isolation structure Download PDFInfo
- Publication number
- CN209045527U CN209045527U CN201821461597.XU CN201821461597U CN209045527U CN 209045527 U CN209045527 U CN 209045527U CN 201821461597 U CN201821461597 U CN 201821461597U CN 209045527 U CN209045527 U CN 209045527U
- Authority
- CN
- China
- Prior art keywords
- layer
- groove
- silicon dioxide
- isolation structure
- angstroms
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model provides a kind of fleet plough groove isolation structure, which includes: the fluted semiconductor substrate of tool, and groove is formed in semiconductor substrate；First silicon dioxide layer is formed in groove and forms cavity between channel bottom；Second silicon dioxide layer is formed in the surface of the first silicon dioxide layer, and the upper surface of the second silicon dioxide layer is flushed with groove upper surface.By the lower part of groove being set up separately and is set to cavity in fleet plough groove isolation structure, top filled media layer, size, shape and position of the cavity of formation etc. all can be by the preparation method stability contortings, to guarantee the raising of the stabilization and quality of device performance；In addition, can effectively improve the insulation effect of fleet plough groove isolation structure since the relative dielectric constant of air is close to 1 while reduce parasitic capacitance, to further increase the integrated level of device.
Description
Technical field
The utility model belongs to semiconductor integrated circuit field, more particularly to a kind of fleet plough groove isolation structure.
Background technique
Semiconductor integrated circuit generally comprises active area and the isolated area between active area, these isolated areas are manufacturing
It is formed before active device.With the development of semiconductor technology, the characteristic size of device is smaller and smaller in integrated circuit, device and
The speed of system increases accordingly, and after especially semiconductor technology enters the deep-submicron stage, isolation technology is become more and more important.
Currently, the method for forming active area of semiconductor device isolation structure mostly uses greatly shallow ditch groove separation process (Shallow Trench
Isolation, STI).
Fleet plough groove isolation structure in the prior art includes to be formed in the groove of isolated area or gap, ditch in semiconductor substrate
The electrical couplings to prevent from closing on device architecture are filled up by dielectric material in slot or gap.But as devices on integrated circuits is close
Degree lasting promotion, the size of device architecture between device at a distance from be gradually reduced, fleet plough groove isolation structure is also gradually reduced.So
And the reduction speed of fleet plough groove isolation structure vertical height is usually slow compared with its horizontal width, groove depth-to-width ratio with higher, leads
It causes to be difficult in the case where not generating the situation in random cavity or gap, completes the filling processing procedure of filling groove.
In addition, being led in the prior art using dielectric material filling groove since the relative dielectric constant of dielectric material is larger
Cause parasitic capacitance between adjacent devices larger, to restrict the raising of semiconductor integrated circuit speed.In addition, dielectric material and device
There is biggish thermal mismatch problem between part, influences the mechanical stability of entire integrated circuit device.
Therefore, it is necessary to propose that a kind of fleet plough groove isolation structure that can effectively reduce parasitic capacitance, improve insulation effect is real
Belong to necessary.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of shallow trench isolation mechanisms
And preparation method thereof, for solution, fleet plough groove isolation structure parasitic capacitance is larger in the prior art, and insulation effect is poor equal to ask
Topic.
In order to achieve the above objects and other related objects, the utility model provides a kind of fleet plough groove isolation structure, comprising:
Semiconductor substrate, has groove, and the groove is formed in the semiconductor substrate；
First silicon dioxide layer is formed in the groove and forms cavity between the channel bottom；
Second silicon dioxide layer, is formed in the surface of first silicon dioxide layer, and second silicon dioxide layer
Upper surface is flushed with the groove upper surface.
Preferably, first silicon dioxide layer has gap from bottom to top, and second silicon dioxide layer is filled
The gap.
Preferably, the isolation structure further include:
Thermal oxide layer is formed in side wall and the bottom of the groove；
For the protective layer of oxygen isolation, it is formed in the thermal oxide layer surface.
Preferably, the depth of the groove is between 2900 angstroms~3100 angstroms, and width is between 140 angstroms~160 angstroms.
Further, the thermal oxide layer includes linear thermal oxide layer, the thickness of the linear thermal oxide layer between 5 angstroms~
15 angstroms, the protective layer includes linear protection layer, and the thickness of the linear protection layer is between 10 angstroms~20 angstroms.
Further, the thickness of the carbon-coating is between 500 angstroms~2500 angstroms.
As described above, the fleet plough groove isolation structure of the utility model, has the advantages that by shallow trench isolation
In structure, the lower part of groove is set up separately and is set to cavity, top filled media layer, size, shape and position of the cavity of formation etc.
It all can be by the preparation method stability contorting of the utility model, to guarantee the raising of the stabilization and quality of device performance；In addition,
Since the relative dielectric constant of air is close to 1, the insulation effect of fleet plough groove isolation structure can be effectively improved while reducing shallow ridges
The parasitic capacitance of recess isolating structure, to can further improve the integrated level of device.
Detailed description of the invention
Fig. 1 is shown as the flow chart of the preparation method of the fleet plough groove isolation structure of the utility model.
Fig. 2 to Figure 15 is shown as the corresponding knot of corresponding steps in the preparation method of the fleet plough groove isolation structure of the utility model
Structure schematic diagram, wherein Figure 15 is also illustrated as the structural schematic diagram of the fleet plough groove isolation structure of the utility model.
Component label instructions
1 semiconductor substrate
10 grooves
11 buffer layers
12 first hard mask layers
13 second hard mask layers
131 hard mask polysilicon layers
132 anti-reflecting layers
14 photoresist layers
141 openings
15 windows
2 thermal oxide layers
3 protective layers
4 carbon-coatings
5 polysilicon layers
51 gaps
6 first silicon dioxide layers
7 cavitys
8 second silicon dioxide layers
S1~S6 step
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to 1~Figure 15.It should be noted that diagram provided in the present embodiment only illustrates this reality in a schematic way
With novel basic conception, only shown in diagram then with related component in the utility model rather than group when according to actual implementation
Number of packages mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind,
And its assembly layout kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present embodiment provides a kind of preparation method of fleet plough groove isolation structure, the fleet plough groove isolation structure
Preparation method include the following steps:
1) semiconductor substrate is provided, forms groove in Yu Suoshu semiconductor substrate；
2) carbon-coating is filled in Yu Suoshu groove, and the thickness of the carbon-coating is less than the depth of the groove；
3) side wall of the groove on Yu Suoshu carbon-coating top forms polysilicon layer；
4) thermal oxidation technology is used, so that the polysilicon layer is oxidized to the first silicon dioxide layer, while making the carbon-coating oxygen
Carbon dioxide gas is turned to be discharged to form cavity；
5) part first silicon dioxide layer is removed, and in forming the second dioxy in remaining first silicon dioxide layer
SiClx layer, and the upper surface of second silicon dioxide layer is flushed with the groove upper surface.
By the lower part of groove being set up separately and is set to cavity in fleet plough groove isolation structure, top filling is situated between the utility model
Matter layer, size, shape and position of the cavity of formation etc. all can be by the preparation method stability contortings of the utility model, to protect
Demonstrate,prove the raising of the stabilization and quality of device performance；In addition, can be effectively improved shallow since the relative dielectric constant of air is close to 1
The insulation effect of groove structure reduces the parasitic capacitance of fleet plough groove isolation structure simultaneously, to can further improve the integrated of device
Degree.
The preparation method of the fleet plough groove isolation structure of the utility model is described in detail below in conjunction with attached drawing.
Firstly, carrying out step S1 shown in S1 and Fig. 5 as shown in figure 1), semiconductor substrate 1, Yu Suoshu semiconductor lining are provided
Groove 10 is formed in bottom 1.
In the present embodiment, the semiconductor substrate 1 includes silicon substrate.
As preferable example, the step of step S1 forms groove 10, includes:
As shown in Fig. 2, step 1-1) semiconductor substrate 1 is provided, it is successively formed in the semiconductor substrate 1 from bottom to top
Buffer layer 11, the first hard mask layer 12, the second hard mask layer 13 and the photoresist layer 14 with opening 141.
The buffer layer 11 is preferably formed using thermal oxidation technology, and more preferably, the buffer layer 11 uses dry oxygen thermal oxide
Technique is formed.In the present embodiment, the semiconductor substrate 1 includes silicon substrate, is served as a contrast in the silicon by using thermal oxidation technology
The buffer layer 11 is formed on bottom.
In the step, it is preferred to use chemical vapor deposition process or spin coating process form first hard mask layer
12, the second hard mask layer 13 and photoresist layer 14.First hard mask layer 12 includes silicon oxynitride layer or silicon carbide layer, described
Second hard mask layer 13 includes hard mask polysilicon layer 131 and anti-reflecting layer 132 from bottom to top.
As shown in figure 3, step 1-2) dry etch process is used, it is hard to be sequentially etched described second based on the opening 141
Mask layer 13, the first hard mask layer 12 and buffer layer 11 form window 15.
As shown in figure 4, step 1-3) dry etch process is used, the semiconductor substrate 1 is etched based on the window 15.
As shown in figure 5, step 1-4) photoresist layer 14 and the second hard mask layer 13 are removed, form the groove 10.
What needs to be explained here is that the expression of groove 10 described in the utility model is formed at the semiconductor substrate 1
In part, and in this preferable example, the depth of the groove 10 includes the thickness and described first of the buffer layer 11
The thickness of hard mask layer 12, during general technology, the buffer layer 11 and first hard mask layer 12 are relative to described
Very little for the depth of groove 10, so will not be had an impact to the depth of the groove 10.
In the present embodiment, the depth of the groove 10 is between 2900 angstroms~3100 angstroms, width between 140 angstroms~
Between 160 angstroms.Preferably, the depth of the groove 10 is 3000 angstroms, and width is 150 angstroms.
In addition, step 1-4) in, the buffer layer 11 and first hard mask layer 12 are not removed, it is intended that
The semiconductor substrate 1 and the groove will not be etched into when finally etching the buffer layer 11 and first hard mask layer 12
Second silicon dioxide layer 8 of 10 connected corners, " beak " effect of isolation structure is effectively reduced, this also will later
It elaborates.
Then, shown in S2 and Fig. 8 as shown in figure 1, step S2 is carried out) the interior filling carbon-coating 4 of Yu Suoshu groove 10, and the carbon
The thickness of layer 4 is less than the depth of the groove 10.
As a preferable examples, in step 2), the filling carbon-coating 4 further includes before in described in Yu Suoshu groove 10
The side wall of groove 10 and bottom form thermal oxide layer 2 and form the protection for oxygen isolation in the surface of the thermal oxide layer 2
The step of layer 3.Based on the preferable examples, step 2) preferably includes following steps:
As shown in fig. 6, step 2-1) use thermal oxidation technology to form the hot oxygen in the side wall of the groove 10 and bottom
Change layer 2.Preferably, the thermal oxide layer 2 includes linear thermal oxide layer, the thickness of the linear thermal oxide layer is between 5 angstroms~15
Between angstrom, it is therefore preferable to 10 angstroms.
As shown in fig. 7, step 2-2) use chemical vapor deposition process in the surface of the thermal oxide layer 2 and described first
The surface of hard mask layer 12 deposits the protective layer 3.
The protective layer 3 that 12 surface of the first hard mask layer is formed in this step can be in this step 3-1) after immediately
Removal, can also be placed on and finally remove together with extra second silicon dioxide layer 8 being subsequently formed, select in the present embodiment
It is removed together finally with extra second silicon dioxide layer 8 being subsequently formed, process can be saved, reduce cost.
In the present embodiment, the preferably described protective layer 3 includes silicon nitride layer.The protective layer 3 includes linear protection layer, described
The thickness of linear protection layer is between 10 angstroms~20 angstroms, it is therefore preferable to 15 angstroms.
As shown in figure 8, step 2-3) use chemical vapor deposition process to deposit the carbon-coating in the surface of the protective layer 3
4, and be etched back, only retain the carbon-coating 4 of 10 lower part of groove, and the thickness of the carbon-coating 4 is less than the groove
10 depth.
In the present embodiment, the thickness of the carbon-coating 4 is between 500 angstroms~2500 angstroms, and preferably 2000 angstroms.
Continue, shown in S3 and Figure 10 as shown in figure 1, carry out step S3) Yu Suoshu carbon-coating 4 top the groove 10 side
Wall forms polysilicon layer 5.
As preferable example, step S3 the following steps are included:
As shown in figure 9, step 3-1) use chemical vapor deposition process in 3 table of 4 surface of carbon-coating and the protective layer
Face deposits the polysilicon layer 5.
As shown in Figure 10, step 3-2) it is etched back to the polysilicon layer 5, only retain the groove on 4 top of carbon-coating
The polysilicon layer 5 of 10 side walls.
In the present embodiment, be formed in the thickness of the polysilicon layer 5 of 10 side wall of groove between 15 angstroms~23 angstroms it
Between, preferably 18 angstroms.
Then, shown in S4 and Figure 11 as shown in figure 1, step S4 is carried out) thermal oxidation technology is used, make the polysilicon layer 5
It is oxidized to the first silicon dioxide layer 6, while so that the carbon-coating 4 is oxidized to carbon dioxide gas and being discharged to form cavity 7.
In the present embodiment, the oxidizing temperature of the thermal oxidation technology is between 700 DEG C~1000 DEG C.Preferably, it uses
First silicon dioxide layer 6 that thermal oxidation technology is formed has gap 51 from bottom to top, and the carbon dioxide gas is through institute
State the discharge of gap 51, it is ensured that the carbon dioxide gas of generation is discharged from the cavity 7 completely, improves the purity of cavity, with
Reduce the whole relative dielectric constant of fleet plough groove isolation structure.
Shown in S5 and Figure 12~Figure 15 as shown in figure 1, step S5 is carried out) removal part first silicon dioxide layer 6, and
In forming the second silicon dioxide layer 8, and the upper surface of second silicon dioxide layer 8 in remaining first silicon dioxide layer 6
It is flushed with 10 upper surface of groove.
As preferable example, step S5 the following steps are included:
As shown in figure 12, step 5-1) using dry etch process removal part first silicon dioxide layer 6.It is etched back to
The principle of first silicon dioxide layer 6 is to guarantee that first silicon dioxide layer 6 is not cut through.In the present embodiment, preferred institute
The removal thickness of the first silicon dioxide layer 6 is stated between 100 angstroms~450 angstroms, preferably 400 angstroms.
As shown in figure 13, step 5-2) use chemical vapor deposition process in remaining first silicon dioxide layer, 6 surface
And 3 surface of protective layer deposits second silicon dioxide layer 8, and the upper surface of second silicon dioxide layer 8 with it is described
10 upper surface of groove flushes.
What needs to be explained here is that when first silicon dioxide layer 6 has gap 51 from bottom to top, using chemistry
Gas-phase deposition forms second silicon dioxide layer 8, then one layer very thin second can be formed on the inner wall of the cavity 7
Silicon dioxide layer 8, in order to minimize second silicon dioxide layer of thin layer 8, it is preferred to use plasma enhanced chemical vapor is heavy
Product technique forms second silicon dioxide layer 8, can fill the gap 51 as early as possible, reduce by second dioxy in the cavity
SiClx layer 8.
As shown in figure 14, step 5-3) chemical mechanical milling tech is used, remove described second except the groove 10
Silicon dioxide layer 8 and protective layer 3.
As described above, selection removes the protective layer 3 in this step, materials at two layers can be removed with a procedure, i.e., it is described
Second silicon dioxide layer 8 and protective layer 3 save process, reduce cost.
As shown in figure 15, step 5-4) using dry etch process or the wet corrosion technique removal semiconductor substrate 1
First hard mask layer 12 and buffer layer 11 of upper surface.
As noted previously, as second silicon dioxide layer 8 is protected by the external protective layer 3, so described in the removal
It is not in " gutter " phenomenon when the first hard mask layer 12 and buffer layer 11.
Embodiment two
Incorporated by reference to embodiment one with continued reference to Figure 15 and Fig. 5, the utility model also provides a kind of fleet plough groove isolation structure,
In, the fleet plough groove isolation structure preferably uses the preparation method of the utility model to prepare, and the fleet plough groove isolation structure includes:
Semiconductor substrate 1, has groove 10, and the groove 10 is formed in the semiconductor substrate 1；
First silicon dioxide layer 6 is formed in the groove 10 and forms cavity 7 between the channel bottom；
Second silicon dioxide layer 8 is formed in the surface of first silicon dioxide layer 6, and second silicon dioxide layer 8
Upper surface flushed with 10 upper surface of groove.
As an example, the semiconductor substrate 1 includes silicon substrate.
Preferably, the fleet plough groove isolation structure further include:
Thermal oxide layer 2 is formed in side wall and the bottom of the groove 10；
For the protective layer 3 of oxygen isolation, it is formed in 2 surface of thermal oxide layer.
Preferably, the depth of the groove 10 is between 2900 angstroms~3100 angstroms, and width is between 140 angstroms~160 angstroms.
Preferably, the thermal oxide layer 2 includes linear thermal oxide layer, the thickness of the linear thermal oxide layer between 5 angstroms~
15 angstroms, the protective layer 3 includes linear protection layer, and the thickness of the linear protection layer is between 10 angstroms~20 angstroms.
Preferably, the thickness of the carbon-coating 4 is between 500 angstroms~2500 angstroms.
Preferably, as shown in figure 11, first silicon dioxide layer 6 has gap 51 from bottom to top, and described second
Silicon dioxide layer 8 fills the gap 51.
The utility model proposes fleet plough groove isolation structure, the lower part of groove 10 is set up separately and is set to cavity 7, top filling be situated between
Matter layer 6 and 7 can effectively improve the insulation effect of fleet plough groove isolation structure simultaneously since the relative dielectric constant of air is close to 1
The parasitic capacitance for reducing fleet plough groove isolation structure, to can further improve the integrated level of device.
In conclusion the fleet plough groove isolation structure of the utility model includes: the fluted semiconductor substrate of tool, groove is formed
In semiconductor substrate；First silicon dioxide layer is formed in groove and forms cavity between channel bottom；Second titanium dioxide
Silicon layer is formed in the surface of the first silicon dioxide layer, and the upper surface of the second silicon dioxide layer is flushed with groove upper surface.Pass through
In fleet plough groove isolation structure, the lower part of groove is set up separately and is set to cavity, top filled media layer, the size of the cavity of formation,
Shape and position etc. all can be by the preparation method stability contortings of the utility model, to guarantee the stabilization and quality of device performance
Raising；In addition, the insulation effect of fleet plough groove isolation structure can be effectively improved since the relative dielectric constant of air is close to 1
The parasitic capacitance of fleet plough groove isolation structure is reduced simultaneously, to can further improve the integrated level of device.So the utility model
It effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (5)
1. a kind of fleet plough groove isolation structure characterized by comprising
Semiconductor substrate, has groove, and the groove is formed in the semiconductor substrate；
First silicon dioxide layer is formed in the groove and forms cavity between the channel bottom；
Second silicon dioxide layer is formed in the surface of first silicon dioxide layer, and the upper table of second silicon dioxide layer
Face is flushed with the groove upper surface.
2. fleet plough groove isolation structure according to claim 1, it is characterised in that: first silicon dioxide layer has under
Gap on and, and second silicon dioxide layer fills the gap.
3. fleet plough groove isolation structure according to claim 1, which is characterized in that the isolation structure further include:
Thermal oxide layer is formed in side wall and the bottom of the groove；
For the protective layer of oxygen isolation, it is formed in the thermal oxide layer surface.
4. fleet plough groove isolation structure according to claim 1, it is characterised in that: the depth of the groove between 2900 angstroms~
Between 3100 angstroms, width is between 140 angstroms~160 angstroms.
5. fleet plough groove isolation structure according to claim 3, it is characterised in that: the thermal oxide layer includes linear thermal oxide
Layer, for the thickness of the linear thermal oxide layer between 5 angstroms~15 angstroms, the protective layer includes linear protection layer, described linear
The thickness of protective layer is between 10 angstroms~20 angstroms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821461597.XU CN209045527U (en) | 2018-09-07 | 2018-09-07 | Fleet plough groove isolation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821461597.XU CN209045527U (en) | 2018-09-07 | 2018-09-07 | Fleet plough groove isolation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209045527U true CN209045527U (en) | 2019-06-28 |
Family
ID=67032578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821461597.XU Active CN209045527U (en) | 2018-09-07 | 2018-09-07 | Fleet plough groove isolation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209045527U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111146140A (en) * | 2019-11-27 | 2020-05-12 | 上海集成电路研发中心有限公司 | Semiconductor structure and forming method |
-
2018
- 2018-09-07 CN CN201821461597.XU patent/CN209045527U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111146140A (en) * | 2019-11-27 | 2020-05-12 | 上海集成电路研发中心有限公司 | Semiconductor structure and forming method |
| CN111146140B (en) * | 2019-11-27 | 2023-09-05 | 上海集成电路研发中心有限公司 | Semiconductor structure and forming method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20030057184A1 (en) | Method for pull back SiN to increase rounding effect in a shallow trench isolation process | |
| CN105047660B (en) | Fleet plough groove isolation structure | |
| CN103871856B (en) | The forming method of metal gates | |
| CN112420716B (en) | Semiconductor device and preparation method thereof | |
| CN108389831A (en) | The fill method of interlayer dielectric layer | |
| CN209029354U (en) | Fleet plough groove isolation structure | |
| CN209045527U (en) | Fleet plough groove isolation structure | |
| CN105118775A (en) | A shield grid transistor formation method | |
| CN104465728B (en) | The grid structure and process of separate gate power device | |
| CN108735750A (en) | Memory construction and its manufacturing method | |
| CN106098544A (en) | The method improving groove type double-layer grid MOS dielectric layer pattern | |
| CN103632943A (en) | Manufacturing method of semiconductor device | |
| CN104134628A (en) | Manufacturing method of shallow trench isolation structure | |
| US5923991A (en) | Methods to prevent divot formation in shallow trench isolation areas | |
| CN102054672B (en) | Process method for forming minisize pattern on substrate with waved surface | |
| CN107799531B (en) | A kind of 3D nand memory grade layer stack manufacturing method | |
| CN103531476B (en) | Method, semi-conductor device manufacturing method | |
| CN107706145B (en) | Isolation trench film filling structure, semiconductor memory device and preparation method | |
| CN112951840B (en) | Three-dimensional memory and preparation method thereof | |
| WO2021213130A1 (en) | Forming method for memory and memory | |
| CN104851834A (en) | Semiconductor device preparation method | |
| US8524093B2 (en) | Method for forming a deep trench | |
| CN110890313A (en) | Shallow trench isolation structure and preparation method thereof | |
| CN208706616U (en) | Fleet plough groove isolation structure | |
| CN106952911A (en) | The forming method of fin semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |