CN107706145B - Isolation trench film filling structure, semiconductor memory device and preparation method - Google Patents

Isolation trench film filling structure, semiconductor memory device and preparation method Download PDF

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CN107706145B
CN107706145B CN201710980265.6A CN201710980265A CN107706145B CN 107706145 B CN107706145 B CN 107706145B CN 201710980265 A CN201710980265 A CN 201710980265A CN 107706145 B CN107706145 B CN 107706145B
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peripheral
trench
density plasma
semiconductor substrate
layer
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CN107706145A (en
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides an isolation groove film filling structure, a semiconductor memory device and a preparation method, wherein the preparation method of the isolation groove film filling structure at least comprises the following steps: providing a semiconductor substrate provided with a peripheral groove; forming a prefabricated filling material on the semiconductor substrate, covering the upper surface of the semiconductor substrate and the side wall and the bottom of the peripheral groove, and forming a necking neck; pre-etching the prefabricated filling material to remove the necking neck; forming a high-density plasma oxide material on the semiconductor substrate, covering the prefabricated filling material and filling the peripheral groove; and removing the redundant high-density plasma oxide material and the prefabricated filling material to obtain a high-density plasma oxide layer and a prefabricated filling layer which are positioned in the peripheral groove. The invention improves the appearance of the prefabricated filling material by pre-etching, so that a cavity is not easy to form between the high-density plasma oxide material and the prefabricated filling material, and further, the device failure caused by short circuit of a metal bit line formed later is avoided.

Description

Isolation trench film filling structure, semiconductor memory device and preparation method
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to an isolation trench thin film filling structure, a semiconductor memory device and a method for manufacturing the same.
Background
The patterning can create a topology with three spatial dimensions on the wafer surface, which creates gaps and steps on the wafer surface. A small gap (e.g., an isolation trench or via) may be described by an aspect ratio, which is defined as the ratio of the depth to the width of the gap. The ability to fill very small gaps on the surface of a silicon wafer is the most important thin film property in the fabrication of devices. For small gaps, the aspect ratio, whether high/low, makes it difficult to deposit films of uniform thickness and creates pinch-offs and voids. With the continued decrease in feature sizes of high density integrated circuits, it is important that a uniform, void-free fill deposition process be performed for high/low aspect ratio gaps.
Chemical vapor deposition (Chemical Vapor Deposition, CVD) is a process of depositing a solid film on the surface of a silicon wafer by chemical reaction of gas mixture. Common chemical vapor deposition includes atmospheric Pressure chemical vapor deposition (Atmospheric Pressure CVD, APCVD), low Pressure Chemical Vapor Deposition (LPCVD), and plasma-assisted chemical vapor deposition. A recent development in plasma-assisted chemical vapor deposition is high density plasma chemical vapor deposition (High Density Plasma CVD, HDPCVD) which uses a plasma at low pressure in the form of a high density gas mixture that directly contacts the surface of the silicon wafer in the reaction chamber. Its main advantage is that it can prepare the film capable of filling the gap with high depth-to-width ratio at the deposition temperature of 300-400 deg.C.
The high density plasma chemical vapor deposition process has simultaneous deposition and etching, which is the basis for filling high aspect ratio gaps with dielectric materials and without void formation. The synchronous deposition and etching mainly comprises the following three mechanisms: 1. ion-induced deposition: ion-induced film initial product deposition to form gap filling; 2. sputtering and etching: etching redundant films at the gap inlet by argon ion sputtering, and forming an inclined plane shape on the films; 3. and (3) redeposition: and depositing the etched material. The process is repeated until the upper and lower topography is consistent. The method is used for depositing the film in the U.S. patent 6908862B 2. Specifically, this patent discloses a method of depositing a film on a substrate disposed in a substrate reaction chamber, the method comprising depositing a first portion of a thin film by forming a high density plasma from a first gaseous mixture flowing into the reaction chamber; then stopping the deposition process and etching the first portion of the deposited film by flowing a halogen etchant into the reaction chamber; next, passivating the surface of the etched film by flowing a passivating gas into the reaction chamber, and then depositing a second portion of the thin film on the first portion by forming a high-density plasma from a second gaseous mixture flowing into the reaction chamber; in one embodiment, the passivation gas consists of an oxygen source that is free of inert gas.
However, the above patent is mainly directed to the problem of void generation in the center of the gap due to the difficulty in film deposition caused by too high aspect ratio when the high aspect ratio gap-filling film is used. The redundant film at the gap entrance is etched into an inclined surface shape (or called a funnel shape), so that the material deposited again later can be filled into the gap, and the hollow at the center of the gap is avoided. Although this patent is effective in solving the void filling problem of high aspect ratio gaps, it does not solve well the void problem that occurs during film filling for low (or medium) aspect ratio gaps.
In the prior art, the isolation trench thin film filling structure includes a pre-filled layer 301 covering the sidewall and bottom of the isolation trench, and a high density plasma oxide layer 402 covering the pre-filled layer 301 and filling the isolation trench. As shown in fig. 1, during normal filling, a void 401 should not occur between the pre-filling layer 301 and the high-density plasma oxide layer 402, so that the metal bit line 501 formed later should work normally, and a phenomenon such as a short circuit is not easy to occur, so that a Device (Device) fails. However, with continued reference to fig. 1, due to the limitations of the prior art, voids 401 often occur between the pre-filled layer 301 and the high-density plasma oxide layer 402, so that the metal bit line 501 is easily shorted during the subsequent formation of the metal bit line 501, resulting in device failure.
Therefore, how to avoid the void generated in the high/low aspect ratio isolation trench during the film filling process, so that the metal bit line formed later is easy to generate short circuit to cause device failure is a problem to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an isolation trench thin film filling structure, a semiconductor memory device and a method for manufacturing the same, which are used for solving the problem that in the prior art, a high/low aspect ratio isolation trench is prone to void during the thin film filling process, so that a short circuit is prone to occur in a subsequently formed metal bit line, thereby causing device failure.
To achieve the above and other related objects, the present invention provides a method for preparing an isolation trench thin film filling structure, wherein the method for preparing the isolation trench thin film filling structure at least comprises the following steps:
providing a semiconductor substrate, wherein an upper surface of the semiconductor substrate comprises a device region and a peripheral region surrounding the device region, a plurality of array grooves in the device region and a peripheral groove in the peripheral region are prepared on the semiconductor substrate, and the width of the peripheral groove is more than twice the cell width of the array groove;
Forming a prefabricated filling material on the upper surface of the semiconductor substrate, wherein the prefabricated filling material further covers the upper surface of the semiconductor substrate and the side walls and the bottom of the peripheral groove, the prefabricated filling material further fills the array groove and is used for defining a plurality of active areas, a necking neck is formed at the opening end of the peripheral groove by the prefabricated filling material, and the opening aperture of the necking neck is smaller than the middle aperture of the prefabricated filling material at the middle position of the peripheral groove;
pre-etching the prefabricated filling material to remove the necking neck of the prefabricated filling material;
forming a high-density plasma oxide material on the upper surface of the semiconductor substrate, wherein the high-density plasma oxide material further covers the prefabricated filling material and fills the peripheral groove in a void-free manner; the method comprises the steps of,
and removing the high-density plasma oxide material and the prefabricated filling material on the semiconductor substrate to obtain a high-density plasma oxide layer and a prefabricated filling layer which are positioned in the peripheral groove.
Preferably, in the step of pre-etching the pre-filling material, it includes: and etching the prefabricated filling material by adopting a high-density plasma etching process, and simultaneously keeping the etching pressure at 10-40 mtorr.
Preferably, when etching the prefabricated filling material, the etching depth of the high-density plasma etching process is controlled not to expose the step corners of the peripheral grooves.
Preferably, in the step of removing the high-density plasma oxide layer and the pre-filled layer, it includes:
and sequentially etching the high-density plasma oxide material and the prefabricated filling material until the upper surface of the semiconductor substrate is exposed, so that the high-density plasma oxide material and the prefabricated filling material outside the peripheral groove are removed, and the peripheral groove is filled with the high-density plasma oxide material and the residual part of the prefabricated filling material to obtain the high-density plasma oxide layer and the prefabricated filling layer, so that a void-free isolation groove film filling structure is formed.
Preferably, before forming the prefabricated filling material, the preparation method of the isolation trench film filling structure further comprises the following steps:
and forming a passivation layer on the semiconductor substrate, wherein the passivation layer covers the upper surface of the semiconductor substrate.
Preferably, the depth-to-width ratio of the peripheral grooves is 0.5:1-21:20, and the depth-to-width ratio of the array grooves is 10:1-20:1.
Preferably, the preformed filling material is formed using a high density plasma deposition process, a plasma enhanced deposition process, an atmospheric/low pressure chemical vapor deposition process, a spin-on deposition process, or a surface oxidation process.
Preferably, in the step of pre-etching the pre-filling material, the pre-filling layer at the step corners of the peripheral trench is also cut off.
To achieve the above and other related objects, the present invention provides an isolation trench thin film filling structure, wherein the isolation trench thin film filling structure at least comprises:
a semiconductor substrate, wherein an upper surface of the semiconductor substrate comprises a device region and a peripheral region surrounding the device region, a plurality of array grooves in the device region and a peripheral groove in the peripheral region are prepared on the semiconductor substrate, and the width of the peripheral groove is more than twice the cell width of the array groove;
a pre-filled layer covering the sidewalls and bottom of the peripheral trench, the pre-filled material further filling the array trench to define a plurality of active regions; the method comprises the steps of,
a high-density plasma oxide layer covering the pre-fabricated filling layer within the peripheral trench and filling the peripheral trench;
The thickness of the prefabricated filling layer at the corner of the peripheral groove step is smaller than or equal to that of the prefabricated filling layer at the side wall of the peripheral groove, so that the problem that a metal bit line formed later is short-circuited due to the fact that a cavity exists between the high-density plasma oxide layer and the prefabricated filling layer is avoided.
Preferably, the peripheral trench thin film fill structure further comprises a passivation layer formed overlying the upper surface of the semiconductor substrate, and the pre-filled layer thickness at the peripheral trench step corners overlies the peripheral trench step corners.
Preferably, a pre-filled layer located at the peripheral trench step corner is connected to the side edges of the passivation layer.
Preferably, the depth-to-width ratio of the peripheral grooves is 0.5:1-21:20, and the depth-to-width ratio of the array grooves is 10:1-20:1.
Preferably, the step corner of the peripheral groove is formed with a chamfer.
To achieve the above and other related objects, the present invention provides a semiconductor memory device, wherein the semiconductor memory device includes at least:
a substrate;
a plurality of peripheral trenches formed on the semiconductor substrate and surrounding a plurality of active regions located on the semiconductor substrate;
A prefabricated filling layer covering the side wall and the bottom of the peripheral groove; the method comprises the steps of,
a high-density plasma oxide layer covering the pre-filled layer and filling the peripheral trench;
wherein the high density plasma oxide layer and the pre-filled layer together fill the peripheral trench and together provide a void-free film fill depth equal to the peripheral trench depth.
Preferably, the thickness of the prefabricated filling layer at the corner of the peripheral groove step is smaller than or equal to the thickness of the peripheral groove side wall near the bottom, so that the void-free film filling depth can be directly formed.
Preferably, the depth-to-width ratio of the peripheral groove is 0.5:1-21:20.
Preferably, the semiconductor memory device further includes a plurality of metal bit lines disposed on the semiconductor substrate, ends of the metal bit lines extending onto the high-density plasma oxide layer within the peripheral trench.
As described above, the isolation trench film filling structure, the semiconductor memory device and the manufacturing method of the present invention have the following beneficial effects:
according to the isolation groove film filling structure and the preparation method thereof, before the high-density plasma oxide material is formed, the appearance of the prefabricated filling material is improved through pre-etching, so that the thickness of the prefabricated filling material at the corner of the isolation groove step is smaller than or equal to that of the prefabricated filling material at the side wall of the isolation groove, the bond between the high-density plasma oxide material and the prefabricated filling material is good, a cavity is not easy to form, and further the device failure caused by short circuit of a metal bit line formed later is avoided. In addition, the present invention is applicable to high/low aspect ratio isolation trenches, particularly low or medium aspect ratio isolation trenches. In addition, the invention adopts a high-density plasma etching process to etch the prefabricated filling material, and simultaneously ensures the integrity of the step corners of the isolation groove by controlling the etching pressure and the etching depth, thereby avoiding the circuit breaking caused by the cutting of the step corners of the isolation groove and finally causing the failure of the device. In addition, the invention can form a chamfer on the prefabricated filling layer at the corner of the step of the peripheral groove, further enlarge the aperture of the prefabricated filling layer at the opening end of the peripheral groove, facilitate the subsequent high-density plasma oxide layer filling formation, further reduce the generation of voids and improve the yield of devices.
The semiconductor memory device and the preparation method thereof adopt the isolation groove film filling structure and the preparation method thereof to prepare the isolation groove film filling structure, the high-density plasma oxide material in the isolation groove film filling structure and the prefabricated filling material have good bonding effect, and the void-free film filling depth which is equal to the isolation groove depth can be provided together, so that the problem of short circuit of a metal bit line formed later is not easy to occur, the possibility of device failure is greatly reduced, and the device yield is improved; meanwhile, the prefabricated filling material at the corner of the step of the isolation groove is good, so that the circuit is not easy to break, and the yield of the device is further improved.
Drawings
Fig. 1 is a schematic diagram showing the comparison of the prior art isolation trench film filling structure when voids and normal filling occur.
Fig. 2 to 5 are schematic structural views showing specific steps in a method for manufacturing an isolation trench thin film filling structure in the prior art.
Fig. 6 is a schematic flow chart of a method for preparing an isolation trench film filling structure according to a first embodiment of the present invention.
Fig. 7 to 11 are schematic structural views showing specific steps in the method for manufacturing an isolation trench thin film filling structure according to the first embodiment of the present invention, wherein fig. 11 is a schematic structural view showing the isolation trench thin film filling structure according to the first embodiment of the present invention.
Fig. 12 is a schematic view showing an isolation trench thin film filling structure obtained by cutting off a pre-filling material at a corner of an isolation trench step in a method for manufacturing the isolation trench thin film filling structure according to the first embodiment of the present invention.
Fig. 13 to 17 are schematic structural views showing specific steps of forming the isolation trench thin film filling structure in the peripheral trench and the array trench simultaneously in the method for manufacturing the isolation trench thin film filling structure according to the first embodiment of the present invention, wherein fig. 17 is a schematic structural view showing the isolation trench thin film filling structure according to the first embodiment of the present invention.
Description of element reference numerals
100. Semiconductor substrate
101. Peripheral groove
102. Array trench
201. Passivation layer
300. Prefabricated filling material
301. Prefabricated filling layer
302. Necking neck
400. High density plasma oxide material
401. Hollow cavity
402. High density plasma oxide layer
501. Metal bit line
S1 to S5 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
In the background art, as for the problem of the void 401 shown in fig. 1, the inventors have found through intensive studies that the void 401 is often generated between the pre-filled layer 301 and the high density plasma oxide layer 402 because, after the pre-filled material is formed on the semiconductor substrate 100, as shown in fig. 2 and 3, the pre-filled material at the corner a of the isolation trench step protrudes, i.e., the thickness of the pre-filled material at the corner a of the isolation trench step is greater than that at the side wall of the isolation trench, thereby causing that when the high density plasma oxide material is formed, as shown in fig. 4, the bond between the high density plasma oxide material 400 and the pre-filled material 300 is poor, so that the void 401 is easily generated at the contact position between the high density plasma oxide material 400 and the pre-filled material 300, thereby obtaining the isolation trench thin film filling structure as shown in fig. 5, and it is not difficult to find that the position between the side wall of the high density plasma oxide layer 402 and the pre-filled layer 301 at the corner of the isolation trench step in fig. 5 has the void 401, so that in the subsequent process of forming the metal bit line will be filled with metal, so that the metal bit line will easily cause the failure of the device.
Referring to fig. 6 to 17, a first embodiment of the present invention relates to a method for preparing an isolation trench film filling structure. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 6 to 17, the method for manufacturing the isolation trench thin film filling structure of the present embodiment at least includes the steps of:
in step S1, a semiconductor substrate 100 is provided, wherein an upper surface of the semiconductor substrate 100 includes a device region and a peripheral region surrounding the device region, a plurality of array trenches 102 in the device region and a peripheral trench 101 in the peripheral region are formed on the semiconductor substrate 100, and a width of the peripheral trench 101 is more than twice a cell width of the array trenches 102.
In step S2, a pre-filling material 300 is formed on the upper surface of the semiconductor substrate 100, the pre-filling material 300 further covers the upper surface of the semiconductor substrate 100 and the sidewalls and bottom of the peripheral trench 101, the pre-filling material 300 further fills the array trench 102 to define a plurality of active regions, the pre-filling material 300 is formed with a necking neck 302 at the opening end of the peripheral trench 101, and the opening aperture of the necking neck 302 is smaller than the middle aperture of the pre-filling material 300 at the middle position of the peripheral trench 101.
Step S3, pre-etching the pre-filling material 300 to remove the necking neck 302 of the pre-filling material 300.
In step S4, a high-density plasma oxide material 400 is formed on the upper surface of the semiconductor substrate 100, the high-density plasma oxide material 400 further covers the pre-formed filling material 300, and the peripheral trench 101 is filled in a void-free manner.
In step S5, the high-density plasma oxide material 400 and the pre-fill material 300 of the peripheral trench 101 on the semiconductor substrate 100 are removed to obtain a high-density plasma oxide layer 402 and a pre-fill layer 301 within the peripheral trench 101.
It should be noted that, the pre-filling material 300 can improve its own morphology by pre-etching, so that the thickness of the pre-filling material at the step corner a of the peripheral trench 101 is less than or equal to the thickness of the pre-filling material at the sidewall of the peripheral trench 101, thereby avoiding the formation of voids between the high-density plasma oxide material 400 and the pre-filling material 300 during the formation of the high-density plasma oxide material 400, which may cause a short circuit of the metal bit lines formed later.
In addition, before forming the pre-filling material 300, the method for manufacturing the isolation trench thin film filling structure of the present embodiment further includes:
A passivation layer 201 is formed on the semiconductor substrate 100, the passivation layer 201 covering the upper surface of the semiconductor substrate 100.
As an example, referring to fig. 7 to 11, each step of forming the isolation trench thin film filling structure in the peripheral trench 101 in the method for manufacturing the isolation trench thin film filling structure of the present embodiment is specifically described below:
first, step S1 is performed to provide a semiconductor substrate 100, wherein the peripheral trench 101 is formed in such a manner that an upper surface of the semiconductor substrate 100 includes a device region and a peripheral region surrounding the device region as shown in fig. 7, and the semiconductor substrate 100 is provided with the peripheral trench 101 in the peripheral region.
In the present embodiment, the semiconductor substrate 100 includes, but is not limited to, a silicon substrate.
Next, before executing step S2, the method for preparing the isolation trench thin film filling structure of the present embodiment further includes: a passivation layer 201 is formed on the semiconductor substrate 100, the passivation layer 201 covering the upper surface of the semiconductor substrate 100 as shown in fig. 7.
In this embodiment, nitride is used for the passivation layer 201.
As a preferred embodiment, siN is used for the passivation layer 201.
Next, step S2 is performed to form a pre-filling material 300 on the semiconductor substrate 100, where the pre-filling material 300 covers the upper surface of the passivation layer 201 and the sidewalls and bottom of the peripheral trench 101, and the pre-filling material 300 forms a necking neck 302 at the opening end of the peripheral trench 101, and the opening aperture of the necking neck 302 is smaller than the middle aperture of the pre-filling material 300 at the middle position of the peripheral trench 101, as shown in fig. 8.
In this embodiment, the pre-filled material 300 may be formed using a high density plasma deposition process, a plasma enhanced deposition process, an atmospheric/low pressure chemical vapor deposition process, a spin-on deposition process, or a surface oxidation process. Of course, the forming method of the preliminary filling material 300 is not limited thereto, and may be designed and adjusted according to actual needs.
It should be noted that the pre-filled material 300 may also protect the semiconductor substrate 100 from damage to the semiconductor substrate 100 during subsequent etching and deposition steps.
Next, step S3 is performed to pre-etch the pre-filled material 300 to remove the neck-down 302 of the pre-filled material 300, as shown in fig. 9.
The pre-filling material 300 improves its shape by pre-etching, so that the thickness of the pre-filling material at the step corner a of the peripheral trench 101 is less than or equal to the thickness of the pre-filling material at the sidewall of the peripheral trench 101, that is, the pre-filling material 300 can remove the necking 302 by pre-etching, as shown in fig. 9, so as to avoid forming a cavity between the high-density plasma oxide material 400 and the pre-filling material 300 when forming the high-density plasma oxide material 400, thereby causing a short circuit of a metal bit line formed subsequently. Since the profile of the pre-filled material 300 is improved by pre-etching, the thickness of the pre-filled material at the step corner of the peripheral trench 101 is smaller than or equal to the thickness of the pre-filled material at the sidewall of the peripheral trench 101, and the necking 302 is removed, so that the bond between the high-density plasma oxide material 400 and the pre-filled material 300 is good, and the void is not easy to form, thereby avoiding the problem of the short circuit of the metal bit line formed later.
Next, step S4 is performed to form a high-density plasma oxide material 400 on the upper surface of the semiconductor substrate 100, where the high-density plasma oxide material 400 further covers the pre-filled material 300 and fills the peripheral trench 101 in a void-free manner, as shown in fig. 10.
In this embodiment, the high-density plasma concentration range used in forming the high-density plasma oxide material 400 is 10E10E/cm or more 3 。
Finally, step S5 is performed to remove the high-density plasma oxide material 400 and the pre-filled material 300 on the semiconductor substrate 100 of the peripheral trench 101, so as to obtain the high-density plasma oxide layer 402 and the pre-filled layer 301 located in the peripheral trench 101, as shown in fig. 11, thereby obtaining the isolation trench film filling structure without voids.
As shown in fig. 11, in the step of forming the high-density plasma oxide layer 402 and the pre-filling layer 301, it includes:
the high-density plasma oxide material 400 and the pre-filling material 300 are sequentially etched until the upper surface of the passivation layer 201 is exposed, so that the high-density plasma oxide material 400 and the pre-filling material 300 outside the peripheral trench 101 are removed, and the peripheral trench 101 is filled with the residual parts of the high-density plasma oxide material 400 and the pre-filling material 300 to obtain the high-density plasma oxide layer 402 and the pre-filling layer 301, so that a void-free isolation trench film filling structure is formed.
The isolation trench thin film fill structure as shown in fig. 11 is finally formed by the above steps.
In addition, in the step of pre-etching the pre-filling material 300, the pre-filling layer at the step corner of the peripheral trench 101 is also cut off, so that the step corner of the peripheral trench 101 forms a chamfer, and the structure shown in fig. 12 is obtained, and the position B in fig. 12 is the structure after the pre-filling layer 301 at the step corner of the peripheral trench 101 is cut off and then is filled with the high-density plasma oxide layer 402. It will be appreciated that the presence of the chamfer can further enlarge the open aperture of the pre-filled layer 301 at the open end of the peripheral trench 101, thereby avoiding the formation of a necking neck 302 of too small an aperture.
In addition, in the present embodiment, in the step of pre-etching the pre-filling material 300, it includes: the pre-fabricated fill material 300 is etched using a high density plasma etch process while maintaining an etch pressure of 10-40 mtorr. It should be noted that if the etching pressure is greater than 50mtorr or less than 10mtorr, it will be easy to cut the pre-filled material 300 at the step corners of the peripheral trench 101 to form a chamfer. Preferably, the etching pressure is maintained at 20 to 30mtorr. More preferably, the etching pressure is kept at 25mtorr. In addition, NF is preferably used when etching the pre-fill material 300 using a high density plasma etching process 3 And (3) plasma.
Further, the etching depth of the high-density plasma etching process is controlled not to expose the step corners of the peripheral trench 101 when etching the pre-fill material 300.
In addition, in the present embodiment, a plurality of array trenches 102 in the device region are prepared on the semiconductor substrate 100 in addition to the peripheral trench 101 around the peripheral region, and the width of the peripheral trench 101 is more than twice the cell width of the array trench 102, as shown in fig. 13.
As another example, referring to fig. 13 to 17, each step of forming an isolation trench thin film filling structure in the peripheral trench 101 and the array trench 102 in the method for manufacturing an isolation trench thin film filling structure of the present embodiment is specifically described below:
first, step S1 is performed to provide a semiconductor substrate 100, wherein the peripheral trench 101 is shown in fig. 7, an upper surface of the semiconductor substrate 100 includes a device region and a peripheral region surrounding the device region, a plurality of array trenches 102 in the device region and a peripheral trench 101 in the peripheral region are formed on the semiconductor substrate 100, and the width of the peripheral trench 101 is more than twice the cell width of the array trenches 102, as shown in fig. 13.
It should be noted that, the peripheral trench 1011 is generally used to isolate the device with a low aspect ratio, and the array trench 1012 is arranged in an array with a high aspect ratio. Wherein, the depth-to-width ratio of the peripheral trench 1011 is 0.5:1-21:20, and the depth-to-width ratio of the array trench 1012 is 10:1-20:1.
Next, before executing step S2, the method for preparing the isolation trench thin film filling structure of the present embodiment further includes: a passivation layer 201 is formed on the semiconductor substrate 100, the passivation layer 201 covering the upper surface of the semiconductor substrate 100 as shown in fig. 13.
Next, step S2 is performed to form a pre-filling material 300 on the semiconductor substrate 100, where the pre-filling material 300 covers the upper surface of the passivation layer 201 and the sidewalls and bottom of the peripheral trench 101, and the pre-filling material 300 further fills the array trench 102 to define a plurality of active regions, and the pre-filling material 300 forms a necking neck 302 at the opening end of the peripheral trench 101, and the opening aperture of the necking neck 302 is smaller than the middle aperture of the pre-filling material 300 at the middle position of the peripheral trench 101, as shown in fig. 14.
Next, step S3 is performed to pre-etch the pre-filling material 300 to remove the necking neck 302 of the pre-filling material 300, as shown in fig. 15.
Next, step S4 is performed to form a high-density plasma oxide material 400 on the upper surface of the semiconductor substrate 100, where the high-density plasma oxide material 400 further covers the pre-filled material 300 and fills the peripheral trench 101 in a void-free manner, as shown in fig. 16.
Finally, step S5 is performed to remove the high-density plasma oxide material 400 and the pre-filled material 300 on the semiconductor substrate 100 to obtain the high-density plasma oxide layer 402 and the pre-filled layer 301 located in the peripheral trench 101, as shown in fig. 17, so as to obtain the isolation trench thin film filling structure without voids.
The isolation trench thin film fill structure as shown in fig. 17 is finally formed by the above steps.
It is readily appreciated that in forming the pre-fill material 300, the pre-fill material 300 can directly fill the array trench 102 to define a plurality of active regions, as shown in fig. 14. Therefore, the present embodiment is applicable to isolation trenches having a high aspect ratio and a low aspect ratio, and has a good film filling effect and substantially no voids.
According to the preparation method of the isolation groove film filling structure, before the high-density plasma oxide material is formed, the appearance of the prefabricated filling material is improved through pre-etching, so that the thickness of the prefabricated filling material at the corner of the isolation groove step is smaller than or equal to that of the prefabricated filling material at the side wall of the isolation groove, the bond between the high-density plasma oxide material and the prefabricated filling material is good, a cavity is not easy to form, and further the device failure caused by short circuit of a metal bit line formed later is avoided. In addition, the present embodiments are applicable to high/low aspect ratio isolation trenches, particularly low or medium aspect ratio isolation trenches. In addition, the high-density plasma etching process is adopted to etch the prefabricated filling material, and meanwhile, the integrity of the prefabricated filling material at the corner of the step of the isolation groove is guaranteed by controlling the etching pressure and the etching depth, so that the prefabricated filling material at the corner of the step of the isolation groove is prevented from being cut to cause circuit breaking and finally cause device failure.
The above steps of the methods are divided, for clarity of description, and may be combined into one step or split into multiple steps when implemented, so long as they contain the same logic relationship, and they are all within the protection scope of this patent; it is within the scope of this patent to add insignificant modifications to the algorithm or flow or introduce insignificant designs, but not to alter the core design of its algorithm and flow.
A second embodiment of the present invention is directed to a method for manufacturing a semiconductor memory device, including at least: the isolation trench thin film filling structure is prepared by adopting the preparation method of the isolation trench thin film filling structure according to the first embodiment of the invention.
It is not difficult to find that the first embodiment needs to be implemented in cooperation with the second embodiment, so that the related technical details mentioned in the first embodiment are still valid in the second embodiment, and in order to reduce repetition, a detailed description is omitted here. Accordingly, the related art details mentioned in the present embodiment can also be applied to the first embodiment.
According to the preparation method of the semiconductor memory device, the preparation method of the isolation groove film filling structure is adopted, so that the high-density plasma oxide material in the isolation groove film filling structure and the prefabricated filling material have good bonding effect, and the void-free film filling depth which is equal to the isolation groove depth can be provided together, so that the problem of short circuit of a metal bit line formed later is not easy to occur, the possibility of device failure is greatly reduced, and the device yield is improved; meanwhile, the prefabricated filling material at the corner of the step of the isolation groove is good, so that the circuit is not easy to break, and the yield of the device is further improved.
A third embodiment of the present invention relates to an isolation trench thin film filling structure, as shown in fig. 11 and 17, which includes at least:
a semiconductor substrate 100, wherein an upper surface of the semiconductor substrate 100 comprises a device region and a peripheral region surrounding the device region, a plurality of array trenches 102 in the device region and a peripheral trench 101 in the peripheral region are prepared on the semiconductor substrate 100, and the width of the peripheral trench 101 is more than twice the cell width of the array trenches 102;
a pre-fill layer 301 covering the sidewalls and bottom of the peripheral trench 101, the pre-fill material further filling the array trench 102 to define a plurality of active regions; the method comprises the steps of,
a high-density plasma oxide layer 402, the high-density plasma oxide layer 402 overlying the pre-filled layer 301 within the peripheral trench 101 and filling the peripheral trench 101;
the thickness of the pre-filling layer at the step corner of the peripheral trench 101 is less than or equal to the thickness of the pre-filling layer at the sidewall of the peripheral trench 101, so as to avoid the occurrence of a void between the high-density plasma oxide layer 402 and the pre-filling layer 301, which may cause a short circuit of a metal bit line formed later.
In this embodiment, the pre-fill layer 301 thickness at the stepped corners of the peripheral trench 101 is not so thick as to expose the stepped corners of the peripheral trench 101.
In addition, the isolation trench thin film filling structure of the present embodiment further includes:
a passivation layer 201 is formed overlying the upper surface of the semiconductor substrate 100, and a pre-filled layer 301 at the stepped corners of the peripheral trench 101 is formed to a thickness overlying the stepped corners of the peripheral trench 101.
And, the pre-filled layer 301 located at the stepped corner of the peripheral trench 101 is connected to the side edge of the passivation layer 201.
In addition, in the present embodiment, the aspect ratio of the peripheral trench 101 is 0.5:1 to 21:20, and the aspect ratio of the array trench 102 is 10:1 to 20:1.
In addition, in the present embodiment, a chamfer may be formed at the step corner of the peripheral groove 101 as shown in fig. 12. It will also be appreciated that the presence of the chamfer can further enlarge the open aperture of the pre-filled layer 301 at the open end of the peripheral trench 101, thereby avoiding the formation of a necking neck 302 of too small an aperture.
It is to be noted that this embodiment is a product embodiment corresponding to the first embodiment, and this embodiment can be implemented in cooperation with the first embodiment. The related technical details mentioned in the first embodiment are still valid in this embodiment, and in order to reduce repetition, a detailed description is omitted here. Accordingly, the related art details mentioned in the present embodiment can also be applied to the first embodiment.
According to the isolation groove film filling structure, the thickness of the prefabricated filling layer at the corner of the isolation groove step is smaller than or equal to that of the prefabricated filling layer at the side wall of the isolation groove, so that a cavity is avoided between the high-density plasma oxide layer and the prefabricated filling material layer, and further, the device failure caused by short circuit of a metal bit line formed later is avoided. In addition, the present embodiments are applicable to high/low aspect ratio isolation trenches, particularly low or medium aspect ratio isolation trenches.
A fourth embodiment of the present invention relates to a semiconductor memory device including at least: an isolation trench thin film fill structure according to a third embodiment of the present invention.
It is not difficult to find that the semiconductor memory device according to the present embodiment adopts the isolation trench thin film filling structure according to the third embodiment of the present invention, so that the related technical details mentioned in the third embodiment are still valid in the present embodiment, and in order to reduce repetition, a detailed description thereof is omitted. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the third embodiment.
A fifth embodiment of the present invention relates to a semiconductor memory device, as shown in fig. 11, including at least:
A semiconductor substrate 100;
a plurality of peripheral trenches 101 formed on the semiconductor substrate 100 and surrounding a plurality of active regions located on the semiconductor substrate 100;
a pre-filled layer 301 covering the sidewalls and bottom of the peripheral trench 101; the method comprises the steps of,
a high-density plasma oxide layer 402 covering the pre-filled layer 301 and filling the peripheral trench 101;
wherein the high-density plasma oxide layer 402 and the pre-filled layer 301 together fill the peripheral trench 101 and together provide a void-free thin film fill depth equal to the depth of the peripheral trench 101.
In addition, in the present embodiment, the thickness of the pre-filling layer 301 at the step corner of the peripheral trench 101 is equal to or less than the thickness at the side wall of the peripheral trench 101 near the bottom, so as to directly form the void-free thin film filling depth.
In addition, in the present embodiment, the aspect ratio of the peripheral trench 101 is 0.5:1 to 21:20.
In addition, the semiconductor memory device of the present embodiment further includes a plurality of metal bit lines disposed on the semiconductor substrate 100, the ends of the metal bit lines extending to the high-density plasma oxide layer 402 within the peripheral trench 101.
The semiconductor memory device of the embodiment can be well bonded between the high-density plasma oxide layer and the prefabricated filling layer, and can jointly provide the void-free film filling depth equal to the isolation groove depth, so that the problem of short circuit of a metal bit line formed later is not easy to occur, the possibility of device failure is greatly reduced, and the device yield is improved; meanwhile, the prefabricated filling material at the corner of the step of the isolation groove is good, so that the circuit is not easy to break, and the yield of the device is further improved.
In summary, the isolation trench film filling structure, the semiconductor memory device and the preparation method of the invention have the following beneficial effects:
according to the isolation groove film filling structure and the preparation method thereof, before the high-density plasma oxide material is formed, the appearance of the prefabricated filling material is improved through pre-etching, so that the thickness of the prefabricated filling material at the corner of the isolation groove step is smaller than or equal to that of the prefabricated filling material at the side wall of the isolation groove, the bond between the high-density plasma oxide material and the prefabricated filling material is good, a cavity is not easy to form, and further the device failure caused by short circuit of a metal bit line formed later is avoided. In addition, the present invention is applicable to high/low aspect ratio isolation trenches, particularly low or medium aspect ratio isolation trenches. In addition, the invention adopts a high-density plasma etching process to etch the prefabricated filling material, and simultaneously ensures the integrity of the step corners of the isolation groove by controlling the etching pressure and the etching depth, thereby avoiding the circuit breaking caused by the cutting of the step corners of the isolation groove and finally causing the failure of the device. In addition, the invention can form a chamfer on the prefabricated filling layer at the corner of the step of the peripheral groove, further enlarge the aperture of the prefabricated filling layer at the opening end of the peripheral groove, facilitate the subsequent high-density plasma oxide layer filling formation, further reduce the generation of voids and improve the yield of devices.
The semiconductor memory device and the preparation method thereof adopt the isolation groove film filling structure and the preparation method thereof to prepare the isolation groove film filling structure, the high-density plasma oxide material in the isolation groove film filling structure and the prefabricated filling material have good bonding effect, and the void-free film filling depth which is equal to the isolation groove depth can be provided together, so that the problem of short circuit of a metal bit line formed later is not easy to occur, the possibility of device failure is greatly reduced, and the device yield is improved; meanwhile, the prefabricated filling material at the corner of the step of the isolation groove is good, so that the circuit is not easy to break, and the yield of the device is further improved.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (15)

1. The preparation method of the isolation groove film filling structure is characterized by at least comprising the following steps:
providing a semiconductor substrate, wherein an upper surface of the semiconductor substrate comprises a device region and a peripheral region surrounding the device region, a plurality of array grooves in the device region and a peripheral groove in the peripheral region are prepared on the semiconductor substrate, and the width of the peripheral groove is more than twice the cell width of the array groove;
forming a prefabricated filling material on the upper surface of the semiconductor substrate, wherein the prefabricated filling material further covers the upper surface of the semiconductor substrate and the side walls and the bottom of the peripheral groove, the prefabricated filling material further fills the array groove and is used for defining a plurality of active areas, a necking neck is formed at the opening end of the peripheral groove by the prefabricated filling material, and the opening aperture of the necking neck is smaller than the middle aperture of the prefabricated filling material at the middle position of the peripheral groove;
pre-etching the prefabricated filling material to remove the necking neck of the prefabricated filling material, cutting off the prefabricated filling layer at the step corners of the peripheral groove, and forming a chamfer at each corner, wherein the chamfer enables the opening aperture of the opening end of the peripheral groove to be larger than the width of the groove;
Forming a high-density plasma oxide material on the upper surface of the semiconductor substrate, wherein the high-density plasma oxide material further covers the prefabricated filling material and fills the peripheral groove in a void-free manner; the method comprises the steps of,
and removing the high-density plasma oxide material and the prefabricated filling material on the semiconductor substrate to obtain a high-density plasma oxide layer and a prefabricated filling layer which are positioned in the peripheral groove.
2. The method of fabricating an isolation trench thin film fill structure as defined in claim 1, wherein in the step of pre-etching said pre-fill material, comprising: and etching the prefabricated filling material by adopting a high-density plasma etching process, and simultaneously keeping the etching pressure at 10 millitorr-40 millitorr.
3. The method of claim 2, wherein the etching depth of the high-density plasma etching process is controlled so as not to expose the step corners of the peripheral trench when etching the pre-formed filling material.
4. The method of fabricating an isolation trench thin film fill structure as defined in claim 1, wherein in the step of removing said high density plasma oxide layer and said pre-filled layer, comprising:
And sequentially etching the high-density plasma oxide material and the prefabricated filling material until the upper surface of the semiconductor substrate is exposed, so that the high-density plasma oxide material and the prefabricated filling material outside the peripheral groove are removed, and the peripheral groove is filled with the high-density plasma oxide material and the residual part of the prefabricated filling material to obtain the high-density plasma oxide layer and the prefabricated filling layer, so that a void-free isolation groove film filling structure is formed.
5. The method of fabricating an isolation trench thin film fill structure of claim 1, wherein prior to forming the pre-formed fill material, the method of fabricating an isolation trench thin film fill structure further comprises:
and forming a passivation layer on the semiconductor substrate, wherein the passivation layer covers the upper surface of the semiconductor substrate.
6. The method of claim 1, wherein the aspect ratio of the peripheral trench is 0.5:1-21:20 and the aspect ratio of the array trench is 10:1-20:1.
7. The method of claim 1, wherein the pre-formed filling material is formed by a high density plasma deposition process, a plasma enhanced deposition process, an atmospheric/low pressure chemical vapor deposition process, a spin-on deposition process, or a surface oxidation process.
8. An isolation trench thin film fill structure, the isolation trench thin film fill structure comprising at least:
a semiconductor substrate, wherein an upper surface of the semiconductor substrate comprises a device region and a peripheral region surrounding the device region, a plurality of array grooves in the device region and a peripheral groove in the peripheral region are prepared on the semiconductor substrate, and the width of the peripheral groove is more than twice the cell width of the array groove;
a pre-filled layer covering the sidewalls and bottom of the peripheral trench, the pre-filled layer further filling the array trench to define a plurality of active regions; the method comprises the steps of,
a high-density plasma oxide layer covering the pre-fabricated filling layer within the peripheral trench and filling the peripheral trench;
the prefabricated filling layer at the step corner of the peripheral groove is provided with a chamfer, the thickness of the prefabricated filling layer at the step corner of the peripheral groove is smaller than or equal to that of the prefabricated filling layer at the side wall of the peripheral groove, and the chamfer enables the opening aperture of the opening end of the peripheral groove to be larger than the width of the groove, so that the problem that a cavity exists between the high-density plasma oxide layer and the prefabricated filling layer to cause a short circuit of a metal bit line formed later is avoided.
9. The isolation trench thin film fill structure of claim 8, further comprising a passivation layer formed overlying an upper surface of the semiconductor substrate, and wherein the pre-fill layer thickness at the peripheral trench step corners overlies the peripheral trench step corners.
10. The isolation trench thin film fill structure of claim 9, wherein the pre-fill layer at the peripheral trench step corner is connected to a side edge of the passivation layer.
11. The isolation trench thin film fill structure of claim 8, wherein the peripheral trench has an aspect ratio of 0.5:1-21:20 and the array trench has an aspect ratio of 10:1-20:1.
12. A semiconductor memory device, the semiconductor memory device comprising at least:
a semiconductor substrate;
a plurality of peripheral trenches formed on the semiconductor substrate and surrounding a plurality of active regions located on the semiconductor substrate;
a prefabricated filling layer covering the side wall and the bottom of the peripheral groove; the method comprises the steps of,
a high-density plasma oxide layer covering the pre-filled layer and filling the peripheral trench;
Wherein the step corners of the peripheral trench are formed with a cut angle, the high-density plasma oxide layer and the pre-filled layer together fill the peripheral trench and together provide a void-free film fill depth equal to the peripheral trench depth.
13. The semiconductor memory device of claim 12, wherein a thickness of the pre-filled layer at the peripheral trench step corner is less than or equal to a thickness of the peripheral trench sidewall near the bottom for direct formation of the void-free thin film fill depth.
14. The semiconductor memory device of claim 12, wherein the peripheral trench has an aspect ratio of 0.5:1 to 21:20.
15. The semiconductor memory device according to any one of claims 12 to 14, further comprising a plurality of metal bit lines provided on the semiconductor substrate, an end of the metal bit lines extending onto the high-density plasma oxide layer within the peripheral trench.
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