KR100478488B1 - Semiconductor device and fabrication method thereof - Google Patents
Semiconductor device and fabrication method thereof Download PDFInfo
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- KR100478488B1 KR100478488B1 KR10-2002-0076817A KR20020076817A KR100478488B1 KR 100478488 B1 KR100478488 B1 KR 100478488B1 KR 20020076817 A KR20020076817 A KR 20020076817A KR 100478488 B1 KR100478488 B1 KR 100478488B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Abstract
반도체 소자의 트렌치 산화막을 형성하는 방법에 관한 것으로, 그 목적은 보이드가 형성되지 않고 트렌치가 완전히 매립되도록 트렌치 산화막을 형성하는 방법을 제공하는 것이다. 이를 위해 본 발명에서는 트렌치 형성을 위한 식각 시, 실리콘 질화막의 풀백 습식식각 공정을 이용하여 트렌치의 내벽이 계단형상을 가지도록 다단계로 식각하고, 계단형상의 구석부분에 절연막을 1차로 매립한 다음, 그 위에 트렌치 산화막을 형성하는 특징이 있다.The present invention relates to a method of forming a trench oxide film of a semiconductor device, and an object thereof is to provide a method of forming a trench oxide film so that a trench is completely embedded without voids being formed. To this end, in the present invention, when etching to form a trench, the inner wall of the trench is etched in multiple steps using a pullback wet etching process of a silicon nitride film, and an insulating film is first embedded in a stepped corner portion. It is characterized by forming a trench oxide film thereon.
Description
본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 트렌치 산화막을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for forming a trench oxide film.
반도체 소자의 격리구조로서 트렌치 격리구조 (STI : shallow trench isolation)가 많이 사용되고 있다. 트렌치 격리구조에서는 반도체 기판 내에 트렌치를 형성하고 그 내부에 절연물질을 충진시킴으로써 필드영역의 크기를 목적한 트렌치의 크기로 제한하기 때문에 반도체 소자의 미세화에 유리하다.As the isolation structure of the semiconductor device, a trench trench structure (STI: shallow trench isolation) is widely used. In the trench isolation structure, by forming a trench in a semiconductor substrate and filling an insulating material therein, the size of the field region is limited to the desired trench size, which is advantageous for miniaturization of semiconductor devices.
그러면, 종래 트렌치 격리구조의 반도체 소자 제조 방법에 대해 첨부된 도면을 참조하여 설명하면 다음과 같다. 도 1a 내지 도 1b는 종래 반도체 소자 제조 방법을 도시한 단면도이다. Next, a method of manufacturing a semiconductor device having a conventional trench isolation structure will be described with reference to the accompanying drawings. 1A to 1B are cross-sectional views illustrating a conventional semiconductor device manufacturing method.
먼저, 도 1a에 도시된 바와 같이, 반도체 기판(1) 상에 패드산화막(2)을 200Å 정도 증착하고, 그 위에 실리콘질화막(2)을 증착한 후, 그 상부에 감광막을 도포하고 노광하여 트렌치로 예정된 영역의 상부에 해당하는 감광막만을 제거하여 감광막 패턴(미도시)을 형성하고, 감광막 패턴을 마스크로 하여 노출된 실리콘질화막(3), 패드산화막(2) 및 목적하는 소정깊이의 기판(1)을 건식식각하여 반도체 기판(1) 내에 트렌치(100)를 형성한 다음, 감광막 패턴을 제거하고 세정공정을 수행한다.First, as shown in FIG. 1A, a pad oxide film 2 is deposited on the semiconductor substrate 1 by about 200 microseconds, a silicon nitride film 2 is deposited thereon, and then a photoresist film is applied and exposed on the trench. A photoresist pattern (not shown) is formed by removing only the photoresist film corresponding to the upper portion of the predetermined region, and the exposed silicon nitride film 3, the pad oxide film 2, and the substrate 1 having a desired depth are exposed. ), The trench 100 is formed in the semiconductor substrate 1, and then the photoresist pattern is removed and a cleaning process is performed.
이 때, 실리콘질화막(3)은 후속공정인 화학기계적 연마공정에서 종료층 역할을 하게 된다.At this time, the silicon nitride film 3 serves as an end layer in a subsequent chemical mechanical polishing process.
다음, 도 1b에 도시된 바와 같이, 트렌치(100)의 내부를 포함한 상부 전면에 트렌치(100)를 충분히 충진시키도록 트렌치 산화막(4)을 두껍게 증착한다.Next, as shown in FIG. 1B, a thick trench oxide film 4 is deposited to sufficiently fill the trench 100 in the upper front surface including the inside of the trench 100.
이후에는 실리콘질화막(3)이 노출될 때까지 트렌치 산화막(4)을 화학기계적 연마하여 평탄화시킴으로써, 트렌치 격리공정을 완료한다.Thereafter, the trench isolation process is completed by chemical mechanical polishing and planarization of the trench oxide film 4 until the silicon nitride film 3 is exposed.
그런데, 소자의 고집적화에 따라 트렌치 폭의 감소와 깊이의 증가로 인해 트렌치의 종횡비(aspect ratio)가 커지면 트렌치 산화막(4) 증착시 보이드(5)가 발생할 가능성이 증가하는 문제점이 있었다.However, due to the high integration of the device, a decrease in the trench width and an increase in the depth increase the aspect ratio of the trench, thereby increasing the possibility of the voids 5 occurring when the trench oxide film 4 is deposited.
이와 같이 트렌치 산화막(4) 내에 보이드(5)가 발생하면 트렌치 산화막의 평탄화를 위한 화학기계적 연마시 그 보이드(5)가 노출되어 평탄화가 어려워지고, 평탄화 후 보이드가 노출되어 있다가 후속 공정에서 전극 형성용으로 증착하는 폴리실리콘이 보이드로 들어가면 누설전류가 발생하여 소자의 오동작을 유발하는 등 소자에 치명적인 악영향을 미치는 문제점이 있었다.As such, when the voids 5 are generated in the trench oxide film 4, the voids 5 are exposed during chemical mechanical polishing for planarization of the trench oxide film, making it difficult to planarize. When polysilicon deposited for formation enters the voids, there is a problem in that a leakage current occurs to cause a device malfunction, such as a fatal adverse effect on the device.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 보이드가 형성되지 않고 트렌치가 완전히 매립되도록 트렌치 산화막을 형성하는 방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method of forming a trench oxide film so that a void is not formed and the trench is completely filled.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 트렌치 형성을 위한 식각 시, 실리콘 질화막의 풀백 습식식각 공정을 이용하여 트렌치의 내벽이 계단형상을 가지도록 다단계로 식각하고, 계단형상의 구석부분에 절연막을 1차로 매립한 다음, 그 위에 트렌치 산화막을 형성하는 특징이 있다.In order to achieve the object as described above, in the present invention, when the trench is formed for etching, the inner wall of the trench is etched in multiple steps using a pullback wet etching process of a silicon nitride layer, and in stepped corner portions. The insulating film is primarily buried, and then a trench oxide film is formed thereon.
즉, 본 발명에 따른 반도체 소자 방법은, 반도체 기판 상에 실리콘질화막을 형성하고, 실리콘질화막 및 소정두께의 반도체 기판을 선택적으로 식각하여 반도체 기판 내에 1차로 트렌치 바닥부를 형성하는 단계; 실리콘질화막을 습식식각하여 트렌치 바닥부와 인접한 실리콘질화막의 가장자리를 소정폭 제거한 후, 소정폭 제거된 실리콘질화막을 마스크로 하여 노출된 반도체 기판을 식각하여 트렌치를 형성함으로써, 트렌치의 내부 측벽을 계단형상으로 만드는 단계; 트렌치의 내부 및 실리콘질화막을 포함한 상부 전면에 1차 절연막을 형성하되, 1차 절연막의 상부표면이 트렌치 내부 측벽의 계단형상을 유지할 수 있는 정도의 균일한 두께로 1차 절연막을 형성하는 단계; 실리콘질화막이 노출될 때까지 1차 절연막을 에치백하여 1차 절연막을 계단형상의 구석부분에 매립되도록 남김으로써, 1차 절연막 표면이 트렌치 측벽의 평균기울기를 가지도록 만드는 단계; 및 1차 절연막 상에 트렌치의 내부를 매립하도록 2차 절연막을 형성하는 단계를 포함하여 이루어진다.That is, the semiconductor device method according to the present invention comprises the steps of forming a silicon nitride film on the semiconductor substrate, selectively etching the silicon nitride film and the semiconductor substrate of a predetermined thickness to form a trench bottom portion in the semiconductor substrate first; After the silicon nitride film is wet etched to remove the edges of the silicon nitride film adjacent to the trench bottom by a predetermined width, the exposed semiconductor substrate is etched using the removed silicon nitride film as a mask to form a trench, thereby forming a stepped inner sidewall of the trench. Making step; Forming a primary insulating film on the entire upper surface including the inside of the trench and the silicon nitride film, the primary insulating film having a uniform thickness such that the upper surface of the primary insulating film can maintain the stepped shape of the inner sidewall of the trench; Etching back the primary insulating film until the silicon nitride film is exposed, thereby leaving the primary insulating film embedded in the stepped corners, such that the surface of the primary insulating film has an average slope of the trench sidewalls; And forming a secondary insulating film to fill the inside of the trench on the primary insulating film.
이 때 트렌치의 내부 측벽을 계단형상으로 만드는 단계에서, 습식식각에 의해 소정폭 제거된 실리콘질화막을 마스크로 하여 노출된 반도체 기판을 식각하여 트렌치를 형성한 이후에, 실리콘질화막을 다시 습식식각하여 트렌치와 인접한 실리콘질화막의 가장자리를 소정폭 더 제거함으로써, 계단형상을 하나 더 만들 수도 있다.At this time, in the step of forming the inner sidewall of the trench as a step, by etching the exposed semiconductor substrate using a silicon nitride film removed by a predetermined width as a mask to form a trench, the silicon nitride film is wet-etched again to trench By further removing the edges of the silicon nitride film adjacent to and by a predetermined width, one more stepped shape may be formed.
실리콘질화막은 1500-3000Å 두께로 증착하는 것이 바람직하다.The silicon nitride film is preferably deposited to a thickness of 1500-3000 mm 3.
반도체 기판 상에는 패드산화막을 100-300Å 두께로 형성하고, 패드산화막 상에 실리콘질화막을 형성하며, 따라서 1차로 트렌치 바닥부를 형성할 때에는 실리콘질화막, 패드산화막 및 소정두께의 반도체 기판을 선택적으로 식각하여 반도체 기판 내에 1차로 트렌치 바닥부를 형성하는 것이 바람직하다.A pad oxide film is formed on the semiconductor substrate to a thickness of 100-300Å, and a silicon nitride film is formed on the pad oxide film. Therefore, when forming the trench bottom portion, the silicon nitride film, the pad oxide film, and the semiconductor substrate having a predetermined thickness are selectively etched to form a semiconductor. It is desirable to form the trench bottom first in the substrate.
트렌치 바닥부를 형성할 때에는 반도체 기판을 300-700Å의 두께만큼 식각하여 트렌치 바닥부가 패드산화막의 상면으로부터 400-1000Å의 깊이를 가지고, 트렌치 바닥부의 폭은 최종적으로 형성되는 트렌치의 폭에 비해 10-40% 만큼 작은 폭을 가지도록 선택적 식각하는 것이 바람직하다.When the trench bottom is formed, the semiconductor substrate is etched by a thickness of 300-700 kPa, so that the trench bottom has a depth of 400-1000 kPa from the top surface of the pad oxide film, and the width of the trench bottom is 10-40 to the width of the finally formed trench. It is desirable to selectively etch to have a width as small as%.
실리콘질화막을 습식식각하여 트렌치 바닥부와 인접한 실리콘질화막의 가장자리를 소정폭 제거할 때에는, 한 쪽에서 트렌치 바닥부의 전체폭에 비해 5-15% 만큼을 제거하는 것이 바람직하다.When the silicon nitride film is wet etched to remove a predetermined width of the edge of the silicon nitride film adjacent to the trench bottom portion, it is preferable to remove 5-15% of one side of the trench bottom portion from the entire width of the trench bottom portion.
실리콘질화막을 습식식각할 때에는 실리콘질화막의 식각율이 패드산화막 및 반도체 기판의 식각율에 비해 40:1 이상으로 식각선택비가 큰 식각 케미칼을 사용하는 것이 바람직하며, 식각 케미칼로서 인산(H3PO4)을 사용할 수 있다.When wet etching the silicon nitride film, it is preferable to use an etch chemical having a large etching selectivity such that the etching rate of the silicon nitride film is 40: 1 or more relative to that of the pad oxide film and the semiconductor substrate, and phosphoric acid (H 3 PO 4) ) Can be used.
1차 절연막으로는 산화막을 상기 습식식각에 의해 제거하는 실리콘질화막의 폭인, 한 쪽에서 트렌치 바닥부의 전체폭에 비해 5-15% 만큼의 두께로 형성하는 것이 바람직하다.As the primary insulating film, it is preferable to form a thickness of 5-15% of the thickness of the trench bottom portion on one side, which is the width of the silicon nitride film from which the oxide film is removed by the wet etching.
2차 절연막은 형성할 때에는, 1차 절연막, 실리콘질화막, 및 트렌치의 내부를 포함하는 상부 전면에 트렌치의 내부를 매립하도록 2차 산화막을 형성한 후, 실리콘절연막이 노출될 때까지 2차 산화막을 화학기계적 연마하는 것이 바람직하다.When the secondary insulating film is formed, a secondary oxide film is formed in the upper entire surface including the primary insulating film, the silicon nitride film, and the inside of the trench so as to fill the inside of the trench, and then the secondary oxide film is formed until the silicon insulating film is exposed. Chemical mechanical polishing is preferred.
이하, 본 발명에 따른 반도체 소자 및 그 제조 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다. Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 따른 반도체 소자는 도 2e에 도시되어 있으며, 여기에는 반도체 기판(11) 내에 소자분리 영역으로서 형성되어 절연물질로 매립된 트렌치가 형성된 것이 도시되어 있다.The semiconductor device according to the present invention is shown in FIG. 2E, in which a trench formed as an isolation region in the semiconductor substrate 11 and filled with an insulating material is formed.
이 때, 트렌치는 반도체 기판(11)의 내부에서 표면으로 갈수록 폭이 넓어지는 모양을 가지며, 트렌치 내부의 측벽은 계단형상인 것이 특징이다.At this time, the trench has a shape in which the width becomes wider from the inside of the semiconductor substrate 11 toward the surface, and the sidewalls inside the trench are stepped.
트렌치 측벽 계단형상의 구석부분에는 1차 산화막(14)이 매립되도록 형성되어 1차 산화막(14)의 외면이 트렌치 측벽의 평균기울기를 가진다.The trench sidewall stepped corner portions are formed so that the primary oxide film 14 is embedded so that the outer surface of the primary oxide film 14 has an average slope of the trench sidewalls.
1차 산화막(14) 상에는 트렌치의 내부를 매립하도록 2차 산화막(15)이 형성되어 있다.On the primary oxide film 14, a secondary oxide film 15 is formed to fill the inside of the trench.
그러면, 이와 같은 반도체 소자를 제조하는 방법에 대해 도 2a 내지 도 2e를 참조하여 설명한다. 도 2a 내지 도 2e는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Next, a method of manufacturing such a semiconductor device will be described with reference to FIGS. 2A to 2E. 2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11) 상에 패드산화막(12)을 얇게 증착하고, 패드산화막(12) 위에 실리콘질화막(13)을 증착한 후, 그 상부에 감광막을 도포하고 노광하여 트렌치로 예정된 영역의 상부에 해당하는 감광막만을 제거하여 감광막 패턴(미도시)을 형성한다. First, as shown in FIG. 2A, a thin pad oxide film 12 is deposited on the semiconductor substrate 11, a silicon nitride film 13 is deposited on the pad oxide film 12, and then a photoresist film is applied thereon. The photoresist film pattern (not shown) is formed by exposing only the photoresist film corresponding to the upper portion of the region intended as the trench by exposure.
이 때, 패드산화막(12)은 실리콘질화막(13) 자체의 스트레스가 반도체 기판(11)에 그대로 전달되는 것을 억제하기 위해 선택적으로 증착하는 것으로서 100-300Å 정도의 두께로 얇게 증착하는 것이 바람직하다.At this time, the pad oxide film 12 is selectively deposited in order to suppress the stress of the silicon nitride film 13 itself from being transferred to the semiconductor substrate 11 as it is, preferably deposited in a thin thickness of about 100-300 kPa.
실리콘질화막(13)은 산화막과의 선택비가 큰 재료이므로 후속공정인 트렌치 산화막의 화학기계적 연마 공정에서 종료층 역할을 하며 보통 1500-3000Å 정도의 두께로 증착하는 것이 바람직하고, 일 예로서 2000Å 두께로 증착할 수 있다.Since the silicon nitride film 13 is a material having a high selectivity with respect to the oxide film, the silicon nitride film 13 serves as a termination layer in the subsequent chemical mechanical polishing process of the trench oxide film, and is preferably deposited at a thickness of about 1500-3000 mm 3. Can be deposited.
또한, 감광막 패턴에서 오프닝된 부분의 폭은, 이후 트렌치 내벽을 계단형으로 만드는 것을 감안하여 최종 트렌치 폭보다는 약 10-40% 정도 작도록 감광막 패턴을 형성하는 것이 바람직하며, 최종 트렌치 폭보다 작은 정도는 계단형으로 만드는 회수에 비례하여 10-40% 범위에서 정한다. In addition, the width of the opened portion of the photoresist pattern is preferably formed to form the photoresist pattern to be about 10-40% smaller than the final trench width, in consideration of making the trench inner wall stepped later, and less than the final trench width. Is in the range of 10-40% relative to the number of steps to be cascaded.
이어서, 감광막 패턴을 마스크로 하여 노출된 실리콘질화막(13), 패드산화막(12)을 식각하고 그 후 반도체 기판(11)을 소정깊이로 얕게 건식식각하여 1차로 트렌치 바닥부를 형성한 후, 감광막 패턴을 제거하고 세정공정을 수행한다.Subsequently, the exposed silicon nitride film 13 and the pad oxide film 12 are etched using the photoresist pattern as a mask, and then the semiconductor substrate 11 is dry-etched shallowly to a predetermined depth to form a trench bottom portion first, and then the photoresist pattern Is removed and a cleaning process is performed.
이 때, 패드산화막(12)의 식각 이후에 식각하는 반도체 기판의 깊이는 300-700Å 정도, 바람직하게는 500Å 정도의 깊이로 식각한다. 따라서, 트렌치 바닥부는 패드산화막의 상면으로부터 400-1000Å 정도의 깊이로 형성된다.At this time, the depth of the semiconductor substrate to be etched after the pad oxide film 12 is etched to a depth of about 300-700 kPa, preferably about 500 kPa. Thus, the trench bottom is formed to a depth of about 400-1000 mm from the top surface of the pad oxide film.
다음, 도 2b에 도시된 바와 같이, 실리콘질화막(13)을 습식식각으로 1차 제거한다. 습식식각을 할 때에는 실리콘질화막(13)만을 식각하고 그 외 패드산화막(12)이나 반도체 기판(11)은 거의 식각하지 않도록 식각선택비가 큰 식각 케미칼을 사용하며, 바람직하게는 실리콘질화막(13)의 식각율이 패드산화막(12) 및 반도체 기판(11)의 식각율에 비해 40:1 이상으로 식각선택비가 큰 식각 케미칼을 사용한다.Next, as shown in FIG. 2B, the silicon nitride film 13 is first removed by wet etching. When wet etching, only the silicon nitride film 13 is etched, and an etchant having a large etching selectivity is used so that the pad oxide film 12 and the semiconductor substrate 11 are hardly etched. Preferably, the silicon nitride film 13 An etching chemical having an etching selectivity of greater than 40: 1 compared to the etching rates of the pad oxide film 12 and the semiconductor substrate 11 is used.
일 예로서, 실리콘질화막:패드산화막:폴리실리콘(반도체 기판)의 식각비가 40:1:0 인 인산(H3PO4)을 사용할 수 있다.As an example, phosphoric acid (H 3 PO 4 ) having an etching ratio of 40: 1: 0 of silicon nitride film: pad oxide film: polysilicon (semiconductor substrate) may be used.
그러면 실리콘질화막(13)은 등방성 식각인 습식식각에 의해 두께방향과 측방으로 동시에 식각되어 결과적으로 트랜치 바닥부의 가장자리에 인접한 실리콘질화막(13)이 소정폭만큼 1차로 제거되고 제거된 부분을 통해 패드산화막(12)이 소정폭 노출된다. 이러한 실리콘질화막의 습식식각 공정은 트렌치의 풀백(pull back) 습식식각으로 알려져 있는 공정이다.Then, the silicon nitride film 13 is etched simultaneously in the thickness direction and laterally by wet etching, which is an isotropic etching, and as a result, the silicon oxide film 13 adjacent to the edge of the trench bottom is first removed by a predetermined width and then pad oxide film through the removed portion. (12) is exposed to a predetermined width. The wet etching process of the silicon nitride film is a process known as pull back wet etching of trenches.
이러한 풀백 습식식각 공정을 통해 트렌치의 내벽을 계단형상으로 제작하는데, 본 발명에서는 트렌치의 깊이 및 폭을 고려하여 이러한 풀백 습식식각 공정을 한번 또는 두 번 이상 반복 수행함으로써 계단형상의 개수를 하나 또는 둘 이상으로 형성한다. Through the pullback wet etching process, the inner wall of the trench is manufactured in a stepped shape. In the present invention, the number of stepped shapes is one or two by repeating the fullback wet etching process one or two times in consideration of the depth and width of the trench. It forms as above.
도 2b에서와 같이 1차 풀백 습식식각 공정을 통해 노출되는 패드산화막(12)의 폭은 한 쪽에서 트렌치 바닥부의 전체폭에 비해 5-15% 정도가 되는 것이 적당하다. 일 예로서, 도 2a에서 1차로 형성한 트렌치 영역의 폭을 2500Å으로 할 경우, 습식식각에 의해 노출되는 패드산화막의 폭은 한 쪽에서 250Å씩이 되도록 하며 따라서 총 500Å만큼 트렌치의 폭이 더 넓어진 결과로 만들 수 있다.As shown in FIG. 2B, the width of the pad oxide layer 12 exposed through the first pullback wet etching process may be about 5-15% of the width of the trench bottom portion on one side. As an example, when the width of the trench region formed primarily in FIG. 2A is set to 2500 mW, the width of the pad oxide film exposed by wet etching is 250 m3 on one side, and thus the width of the trench is wider by 500 mW in total. Can be made with
다음, 도 2c에 도시된 바와 같이, 실리콘질화막(13)을 마스크로 하여 노출된 패드산화막(12) 및 목적하는 소정깊이의 반도체 기판(11)을 건식식각하여 트렌치를 형성하며, 이 때에는 통상적인 트렌치 깊이만큼 식각하도록 한다. Next, as shown in FIG. 2C, the trench is formed by dry etching the exposed pad oxide film 12 and the semiconductor substrate 11 having a desired depth by using the silicon nitride film 13 as a mask. Etch as deep as the trench.
다음, 도 2d에 도시된 바와 같이, 다시 한번 풀백 습식식각 공정을 수행하여 실리콘질화막(13)을 소정폭만큼 2차로 제거하고 제거된 부분을 통해 패드산화막(12)을 소정폭 노출시킨다. 이러한 2차 풀백 습식식각 공정(도 2d)으로 제거되는 실리콘질화막(13)의 폭은 이전에 수행하였던 1차 풀백 습식식각 공정(도 2b)에서 1차로 제거되었던 폭과 동일한 수준으로 하며, 결과적으로 트렌치를 계단형상의 내벽을 가지면서 가장자리로 갈수록 넓어지는 모양으로 형성한다. Next, as shown in FIG. 2D, the pull back wet etching process is once again performed to remove the silicon nitride layer 13 by a predetermined width and expose the pad oxide layer 12 through the removed portion. The width of the silicon nitride film 13 removed by the second full back wet etching process (FIG. 2D) is the same as the width that was first removed in the first full back wet etching process (FIG. 2B). The trench is formed to have a stepped inner wall and widen toward the edge.
이어서, 노출된 패드산화막(12), 실리콘질화막(13) 및 트렌치의 내벽을 포함하여 반도체 기판의 상부 전면에 표면형상을 따라 1차 산화막(14)을 증착한다. 이 때 1차 산화막(14)의 상부표면이 트렌치 내부 측벽의 계단형상을 유지할 수 있는 정도의 균일한 두께로 1차 산화막(14)을 증착하며 그 두께는 한번의 풀백 습식식각 공정에서 제거하는 실리콘질화막의 폭과 동일한 수준이 되도록, 즉, 한 쪽에서 트렌치 바닥부의 전체폭에 비해 5-15% 만큼의 두께로 증착한다.Subsequently, the primary oxide film 14 is deposited along the surface of the upper surface of the semiconductor substrate, including the exposed pad oxide film 12, the silicon nitride film 13, and the inner wall of the trench. At this time, the primary oxide layer 14 is deposited to a uniform thickness such that the upper surface of the primary oxide layer 14 can maintain the stepped shape of the inner sidewall of the trench, and the thickness thereof is removed in one pull-back wet etching process. The deposition is performed at a level equal to the width of the nitride film, i.e., 5-15% of the thickness of the trench bottom on one side.
다음, 도 2e에 도시된 바와 같이, 실리콘질화막(13)이 노출될 때까지 1차 산화막(14)을 에치백(etch back)공정으로 식각하여 트렌치 내벽의 계단형상에서 구석부분에만 1차 산화막을 남기고, 결과적으로 1차 산화막(14)의 표면이 트렌치의 측벽의 평균기울기를 가지도록 한다. Next, as shown in FIG. 2E, the primary oxide layer 14 is etched by an etch back process until the silicon nitride layer 13 is exposed, thereby forming the primary oxide layer only at the corners in the stepped shape of the trench inner wall. As a result, the surface of the primary oxide film 14 has a mean slope of the sidewalls of the trench.
이어서, 실리콘질화막(13) 및 1차 산화막(14)을 포함하여 반도체 기판의 상부전면에 트렌치를 충분히 충진시키도록 2차 산화막(15)을 두껍게 증착한다.Subsequently, the secondary oxide film 15 is thickly deposited to sufficiently fill the trench in the upper front surface of the semiconductor substrate including the silicon nitride film 13 and the primary oxide film 14.
이후에는 실리콘질화막(13)이 노출될 때까지 2차 산화막(15)을 화학기계적 연마하여 평탄화시킴으로써, 트렌치 격리공정을 완료한다.Thereafter, the trench isolation process is completed by chemical mechanical polishing and planarization of the secondary oxide film 15 until the silicon nitride film 13 is exposed.
상술한 설명에서, 도 2d에서 수행하였던 2차 풀백 습식식각 공정을 수행하지 않아 트렌치의 풀백 습식식각 공정을 1회만 수행할 수도 있으며, 또는 2차 풀백 습식식각 공정 이후에 한번 더 풀백 습식식각 공정을 수행할 수도 있다. 이와 같이 풀백 습식식각 공정의 횟수에 따라 트렌치 내벽의 경사도를 조절할 수 있다. In the above description, the second full back wet etching process performed in FIG. 2D may not be performed, and the full back wet etching process of the trench may be performed only once, or the full back wet etching process may be performed once more after the second full back wet etching process. It can also be done. As such, the inclination of the inner wall of the trench may be adjusted according to the number of pullback wet etching processes.
상술한 바와 같이, 본 발명에서는 트렌치 형성을 위한 식각 시, 실리콘 질화막의 풀백 습식식각 공정을 이용하여 트렌치의 내벽이 계단형상을 가지도록 다단계 식각하기 때문에, 결과적으로 트렌치 내벽의 경사도가 완만하여 트렌치 산화막을 보이드 없이 형성하는 효과가 있다.As described above, in the present invention, since the inner wall of the trench is multi-step etched by using the pullback wet etching process of the silicon nitride film during the etching for forming the trench, the slope of the trench inner wall is smooth and consequently the trench oxide film is smooth. Has the effect of forming without voids.
따라서, 게이트 산화막 내에서의 보이드 형성으로 인한 누설전류에 기인한 소자의 신뢰성 감소 요인의 발생을 방지하고, 소자의 수율이 향상되는 효과가 있다.Therefore, there is an effect of preventing the occurrence of a factor of decreasing the reliability of the device due to leakage current due to void formation in the gate oxide film, and improving the yield of the device.
도 1a 내지 도 1b는 종래 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1B are cross-sectional views illustrating a conventional semiconductor device manufacturing method.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
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| JPS6151937A (en) * | 1984-08-22 | 1986-03-14 | Toshiba Corp | Manufacture of semiconductor device |
| JPH05234157A (en) * | 1992-02-18 | 1993-09-10 | Fujitsu Ltd | Electron beam recording and reproducing device |
| JP2000124302A (en) * | 1998-10-15 | 2000-04-28 | Nec Corp | Semiconductor device and its manufacture |
| KR100278883B1 (en) * | 1999-01-25 | 2001-01-15 | 황인길 | Shallow trench manufacturing method for isolating semiconductor devices |
| KR20020083617A (en) * | 2001-04-27 | 2002-11-04 | 삼성전자 주식회사 | Shallow Trench Isolation Method and Method for Fabricating semiconductor device using the same |
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2002
- 2002-12-05 KR KR10-2002-0076817A patent/KR100478488B1/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60164335A (en) * | 1984-02-06 | 1985-08-27 | Nec Corp | Manufacture of semiconductor device |
| JPS6151937A (en) * | 1984-08-22 | 1986-03-14 | Toshiba Corp | Manufacture of semiconductor device |
| JPH05234157A (en) * | 1992-02-18 | 1993-09-10 | Fujitsu Ltd | Electron beam recording and reproducing device |
| JP2000124302A (en) * | 1998-10-15 | 2000-04-28 | Nec Corp | Semiconductor device and its manufacture |
| KR100278883B1 (en) * | 1999-01-25 | 2001-01-15 | 황인길 | Shallow trench manufacturing method for isolating semiconductor devices |
| KR20020083617A (en) * | 2001-04-27 | 2002-11-04 | 삼성전자 주식회사 | Shallow Trench Isolation Method and Method for Fabricating semiconductor device using the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170015859A (en) * | 2017-01-26 | 2017-02-09 | 매그나칩 반도체 유한회사 | Semiconductor and method for fabricating the same |
| KR101867755B1 (en) * | 2017-01-26 | 2018-06-15 | 매그나칩 반도체 유한회사 | Semiconductor and method for fabricating the same |
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|---|---|
| KR20040049414A (en) | 2004-06-12 |
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