CN207320089U - Isolated groove film filled structure and semiconductor storage unit - Google Patents
Isolated groove film filled structure and semiconductor storage unit Download PDFInfo
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- CN207320089U CN207320089U CN201721350701.3U CN201721350701U CN207320089U CN 207320089 U CN207320089 U CN 207320089U CN 201721350701 U CN201721350701 U CN 201721350701U CN 207320089 U CN207320089 U CN 207320089U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000003860 storage Methods 0.000 title claims abstract description 23
- 230000002093 peripheral effect Effects 0.000 claims abstract description 129
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000011049 filling Methods 0.000 claims abstract description 41
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Abstract
The utility model provides a kind of isolated groove film filled structure and semiconductor storage unit, wherein, isolated groove film filled structure includes at least：Semi-conductive substrate, which, which prepares, peripheral groove；Prefabricated filled layer, covers side wall and the bottom of peripheral groove；And high density plasma oxide layer, the high density plasma oxide layer are covered on the prefabricated filled layer in peripheral groove and fill full peripheral groove；Wherein, the prefabricated filling layer thickness positioned at peripheral groove step corner is less than or equal to the prefabricated filling layer thickness positioned at peripheral groove side-walls.The utility model makes the prefabricated filling layer thickness positioned at isolated groove step corner be less than or equal to the prefabricated filling layer thickness positioned at isolated groove side-walls, so that avoid producing cavity between high density plasma oxide layer and prefabricated encapsulant layer, and then there is short circuit and causes component failure in the metal bit line for avoiding being subsequently formed.
Description
Technical field
Technical field of semiconductors is the utility model is related to, is led more particularly to a kind of isolated groove film filled structure and partly
Body memory part.
Background technology
Graphic making can generate the topology with three Spatial Dimensions in silicon chip surface, and which forms silicon chip table
The gap in face and step.One small―gap suture (such as isolated groove or through hole) can be described with depth-to-width ratio, between depth-to-width ratio is defined as
The ratio of the depth and width of gap.In the making of device, filling the ability in the gap of very little on silicon chip surface becomes most important
Film characteristics.For the gap of very little, no matter its depth-to-width ratio is high/low, makes it difficult to deposit and form film in uniform thickness,
And pinch off and cavity can be produced.Continuous with high density integrated circuit characteristic size reduces, between high/low depth-to-width ratio
The filling depositing technics that gap can carry out uniformly, without cavity seems most important.
Chemical vapor deposition (Chemical Vapor Deposition, CVD) is existed by the chemical reaction of gas mixing
The technique that silicon chip surface deposits one layer of solid film.Common chemical vapor deposition includes Films Prepared by APCVD
(Atmospheric Pressure CVD, APCVD), low-pressure chemical vapor phase deposition (Low Pressure CVD, LPCVD) and
Plasma-enhanced CVD deposits.One latest development of plasma-enhanced CVD deposit is high-density plasma
Body chemical vapor deposition (High Density Plasma CVD, HDPCVD), its using plasma is under low pressure with high density
The form of mixed gas directly contacts the surface of silicon chip in reaction chamber.Its major advantage is can be in 300 DEG C~400 DEG C friendships
Under the deposition temperature at bottom, the film that can fill high-aspect-ratio gap is prepared.
High-density plasma chemical vapor deposition technique has synchronous deposit and corrasion, it is filled out with dielectric material
Fill the gap of high-aspect-ratio and the basis formed without cavity.Synchronous deposit and etching mainly include following three-step mechanism：1st, from
Son induction deposit：Ion induction film initial product deposits to form gap filling；2nd, sputter etching：Between argon ion sputtering etches away
The unnecessary film in gap inlet, forms ramp profile on film；3rd, deposit again：The material being etched is deposited again.Repeating should
Process, until upper and lower consistent appearance.United States Patent (USP) US6908862B2 is exactly to deposit film in this way.Specifically,
It which disclose a kind of method of the deposited film on the substrate being arranged in substrate reaction chamber, this method is included by from inflow
First gaseous mixture of reaction chamber forms high-density plasma to deposit the Part I of film；Then stop depositing
Journey, and etch the Part I of the deposit film by making halogen etch agent flow into reaction chamber；Next, by making passivating gas
Body flows into reaction chamber to be passivated the surface of etching-film, then by forming high density from the second gaseous mixture for flowing into reaction chamber
Plasma, by the Part II deposit of film over the first portion；In one embodiment, passivation gas is by without inertia
The oxygen source composition of gas.
However, when above-mentioned patent is primarily directed to high-aspect-ratio gap filling film, since depth-to-width ratio is excessive, film forms sediment
Cavity generation problem in gap center position caused by product is difficult.By the way that the unnecessary film of gap inlet is etched into ramp profile
(or funnel shaped), so that the follow-up material deposited again can be filled into gap, so as to avoid gap center position
Produce cavity.Although the patent can effectively solve the problem that the filling cavity problem in high-aspect-ratio gap, for low (or medium
) empty problem that depth-to-width ratio gap produces in film filling process, it can not but solve well.
In the prior art, isolated groove film filled structure includes the side wall of covering isolated groove and the prefabricated of bottom is filled out
Fill layer 301, and the prefabricated filled layer 301 of covering and the high density plasma oxide layer 402 for filling full isolated groove.Such as figure
Shown in 1, in normal filling, cavity should not occur between prefabricated filled layer 301 and high density plasma oxide layer 402
401, thus the metal bit line 501 being subsequently formed should be able to work normally, phenomena such as being less prone to short circuit and cause device
(Device) fail.However, please continue to refer to Fig. 1, due to the limitation of existing process, prefabricated filled layer 301 and high density etc. from
Cavity 401 often occurs between daughter oxide skin(coating) 402, thus during metal bit line 501 is subsequently formed, cavity
It will be filled with metal in 401, cause metal bit line 501 easily short circuit phenomenon occur and cause component failure.
Therefore, how to avoid the isolated groove of high/low depth-to-width ratio from producing cavity in film filling process, cause follow-up shape
Into metal bit line easily occur short circuit and cause component failure, be a problem to be solved.
The content of the invention
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of isolated groove film to fill out
Structure and semiconductor storage unit are filled, for solving the isolated groove of high/low depth-to-width ratio in the prior art in film filling process
In be also easy to produce cavity, the metal bit line for causing to be subsequently formed easily there is short circuit and the problem of cause component failure.
In order to achieve the above objects and other related objects, the utility model provides a kind of isolated groove film filled structure,
Wherein, the isolated groove film filled structure includes at least：
Semi-conductive substrate, a upper surface of the Semiconductor substrate include device region and around the periphery of the device region
Area, prepare in the Semiconductor substrate have multiple array trench in the device region and one the peripheral region peripheral ditch
Groove, the width of the peripheral groove are more than more than twice of the cell width of the array trench；
Prefabricated filled layer, covers side wall and the bottom of the peripheral groove, and the prefabricated packing material more fills up the battle array
Row groove, to define multiple active areas；And
High density plasma oxide layer, the high density plasma oxide layer are covered in the peripheral groove
The prefabricated filled layer on and fill the full peripheral groove；
Wherein, the prefabricated filling layer thickness positioned at the peripheral groove step corner is less than or equal to positioned at the peripheral ditch
Prefabricated filling layer thickness at groove sidewall, thus avoid the high density plasma oxide layer and the prefabricated filled layer it
Between the metal bit line short circuit that there is cavity and cause to be subsequently formed.
Preferably, the peripheral groove film filled structure further includes passivation layer, and formation is covered in the Semiconductor substrate
Upper surface, and cover the step of the peripheral groove positioned at the prefabricated filling layer thickness of the peripheral groove step corner
Turning.
The prefabricated filled layer for being preferably located at the peripheral groove step corner is connected to the lateral margin of the passivation layer.
Preferably, the depth-to-width ratio of the peripheral groove is 0.5:1~21:20, the depth-to-width ratio of the array trench is 10:1
~20:1.
Preferably, the step turning of the peripheral groove is formed with a corner cut.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor storage unit, wherein, institute
Semiconductor storage unit is stated to include at least：
One substrate；
Multiple peripheral grooves, are formed in the Semiconductor substrate and around positioned at the multiple active of the Semiconductor substrate
Area；
Prefabricated filled layer, covers side wall and the bottom of the peripheral groove；And
High density plasma oxide layer, covers the prefabricated filled layer and fills the full peripheral groove；
Wherein, the high density plasma oxide layer and the prefabricated filled layer fill the peripheral groove jointly,
And one is provided jointly equal to the peripheral groove depth without empty film depth of cracking closure.
Preferably, the prefabricated filled layer is located at the thickness of the peripheral groove step corner less than or equal to positioned at described
Peripheral groove side wall is close to the thickness at bottom, for directly being formed without empty film depth of cracking closure.
Preferably, the depth-to-width ratio of the peripheral groove is 0.5:1~21:20.
Preferably, the semiconductor storage unit further includes multiple metal bit lines, is arranged in the Semiconductor substrate, institute
The end for stating metal bit line is extended on the high density plasma oxide layer in the peripheral groove.
As described above, the isolated groove film filled structure and semiconductor storage unit of the utility model, have with following
Beneficial effect：
The isolated groove film filled structure of the utility model, positioned at the prefabricated filling thickness of isolated groove step corner
Degree is less than or equal to the prefabricated filling layer thickness positioned at isolated groove side-walls so that high density plasma oxide layer with it is pre-
Avoid producing cavity between encapsulant layer processed, and then the metal bit line for avoiding being subsequently formed short circuit occurs and causes device to lose
Effect.In addition, present embodiment is suitable for high/low depth-to-width ratio isolated groove, the isolating trenches of especially low or medium depth-to-width ratio
Groove.In addition, the utility model etches prefabricated packing material using high density plasma etch technique, while etched by controlling
Pressure and etching depth, to ensure the intact of isolated groove step turning, so as to avoid isolated groove step turning from being cut cause
Make circuit breaker and ultimately cause component failure.In addition, the utility model can also be in the prefabricated of peripheral groove step corner
A corner cut is formed on filled layer, can further expand hatch bore diameter of the prefabricated filled layer in the openend of peripheral groove, be easy to
Follow-up high density plasma oxide layer fills to be formed, and further reduces the generation in cavity, improves the yield of device.
The semiconductor storage unit of the utility model, using the isolated groove film filled structure of above-mentioned the utility model,
Have well between high density plasma oxide material and prefabricated packing material in isolated groove film filled structure
Bonding effect, can provide jointly one be equal to isolation trench without empty film depth of cracking closure, thus the gold being subsequently formed
Belong to bit line and be less prone to short circuit problem, greatly reduce the possibility of component failure, improve yield of devices；Meanwhile isolated groove
Step turning is intact, thus circuit is less prone to breaking problem, further increases yield of devices.
Brief description of the drawings
Fig. 1 is shown as isolated groove film filled structure of the prior art and cavity and structure during normal filling is occurring
Contrast schematic diagram.
Fig. 2~Fig. 5 is shown as specific steps in the preparation method of isolated groove film filled structure of the prior art
Structure diagram.
Fig. 6 is shown as the flow of the preparation method of the isolated groove film filled structure of the utility model first embodiment
Schematic diagram.
Fig. 7~Figure 11 is shown as the preparation method of the isolated groove film filled structure of the utility model first embodiment
The structure diagram of middle specific steps, wherein, Figure 11 is also illustrated as isolated groove made of the utility model first embodiment
The schematic diagram of film filled structure.
Figure 12 is shown as the preparation method interval of the isolated groove film filled structure of the utility model first embodiment
From groove step corner prefabricated packing material be removed after the obtained schematic diagram of isolated groove film filled structure.
Figure 13~Figure 17 is shown as the preparation side of the isolated groove film filled structure of the utility model first embodiment
Form the structure diagram of the specific steps of isolated groove film filled structure in method at the same time in peripheral groove and array trench,
Wherein, Figure 17 is also illustrated as the schematic diagram of isolated groove film filled structure made of the utility model first embodiment.
Component label instructions
100 Semiconductor substrates
101 peripheral grooves
102 array trench
201 passivation layers
300 prefabricated packing materials
301 prefabricated filled layers
302 necking necks
400 high density plasma oxide materials
401 cavities
402 high density plasma oxide layers
501 metal bit lines
S1~S5 steps
Embodiment
Illustrate the embodiment of the utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
In the introduction, why found for 401 problem of cavity occurred in Fig. 1, inventor by further investigation
Cavity 401 often occurs between prefabricated filled layer 301 and high density plasma oxide layer 402, is due in semiconductor
Formed on substrate 100 after prefabricated packing material, as shown in Figures 2 and 3, the prefabricated filling material at isolated groove step turning A
Material protrudes, i.e., the prefabricated packing material thickness at the A of isolated groove step turning is more than the prefabricated filling material of isolated groove side-walls
The thickness of material, so as to cause when forming high density plasma oxide material, as shown in figure 4, high-density plasma oxygen
The linkage of compound material 400 and prefabricated packing material 300 and bad, so that easily in high density plasma oxide material
400 produce cavity 401 with the contact position of prefabricated packing material 300, and then obtain isolated groove film filling as shown in Figure 5
Structure, it is not difficult to find that 402 side wall of high density plasma oxide layer and isolated groove step corner in Fig. 5 is prefabricated
Position between filled layer 301 has cavity 401, thus during metal bit line is subsequently formed, will be filled with cavity 401
Metal, causes metal bit line easily short circuit phenomenon occur and causes component failure.
Fig. 6~Figure 17 is referred to, the first embodiment of the utility model is related to a kind of isolated groove film filled structure
Preparation method.It should be noted that the diagram provided in present embodiment only illustrates the utility model in a schematic way
Basic conception, then in schema only the display component related with the utility model rather than component count during according to actual implementation,
Shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its component
Being laid out kenel may also be increasingly complex.
As shown in Fig. 6~Figure 17, the preparation method of the isolated groove film filled structure of present embodiment includes at least such as
Lower step：
Step S1, there is provided semi-conductive substrate 100, a upper surface of Semiconductor substrate 100 include device region and around device
The peripheral region in part area, preparing in Semiconductor substrate 100 has multiple array trench 102 and one in device region in the periphery of peripheral region
Groove 101, the width of peripheral groove 101 are more than more than twice of the cell width of array trench 102.
Step S2, in forming prefabricated packing material 300 on the upper surface of Semiconductor substrate 100, prefabricated packing material 300 is more
Cover the upper surface of Semiconductor substrate 100 and side wall and the bottom of peripheral groove 101, prefabricated packing material 300 more fill up array
Groove 102, to define multiple active areas, prefabricated packing material 300 is at the openend of peripheral groove 101 formed with a necking
Neck 302, the hatch bore diameter of necking neck 302 are less than median pore radius of the prefabricated packing material 300 in 101 centre position of peripheral groove.
Step S3, the prefabricated packing material 300 of pre-etching, to remove the necking neck 302 of prefabricated packing material 300.
Step S4 is highly dense in formation high density plasma oxide material 400 on the upper surface of Semiconductor substrate 100
Degree plasma oxide material 400 more covers prefabricated packing material 300, and full peripheral groove is filled in the form of without cavity
101。
Step S5, removes 400 He of high density plasma oxide material of peripheral groove 101 in Semiconductor substrate 100
Prefabricated packing material 300, to obtain the high density plasma oxide layer 402 in peripheral groove 101 and prefabricated filling
Layer 301.
It should be noted that prefabricated packing material 300 can improve its own form by pre-etching, so that positioned at outer
Enclose the prefabricated filling that the prefabricated packing material thickness at 101 step turning A of groove is less than or equal to be located at 101 side-walls of peripheral groove
Material thickness, so as to avoid when forming high density plasma oxide material 400, high density plasma oxide material
Cavity is formed between 400 and prefabricated packing material 300 and causes the metal bit line short circuit being subsequently formed.
In addition, before prefabricated packing material 300 is formed, the preparation of the isolated groove film filled structure of present embodiment
Method further includes：
In forming passivation layer 201 in Semiconductor substrate 100, passivation layer 201 covers the upper surface of Semiconductor substrate 100.
As an example, Fig. 7~Figure 11, the isolated groove film filling of detailed description below present embodiment are referred to
Each step of isolated groove film filled structure is formed in the preparation method of structure in peripheral groove 101：
First, step S1 is performed, there is provided semi-conductive substrate 100, peripheral groove 101 is as shown in fig. 7, Semiconductor substrate
100 upper surface, which includes device region and prepared on the peripheral region of device region, Semiconductor substrate 100, has one in peripheral region
Peripheral groove 101.
In the present embodiment, Semiconductor substrate 100 includes but not limited to silicon substrate.
Then, before step S2 is performed, the preparation method of the isolated groove film filled structure of present embodiment is also wrapped
Include：In forming passivation layer 201 in Semiconductor substrate 100, passivation layer 201 covers the upper surface of Semiconductor substrate 100, such as Fig. 7 institutes
Show.
In the present embodiment, passivation layer 201 uses nitride.
As a preferred solution, passivation layer 201 uses SiN.
Then, step S2 is performed, in forming prefabricated packing material 300, prefabricated packing material 300 in Semiconductor substrate 100
The upper surface of passivation layer 201 and side wall and the bottom of peripheral groove 101 are covered, prefabricated packing material 300 is in peripheral groove 101
It is less than prefabricated packing material 300 in peripheral groove 101 formed with a necking neck 302, the hatch bore diameter of necking neck 302 at openend
The median pore radius in centre position, as shown in Figure 8.
In the present embodiment, prefabricated packing material 300 can use high density plasma deposition process, plasma
Enhancing depositing technics, normal pressure/low-pressure chemical vapor phase deposition technique, spin-on deposition technique or surface oxidation technique are formed.Certainly,
The forming method of prefabricated packing material 300 is not limited to this, and can be designed and be adjusted according to actual needs.
It is noted that prefabricated packing material 300 can also protect Semiconductor substrate 100, avoid subsequently performing etching
Semiconductor substrate 100 is caused to damage during with depositing step.
Then, step S3, the prefabricated packing material 300 of pre-etching, to remove the necking neck of prefabricated packing material 300 are performed
302, as shown in Figure 9.
Wherein, prefabricated packing material 300 improves its own form by pre-etching, so as to be located at peripheral groove 101
Prefabricated packing material thickness at the A of rank turning is less than or equal to the prefabricated packing material thickness positioned at 101 side-walls of peripheral groove, i.e.,
Prefabricated packing material 300 can remove necking neck 302 by pre-etching, as shown in figure 9, so as to avoid forming high density etc.
Formed during gas ions oxide material 400, between high density plasma oxide material 400 and prefabricated packing material 300 empty
The metal bit line short circuit that hole and causing is subsequently formed.Since the shape of prefabricated packing material 300 is improved by pre-etching, make
Prefabricated packing material thickness positioned at 101 step corner of peripheral groove is less than or equal to positioned at the pre- of 101 side-walls of peripheral groove
Packing material thickness processed, necking neck 302 are removed, so that high density plasma oxide material 400 is filled out with prefabricated
The key that fills between material 300 and become good, be not easy to form cavity, thus also avoid the metal bit line short circuit being subsequently formed
The problem of.
Then, step S4 is performed, in formation high density plasma oxide material on the upper surface of Semiconductor substrate 100
400, high density plasma oxide material 400 more covers prefabricated packing material 300, and is filled completely in the form of without cavity
Peripheral groove 101, as shown in Figure 10.
In the present embodiment, when forming high density plasma oxide material 400, the high-density plasma of use
Bulk concentration scope is more than or equal to 10E10e/cm3。
Finally, step S5 is performed, removes the high density plasma oxide in 101 Semiconductor substrate 100 of peripheral groove
Material 400 and prefabricated packing material 300, to obtain 402 He of high density plasma oxide layer in peripheral groove 101
Prefabricated filled layer 301, as shown in figure 11, so as to obtain the isolated groove film filled structure without cavity.
Wherein, as shown in figure 11, high density plasma oxide layer 402 is being formed and the step of prefabricated filled layer 301
In, including：
High density plasma oxide material 400 and prefabricated packing material 300 are sequentially etched, until exposure passivation layer
201 upper surface, so as to remove the high density plasma oxide material 400 outside peripheral groove 101 and prefabricated packing material
300, the full peripheral groove 101 of residual fraction filling of high density plasma oxide material 400 and prefabricated packing material 300,
To obtain high density plasma oxide layer 402 and prefabricated filled layer 301, and then form the isolated groove film without cavity and fill out
Fill structure.
Isolated groove film filled structure as shown in figure 11 is finally made by above-mentioned steps.
In addition, in the present embodiment, in the step of pre-etching prefabricated packing material 300, in the platform of peripheral groove 101
The prefabricated filled layer of rank corner is also removed, so that the step turning of peripheral groove 101 forms a corner cut, is obtained such as Figure 12
Shown structure, be at the B in Figure 12 101 step corner of peripheral groove prefabricated filled layer 301 be removed after by highly dense
Degree plasma oxide layer 402 mends the structure after filling out.It is understood that the appearance of corner cut can further expand prefabricated fill out
Hatch bore diameter of the layer 301 in the openend of peripheral groove 101 is filled, so as to avoid the formation of the necking neck 302 in too small aperture.
In addition, in the present embodiment, in the step of pre-etching prefabricated packing material 300, including：Using high density etc.
Plasma etching technique etches prefabricated packing material 300, while it is 10mtorr~40mtorr to keep etching pressure.Need to explain
If etching pressure is more than 50mtorr or less than 10mtorr, will be easy to cut to 101 step corner of peripheral groove
Prefabricated packing material 300 and form corner cut.Preferably, it is 20mtorr~30mtorr to keep etching pressure.More preferably, keep
Etching pressure is 25mtorr.In addition, when etching prefabricated packing material 300 using high density plasma etch technique, preferably make
Use NF3Plasma.
Further, when etching prefabricated packing material 300, the etching depth of high density plasma etch technique is controlled
The step turning of unlikely exposed peripheral groove 101.
In addition, in the present embodiment, there is the peripheral groove for being centered around peripheral region except preparing in Semiconductor substrate 100
101, multiple array trench 102 in device region are further prepared with, and the width of peripheral groove 101 is more than the list of array trench 102
More than twice of first width, as shown in figure 13.
As another example, 3~Figure 17, the isolated groove film of detailed description below present embodiment are please referred to Fig.1
The each of isolated groove film filled structure is formed in the preparation method of interstitital texture in peripheral groove 101 and array trench 102
Step：
First, step S1 is performed, there is provided semi-conductive substrate 100, peripheral groove 101 is as shown in fig. 7, Semiconductor substrate
100 upper surface include device region and on the peripheral region of device region, Semiconductor substrate 100 prepare have it is multiple in device region
Array trench 102 and one in the peripheral groove 101 of peripheral region, the width of peripheral groove 101 is more than the unit of array trench 102
More than twice of width, as shown in figure 13.
It should be noted that peripheral groove 1011 be typically be used for isolate component have relatively low depth-to-width ratio between
Gap, and array trench 1012 is then the gap with high depth-to-width ratio being arranged in array.Wherein, 1011 depth-to-width ratio of peripheral groove
For 0.5:1~21:20, the depth-to-width ratio of array trench 1012 is 10:1~20:1.
Then, before step S2 is performed, the preparation method of the isolated groove film filled structure of present embodiment is also wrapped
Include：In forming passivation layer 201 in Semiconductor substrate 100, passivation layer 201 covers the upper surface of Semiconductor substrate 100, such as Figure 13 institutes
Show.
Then, step S2 is performed, in forming prefabricated packing material 300, prefabricated packing material 300 in Semiconductor substrate 100
Cover the upper surface of passivation layer 201 and side wall and the bottom of peripheral groove 101, prefabricated packing material 300 more fill up array trench
102, to define multiple active areas, prefabricated packing material 300 is at the openend of peripheral groove 101 formed with a necking neck
302, the hatch bore diameter of necking neck 302 is less than median pore radius of the prefabricated packing material 300 in 101 centre position of peripheral groove, such as
Shown in Figure 14.
Then, step S3, the prefabricated packing material 300 of pre-etching, to remove the necking neck of prefabricated packing material 300 are performed
302, as shown in figure 15.
Then, step S4 is performed, in formation high density plasma oxide material on the upper surface of Semiconductor substrate 100
400, high density plasma oxide material 400 more covers prefabricated packing material 300, and is filled completely in the form of without cavity
Peripheral groove 101, as shown in figure 16.
Finally, step S5 is performed, removes high density plasma oxide material 400 in Semiconductor substrate 100 and pre-
Packing material 300 processed, to obtain the high density plasma oxide layer 402 in peripheral groove 101 and prefabricated filled layer
301, as shown in figure 17, so as to obtain the isolated groove film filled structure without cavity.
Isolated groove film filled structure as shown in figure 17 is finally made by above-mentioned steps.
It is not difficult to find that when forming prefabricated packing material 300, prefabricated packing material 300 can directly fill up array trench
102, to define multiple active areas, as shown in figure 14.Therefore, no matter high and low the isolated groove of present embodiment depth-to-width ratio be suitable
With film filling effect is good, substantially without cavity.
The preparation method of the isolated groove film filled structure of present embodiment, is forming high density plasma oxide
Before material, improve the shape of prefabricated packing material by pre-etching, make prefabricated the filling out positioned at isolated groove step corner
The prefabricated packing material thickness that material thickness is less than or equal to be located at isolated groove side-walls is filled, so that high-density plasma oxygen
The linkage of compound material and prefabricated packing material and well, is not easy to form cavity, and then the metal bit line for avoiding being subsequently formed goes out
Show short circuit and cause component failure.In addition, present embodiment is suitable for high/low depth-to-width ratio isolated groove, it is especially low or in
Deng depth-to-width ratio isolated groove.In addition, present embodiment etches prefabricated filling material using high density plasma etch technique
Material, while by controlling etching pressure and etching depth, to ensure the intact of isolated groove step turning, so as to avoid isolating trenches
Groove step turning, which is cut, to be caused circuit breaker and ultimately causes component failure.
The step of various methods divide above, be intended merely to describe it is clear, can be merged into when realizing a step or
Some steps are split, are decomposed into multiple steps, as long as including identical logical relation, all protection domain in this patent
It is interior；To either adding inessential modification in algorithm in flow or introducing inessential design, but its algorithm is not changed
Core design with flow is all in the protection domain of the patent.
The second embodiment of the utility model is related to a kind of preparation method of semiconductor storage unit, it is included at least：
Isolating trenches are prepared using the preparation method of the isolated groove film filled structure as involved by the utility model first embodiment
Groove film filled structure.
Implement it is not difficult to find that present embodiment needs first embodiment to coordinate, therefore mentioned in first embodiment
Relevant technical details are still effective in the present embodiment, and in order to reduce repetition, which is not described herein again.Correspondingly, this embodiment party
The relevant technical details mentioned in formula are also applicable in first embodiment.
The preparation method of the semiconductor storage unit of present embodiment, by using the utility model first embodiment institute
The preparation method for the isolated groove film filled structure being related to prepares isolated groove film filled structure, the filling of isolated groove film
There is good bonding effect between high density plasma oxide material and prefabricated packing material in structure, can be common
One is provided equal to isolation trench without empty film depth of cracking closure, thus the metal bit line being subsequently formed is less prone to short circuit
Problem, greatly reduces the possibility of component failure, improves yield of devices；Meanwhile prefabricated the filling out of isolated groove step corner
It is intact to fill material, thus circuit is less prone to breaking problem, further increases yield of devices.
3rd embodiment of the utility model is related to a kind of isolated groove film filled structure, such as Figure 11 and Figure 17 institutes
Show, it is included at least：
Semi-conductive substrate 100, a upper surface of the Semiconductor substrate 100 include device region and around the periphery of device region
Area, preparing in the Semiconductor substrate 100 has peripheral groove 101 of multiple array trench 102 and one in device region in peripheral region,
The width of peripheral groove 101 is more than more than twice of the cell width of array trench 102；
Prefabricated filled layer 301, the side wall and bottom, the prefabricated packing material for covering peripheral groove 101 more fill up array ditch
Groove 102, to define multiple active areas；And
High density plasma oxide layer 402, the high density plasma oxide layer 402 are covered in peripheral groove
On prefabricated filled layer 301 in 101 and peripheral groove 101 is expired in filling；
Wherein, the prefabricated filling layer thickness positioned at 101 step corner of peripheral groove is less than or equal to be located at peripheral groove 101
The prefabricated filling layer thickness of side-walls, so as to avoid depositing between high density plasma oxide layer 402 and prefabricated filled layer 301
The metal bit line short circuit being subsequently formed is caused in cavity.
In the present embodiment, outside the unlikely exposure of 301 thickness of prefabricated filled layer of 101 step corner of peripheral groove
Enclose the step turning of groove 101.
In addition, the isolated groove film filled structure of present embodiment further includes：
Passivation layer 201, forms the upper surface for being covered in Semiconductor substrate 100, and is located at 101 step turning of peripheral groove
The step turning of 301 thickness of the prefabricated filled layer covering peripheral groove 101 at place.
Also, the lateral margin of passivation layer 201 is connected to positioned at the prefabricated filled layer 301 of 101 step corner of peripheral groove.
In addition, in the present embodiment, the depth-to-width ratio of peripheral groove 101 is 0.5:1~21:20, the depth of array trench 102
Wide ratio is 10:1~20:1.
In addition, in the present embodiment, the step corner of peripheral groove 101 can also be formed with a corner cut, such as Figure 12
It is shown.It can also be appreciated that the appearance of corner cut can further expand prefabricated the opening in peripheral groove 101 of filled layer 301
The hatch bore diameter at mouth end, so as to avoid the formation of the necking neck 302 in too small aperture.
It is not difficult to find that present embodiment be with the corresponding product embodiment of first embodiment, present embodiment can
Work in coordination implementation with first embodiment.The relevant technical details mentioned in first embodiment are in the present embodiment still
Effectively, in order to reduce repetition, which is not described herein again.Correspondingly, the relevant technical details mentioned in present embodiment can also be applied
In the first embodiment.
The isolated groove film filled structure of present embodiment, positioned at the prefabricated filling thickness of isolated groove step corner
Degree is less than or equal to the prefabricated filling layer thickness positioned at isolated groove side-walls so that high density plasma oxide layer with it is pre-
Avoid producing cavity between encapsulant layer processed, and then the metal bit line for avoiding being subsequently formed short circuit occurs and causes device to lose
Effect.In addition, present embodiment is suitable for high/low depth-to-width ratio isolated groove, the isolating trenches of especially low or medium depth-to-width ratio
Groove.
4th embodiment of the utility model is related to a kind of semiconductor storage unit, it is included at least：As this practicality is new
Isolated groove film filled structure involved by the 3rd embodiment of type.
It is not difficult to find that the semiconductor storage unit involved by present embodiment uses the 3rd embodiment institute of the utility model
The isolated groove film filled structure being related to, therefore the relevant technical details mentioned in the 3rd embodiment are in the present embodiment
Still effectively, in order to reduce repetition, which is not described herein again.Correspondingly, the relevant technical details mentioned in present embodiment also may be used
Using in the third embodiment.
5th embodiment of the utility model is related to a kind of semiconductor storage unit, and as shown in figure 11, it is included at least：
Semi-conductive substrate 100；
Multiple peripheral grooves 101, are formed in Semiconductor substrate 100 and have around positioned at the multiple of Semiconductor substrate 100
Source region；
Prefabricated filled layer 301, covers side wall and the bottom of peripheral groove 101；And
High density plasma oxide layer 402, covers prefabricated filled layer 301 and fills full peripheral groove 101；
Wherein, high density plasma oxide layer 402 and prefabricated filled layer 301 fill peripheral groove 101 jointly, and
It is common to provide one equal to 101 depth of peripheral groove without empty film depth of cracking closure.
In addition, in the present embodiment, the thickness that prefabricated filled layer 301 is located at 101 step corner of peripheral groove is less than
Equal to positioned at 101 side wall of peripheral groove close to the thickness at bottom, for directly being formed without empty film depth of cracking closure.
In addition, in the present embodiment, the depth-to-width ratio of peripheral groove 101 is 0.5:1~21:20.
In addition, the semiconductor storage unit of present embodiment further includes multiple metal bit lines, Semiconductor substrate 100 is arranged at
On, the end of metal bit line is extended on the high density plasma oxide layer 402 in peripheral groove 101.
The semiconductor storage unit of present embodiment, can be between high density plasma oxide layer and prefabricated filled layer
Good bonding, can provide jointly one be equal to isolation trench without empty film depth of cracking closure, thus the gold being subsequently formed
Belong to bit line and be less prone to short circuit problem, greatly reduce the possibility of component failure, improve yield of devices；Meanwhile isolated groove
The prefabricated packing material of step corner is intact, thus circuit is less prone to breaking problem, further increases yield of devices.
In conclusion the isolated groove film filled structure and semiconductor storage unit of the utility model, have with following
Beneficial effect：
The isolated groove film filled structure of the utility model, positioned at the prefabricated filling thickness of isolated groove step corner
Degree is less than or equal to the prefabricated filling layer thickness positioned at isolated groove side-walls so that high density plasma oxide layer with it is pre-
Avoid producing cavity between encapsulant layer processed, and then the metal bit line for avoiding being subsequently formed short circuit occurs and causes device to lose
Effect.In addition, present embodiment is suitable for high/low depth-to-width ratio isolated groove, the isolating trenches of especially low or medium depth-to-width ratio
Groove.In addition, the utility model etches prefabricated packing material using high density plasma etch technique, while etched by controlling
Pressure and etching depth, to ensure the intact of isolated groove step turning, so as to avoid isolated groove step turning from being cut cause
Make circuit breaker and ultimately cause component failure.In addition, the utility model can also be in the prefabricated of peripheral groove step corner
A corner cut is formed on filled layer, can further expand hatch bore diameter of the prefabricated filled layer in the openend of peripheral groove, be easy to
Follow-up high density plasma oxide layer fills to be formed, and further reduces the generation in cavity, improves the yield of device.
The semiconductor storage unit of the utility model, using above-mentioned the utility model isolated groove film filled structure and
Its preparation method prepares isolated groove film filled structure, high-density plasma oxygen in isolated groove film filled structure
There is good bonding effect between compound material and prefabricated packing material, one can be provided jointly and be equal to isolation trench
Without empty film depth of cracking closure, thus the metal bit line being subsequently formed is less prone to short circuit problem, greatly reduces component failure
Possibility, improve yield of devices；Meanwhile the prefabricated packing material of isolated groove step corner is intact, thus circuit is not easy
There is breaking problem, further increase yield of devices.
So the utility model effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above embodiment is only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art all can under the spirit and scope without prejudice to the utility model, to the above embodiment into
Row modifications and changes.Therefore, such as those of ordinary skill in the art revealed without departing from the utility model
Spirit and all equivalent modifications completed under technological thought or change, should be covered by the claim of the utility model.
Claims (9)
1. a kind of isolated groove film filled structure, it is characterised in that the isolated groove film filled structure includes at least：
Semi-conductive substrate, a upper surface of the Semiconductor substrate include device region and around the peripheral regions of the device region,
In the Semiconductor substrate prepare have multiple array trench in the device region and one the peripheral region peripheral groove, institute
The width for stating peripheral groove is more than more than twice of cell width of the array trench；
Prefabricated filled layer, covers side wall and the bottom of the peripheral groove, and the prefabricated packing material more fills up the array ditch
Groove, to define multiple active areas；And
High density plasma oxide layer, the high density plasma oxide layer are covered in the institute in the peripheral groove
State on prefabricated filled layer and fill the full peripheral groove；
Wherein, the prefabricated filling layer thickness positioned at the peripheral groove step corner is less than or equal to be located at the peripheral groove side
Prefabricated filling layer thickness at wall, so as to avoid depositing between the high density plasma oxide layer and the prefabricated filled layer
The metal bit line short circuit being subsequently formed is caused in cavity.
2. isolated groove film filled structure according to claim 1, it is characterised in that the peripheral groove film filling
Structure further includes passivation layer, forms the upper surface for being covered in the Semiconductor substrate, and turn positioned at the peripheral groove step
Prefabricated filling layer thickness at angle covers the step turning of the peripheral groove.
3. isolated groove film filled structure according to claim 2, it is characterised in that positioned at the peripheral groove step
The prefabricated filled layer of corner is connected to the lateral margin of the passivation layer.
4. isolated groove film filled structure according to claim 1, it is characterised in that the depth-to-width ratio of the peripheral groove
For 0.5:1~21:20, the depth-to-width ratio of the array trench is 10:1~20:1.
5. isolated groove film filled structure according to any one of claims 1 to 4, it is characterised in that the periphery ditch
The step turning of groove is formed with a corner cut.
6. a kind of semiconductor storage unit, it is characterised in that the semiconductor storage unit includes at least：
One substrate；
Multiple peripheral grooves, are formed in the Semiconductor substrate and around multiple active areas positioned at the Semiconductor substrate；
Prefabricated filled layer, covers side wall and the bottom of the peripheral groove；And
High density plasma oxide layer, covers the prefabricated filled layer and fills the full peripheral groove；
Wherein, the high density plasma oxide layer and the prefabricated filled layer fill the peripheral groove jointly, and
It is common to provide one equal to the peripheral groove depth without empty film depth of cracking closure.
7. semiconductor storage unit according to claim 6, it is characterised in that the prefabricated filled layer is located at the periphery
The thickness of groove step corner is less than or equal to positioned at the peripheral groove side wall close to the thickness at bottom, for the no sky
Hole film depth of cracking closure is directly formed.
8. semiconductor storage unit according to claim 6, it is characterised in that the depth-to-width ratio of the peripheral groove is 0.5:
1~21:20.
9. according to claim 6 to 8 any one of them semiconductor storage unit, it is characterised in that the semiconductor memory
Part further includes multiple metal bit lines, is arranged in the Semiconductor substrate, and the end of the metal bit line is extended to described outer
Enclose on the high density plasma oxide layer in groove.
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| CN201721350701.3U CN207320089U (en) | 2017-10-19 | 2017-10-19 | Isolated groove film filled structure and semiconductor storage unit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107706145A (en) * | 2017-10-19 | 2018-02-16 | 睿力集成电路有限公司 | Isolated groove film filled structure, semiconductor storage unit and preparation method |
| CN108962894A (en) * | 2018-06-22 | 2018-12-07 | 长鑫存储技术有限公司 | A method of filling groove forms contact |
-
2017
- 2017-10-19 CN CN201721350701.3U patent/CN207320089U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107706145A (en) * | 2017-10-19 | 2018-02-16 | 睿力集成电路有限公司 | Isolated groove film filled structure, semiconductor storage unit and preparation method |
| CN107706145B (en) * | 2017-10-19 | 2024-03-26 | 长鑫存储技术有限公司 | Isolation trench film filling structure, semiconductor memory device and preparation method |
| CN108962894A (en) * | 2018-06-22 | 2018-12-07 | 长鑫存储技术有限公司 | A method of filling groove forms contact |
| CN108962894B (en) * | 2018-06-22 | 2024-01-16 | 长鑫存储技术有限公司 | Method for forming contact by filling groove |
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