CN110265353B - Trench isolation structure and forming method thereof - Google Patents

Trench isolation structure and forming method thereof Download PDF

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CN110265353B
CN110265353B CN201910572614.XA CN201910572614A CN110265353B CN 110265353 B CN110265353 B CN 110265353B CN 201910572614 A CN201910572614 A CN 201910572614A CN 110265353 B CN110265353 B CN 110265353B
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etching
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CN110265353A (en
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姚公达
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ICLeague Technology Co Ltd
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ICLeague Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

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Abstract

The invention provides a trench isolation structure and a forming method thereof, wherein the trench isolation structure comprises the following steps: providing a substrate; forming a groove in the substrate; forming a dielectric layer on the surface of the substrate and in the groove by adopting a high-density plasma deposition process, wherein the high-density plasma deposition process comprises the following steps: forming a first dielectric film on the surface of the substrate and the side wall and the bottom surface of the groove by adopting a one-time deposition etching process; forming a plurality of layers of overlapped second dielectric films on the surface of the first dielectric film by adopting a plurality of secondary deposition etching processes, and introducing nitrogen into at least one secondary deposition etching process; the forming method of the invention can form a trench isolation structure with good quality and improve the isolation effect of the trench isolation structure.

Description

Trench isolation structure and forming method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a trench isolation structure and a forming method thereof.
Background
As integrated circuit technology continues to mature, the number of active devices integrated per unit area of a semiconductor substrate increases (e.g., in the millions), and the devices are therefore placed more closely within the chip to accommodate the available space on the chip. In order to prevent the devices from affecting each other, an isolation technique is required to isolate the active devices from each other. As the density of active devices per unit area of a semiconductor substrate continues to increase, effective isolation between devices becomes more important.
Trench isolation is a common isolation technique. The trench isolation technology has good isolation effects (such as process isolation effect and electrical isolation effect), and also has the advantages of reducing the area occupied by the surface of the wafer, increasing the integration level of devices, and the like.
However, as the integration degree of semiconductor devices is continuously improved, how to form a trench isolation structure with good quality is a problem which needs to be solved urgently at present.
Disclosure of Invention
The invention provides a trench isolation structure and a forming method thereof, which can form a trench isolation structure with good quality and improve the isolation effect of the trench isolation structure.
To solve the above technical problem, the present invention provides a method for forming a trench isolation structure, including: providing a substrate; forming a groove in the substrate; forming a dielectric layer on the surface of the substrate and in the groove by adopting a high-density plasma deposition process, wherein the high-density plasma deposition process comprises the following steps: forming a first dielectric film on the surface of the substrate and the side wall and the bottom surface of the groove by adopting a one-time deposition etching process; and forming a plurality of layers of overlapped second dielectric films on the surface of the first dielectric film by adopting a plurality of secondary deposition etching processes, and introducing nitrogen into at least one secondary deposition etching process.
Optionally, the one-time deposition etching process includes: forming an initial first dielectric film on the surface of the substrate and the side wall and the bottom of the groove by adopting a first deposition process; after the first deposition process, an initial first dielectric film is etched using a first etch process.
Optionally, the parameters of the first deposition process include: the gas used comprises SiH4And oxygen, wherein the SiH4The flow rate of the gas is 20-60 sccm, the flow rate of the oxygen gas is 30-70 sccm, the pressure of the chamber is 3-7 mtorr, and the source power is 1000-5000W.
Optionally, the parameters of the first etching process include: the adopted gas comprises oxygen and argon, wherein the flow rate of the oxygen is 50 sccm-150 sccm, the flow rate of the argon gas is 300 sccm-700 sccm, the chamber pressure is 30 mtorr-70 mtorr, the source power is 300W-700W, and the bias voltage is-300V-700V.
Optionally, the secondary deposition etching process includes: forming an initial second dielectric film on the first dielectric film by adopting a secondary deposition process; and after the secondary deposition process, etching the initial second dielectric film by adopting a second etching process.
Optionally, the secondary deposition process includes a first deposition process and a second deposition process; the secondary etching process comprises a first etching process and a second etching process.
Optionally, the parameters of the second deposition process include: the gas used comprises SiH4And oxygen, wherein the SiH4The flow rate of the gas is 20 sccm-60 sccm, the flow rate of the oxygen gas is 30 sccm-70 sccm, the pressure of the chamber is 3 mtorr-7 mtorr, and the source power is 2000W-6000W.
Optionally, the parameters of the second etching process include: the adopted gas comprises oxygen and argon, wherein the flow rate of the oxygen is 50 sccm-150 sccm, the flow rate of the argon gas is 300 sccm-700 sccm, the chamber pressure is 30 mtorr-70 mtorr, the source power is 400W-800W, and the bias voltage is-400V-800V.
Optionally, the ratio of the deposition rate of the first deposition process to the etching rate of the first etching process is a first deposition etching ratio; the deposition rate of the second deposition process and the etching rate of the second etching process are a second deposition etching ratio, and the first deposition etching ratio is larger than the second deposition etching ratio.
Optionally, the second deposition etching ratio is in a range of 10% to 80%.
Optionally, the number of times of the secondary deposition etching process is N; and introducing nitrogen into at least one secondary deposition process in the secondary deposition and etching processes from 1 st to N-1 st, wherein N is a natural number more than or equal to 2.
Optionally, nitrogen is introduced into the nth secondary deposition process, and in the 1 st to the (N + 1) th secondary deposition and etching processes, the secondary deposition process is a first deposition process, the secondary etching process is a first etching process, and N is a natural number less than N.
Optionally, in the (N + 2) th to nth secondary deposition and etching processes, the secondary deposition process is a second deposition process, and the secondary etching process is a second etching process.
Optionally, the number of times of the second deposition etching process is 4 or 5.
Optionally, the depth-to-width ratio of the groove is 2: 1-6: 1.
Optionally, the method further includes: and flattening the plurality of layers of overlapped second dielectric films.
Optionally, the volume amount of the nitrogen gas is between 10 ml and 300 ml.
Optionally, the material of the first dielectric film includes silicon oxide.
Optionally, the material of the second dielectric film includes silicon oxide, silicon nitride, or silicon oxynitride.
Accordingly, a trench isolation structure formed by the above method comprises: a substrate; a trench in the substrate; the dielectric layer is positioned on the surface of the substrate and in the groove, and comprises: the first dielectric film is positioned on the surface of the substrate, the side wall and the bottom surface of the groove; and the second dielectric films are overlapped and positioned on the surface of the first dielectric film, and the second dielectric films contain nitrogen elements.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
and in the secondary deposition etching process, a plurality of layers of overlapped second dielectric films are formed on the surface of the first dielectric film, nitrogen is introduced into at least one secondary deposition etching process, and the introduced nitrogen is dissociated into high-density plasma and is further transmitted to the surface of the silicon wafer for chemical reaction to form nitride. The nitride dielectric layer can form a dielectric film with uniform thickness during deposition, and meanwhile, the dielectric layer containing the nitride has good covering capability and can be in close contact with dielectric films deposited on other layers, so that the probability of shrinkage cavities between adjacent dielectric films is reduced, the phenomenon of holes formed in the dielectric layer is reduced, and the isolation effect of the trench isolation structure is improved; meanwhile, since the nitride has higher density and electrical insulation, the nitride can isolate external pollution in a plurality of deposition processes, thereby ensuring that the formed dielectric layer is not polluted.
Furthermore, the number of times of the secondary deposition etching process is N, nitrogen is introduced into at least one of the secondary deposition etching processes from 1 st time to N-1 st time, after the first deposition etching process, a first dielectric film is formed on the surface of the substrate and the side wall and the bottom surface of the groove, the secondary deposition etching process is performed again to form a second dielectric film, and the nitrogen is introduced into the first secondary deposition etching process and is not introduced into the last secondary deposition etching process, so that the formed second dielectric film and the first dielectric film are in good transition, defects between interfaces of the first dielectric film and the second dielectric film are reduced, the problems of electric leakage and the like are reduced, and the isolation effect is improved.
Furthermore, the range of the second deposition etching ratio is 10% -80%, and the second deposition etching ratio can ensure that the opening of the groove is opened by the etching process before the deposition process, so that the acting force of the air pressure in the groove on the deposited dielectric film is small, and the dielectric film can be in close contact with the dielectric film, thereby reducing the phenomenon of holes in the dielectric layer, improving the isolation effect of the formed groove isolation structure and enhancing the performance.
Drawings
Fig. 1 to 2 are schematic structural views of steps of a trench isolation structure;
fig. 3 to 7 are schematic structural diagrams of steps of a trench isolation structure according to an embodiment of the present invention.
Detailed Description
With the development of integrated circuits, the number of active devices integrated on a unit area of a semiconductor substrate is increasing, in order to prevent the devices from affecting each other, a trench isolation structure needs to be adopted to isolate the active devices, so that the semiconductor device is ensured to have good performance in the use process, but the trench isolation structure formed at present has a defect of a hole, so that the trench isolation structure has a poor isolation effect, and the semiconductor device is limited in use due to the fact that the defects of electric leakage and the like easily occur in the use process, and the specific forming process refers to fig. 1 to fig. 2.
Referring to fig. 1, a substrate 1 is provided, and a trench 2 is formed in the substrate 1.
Referring to fig. 2, a dielectric layer 3 is formed on the surface of the substrate 1 and in the trench 2 using a high density plasma deposition process.
The defect that holes exist in a medium layer formed through a high-density plasma deposition process enables the isolation effect of a formed trench isolation structure to not meet actual requirements, because the depth-to-width ratio of a trench is in a range of 2: 1-3: 1, in the process of forming the medium layer, because an opening at the top of the trench is sealed prematurely, a small opening is reserved for the next formation of a medium film, at the moment, the acting force of air pressure in the trench on the medium film is enhanced, adjacent medium films cannot be tightly attached to each other, the holes exist in the medium layer, and the formed trench isolation structure has poor isolation performance.
In order to solve the above problems, embodiments of the present invention provide a trench isolation structure and a method for forming the same. The method comprises the following steps of introducing nitrogen into at least one second deposition etching process in the second deposition etching process, wherein the nitrogen is dissociated into ions to perform chemical reaction with the silicon surface to form silicon nitride, the dielectric film containing the silicon nitride has good thickness uniformity and good step coverage capability, and the second dielectric films of a plurality of laminations can be tightly attached to each other when the second dielectric films of the plurality of laminations are formed, so that the shrinkage phenomenon cannot occur among the second dielectric films of the plurality of laminations, the defect of holes cannot occur in the medium formed in the groove, and the isolation effect of the formed groove isolation structure is improved; in addition, because the silicon nitride has higher compactness, when the dielectric layer is formed in the groove, the silicon nitride can play a role in isolating external impurities, and the formed dielectric layer is ensured not to be polluted.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 7 are schematic structural diagrams of steps of a trench isolation structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate 100 is provided.
In this embodiment, the substrate 100 is made of silicon; in other embodiments, the material of the substrate 100 may also be a semiconductor material such as silicon germanium, gallium arsenide, germanium, or the like.
Referring to fig. 4, a trench 200 is formed in the substrate 100.
In this embodiment, a patterning layer (not shown) is formed on the substrate 100, the substrate 100 is etched by using the patterning layer as a mask, and the trench 200 is formed in the substrate 100.
In an embodiment, the patterned layer is a photoresist layer, the substrate 100 is etched by using the patterned layer as a mask, and the photoresist layer is removed after the trench 200 is formed in the substrate 100.
In an embodiment, the patterned layer includes a photoresist layer and silicon nitride, the substrate 100 is etched using the patterned layer as a mask, and the patterned layer is not removed after the trench 200 is formed in the substrate 100.
In one embodiment, the patterned layer comprises a photoresist layer and a silicon nitride layer, wherein a silicon oxide layer is further included between the silicon nitride layer and the substrate, and the presence of the silicon oxide layer facilitates good adhesion between the silicon nitride layer and the substrate layer.
In this embodiment, the patterning layer includes a photoresist layer and a silicon nitride layer, wherein a silicon oxide layer is further included between the silicon nitride layer and the substrate, the substrate 100 is etched by using the patterning layer as a mask, the patterning layer is not removed after the trench 200 is formed in the substrate 100, and a subsequently formed dielectric layer is located on the surface of the patterning layer.
In this embodiment, the process of forming the trench 200 includes a dry etching process, and the dry etching parameters include: the adopted etching gas comprises HBr and Ar, wherein the flow rate of HBr is 10 sccm-1000 sccm, and the flow rate of Ar is 10 sccm-1000 sccm.
In this embodiment, the depth-to-width ratio of the trench 200 is 2:1 to 6: 1; when the depth-to-width ratio is smaller than 2:1, the depth of the groove is small, and the formed groove isolation structure has poor isolation effect; when the aspect ratio is greater than 6:1, the depth of the formed trench is too deep, which is limited by the process, and a good-quality trench is not easily formed.
In this embodiment, a high-density plasma deposition process is subsequently used to form dielectric layers on the surface of the substrate and in the trench, where the high-density plasma deposition process includes: forming a first dielectric film on the surface of the substrate and the side wall and the bottom surface of the groove by adopting a one-time deposition etching process; and forming a plurality of layers of overlapped second dielectric films on the surface of the first dielectric film by adopting a plurality of secondary deposition etching processes, and introducing nitrogen into at least one secondary deposition etching process. Please refer to fig. 5 to 7.
Referring to fig. 5, a first dielectric film 300 is formed on the surface of the substrate 100 and the sidewall and bottom surfaces of the trench 200 by a single deposition etching process.
In this embodiment, the one-step deposition etching process includes: forming an initial first dielectric film on the surface of the substrate 100 and the sidewalls and bottom of the trench 200 using a first deposition process; after the first deposition process, an initial first dielectric film is etched using a first etch process.
In this embodiment, the material of the first dielectric film 300 includes silicon oxide.
In this embodiment, in one aspect of the purpose of forming the first dielectric film 300, the first dielectric film 300 may be used as a stop layer in a subsequent planarization process; on the other hand, due to the existence of the first dielectric film 300, the substrate 100 is better adhered to a second dielectric film formed later, and the first dielectric film 300 and the second dielectric film can be tightly adhered to each other, so that holes in the dielectric layers are reduced.
In this embodiment, the first deposition process is a high density plasma chemical deposition process (HDPCVD).
In this embodiment, the parameters of the first deposition process include: the gas used comprises SiH4And oxygen, wherein the SiH4The flow rate of the gas is 20-60 sccm, the flow rate of the oxygen gas is 30-70 sccm, the pressure of the chamber is 3-7 mtorr, and the source power is 1000-5000W.
In this embodiment, the first etching process is a dry etching process; the dry etching process parameters comprise: the adopted gas comprises oxygen and argon, wherein the flow rate of the oxygen is 50 sccm-150 sccm, the flow rate of the argon gas is 300 sccm-700 sccm, the chamber pressure is 30 mtorr-70 mtorr, the source power is 300W-700W, and the bias voltage is-300V-700V.
Referring to fig. 6, a first layer of a second dielectric film 401 is formed on a surface of the first dielectric film 300, and a second layer of a second dielectric film 402 is formed on a surface of the first layer of the second dielectric film 401.
In this embodiment, the secondary deposition etching process includes: forming an initial second dielectric film on the first dielectric film by adopting a secondary deposition process; after the secondary deposition process, the initial second dielectric film is etched by using a secondary etching process to form a first layer of second dielectric film 401.
In this embodiment, the material of the second dielectric film includes silicon oxide, silicon nitride, or silicon oxynitride.
In the embodiment, nitrogen is introduced in the process of the first secondary deposition etching process; in other embodiments, nitrogen gas may also be introduced during the second deposition etching process, the third deposition etching process, and the fourth deposition etching process, but nitrogen gas is not introduced during the last deposition etching process.
In the embodiment, nitrogen is introduced in the process of the first secondary deposition etching process, so that the process flow is shortened and the speed is increased.
In other embodiments, nitrogen is introduced into the second deposition etching process, the third deposition etching process, and other secondary deposition etching processes, so that the number of times of the secondary deposition etching process needs to be increased, which is not beneficial to improving the production efficiency.
In the embodiment, the volume of the once introduced nitrogen is between 10 ml and 300 ml; when the volume of the once introduced nitrogen is less than 10 milliliters, the volume of the introduced nitrogen is too small, so that enough nitrogen is not dissociated into ions to react with the silicon surface to form silicon nitride, and the problem of shrinkage cavity between the dielectric films cannot be solved; when the volume of the nitrogen introduced at one time is more than 300 ml, and the volume of the introduced nitrogen is too much, when a dielectric layer is formed in the groove of the next substrate, the first dielectric film and the second dielectric film do not have good transition, and interface defects between the first dielectric film and the second dielectric film are caused.
In this embodiment, the nitrogen gas is introduced once instead of continuously introducing the nitrogen gas in the process of forming the second dielectric film, so that the production cost is saved on one hand, and the process is simplified by introducing enough nitrogen gas once on the other hand.
In this embodiment, the reason why nitrogen is not introduced in the last secondary deposition etching process is that after the primary deposition etching process, a first dielectric film is formed on the surface of the substrate and the side wall and the bottom surface of the trench, and then a second dielectric film is formed by the secondary deposition etching process, so that a better transition process can be achieved between the formed second dielectric film and the first dielectric film, defects between the interfaces of the first dielectric film and the second dielectric film are reduced, problems such as electric leakage are reduced, and the isolation effect is improved.
In the embodiment, nitrogen is introduced in the secondary deposition process of the first secondary deposition etching process, and if nitrogen is introduced in the secondary etching process, the probability of hole formation is increased, because the secondary etching process is performed to etch the dielectric film at the corner of the trench, a larger trench opening is provided for the next secondary deposition process, and the phenomenon of shrinkage cavity does not occur between the second dielectric film formed by the next secondary deposition process and the second dielectric film formed by the previous secondary deposition process; and nitrogen is introduced in the secondary etching process, and the introduced nitrogen is decomposed into ions to react with the silicon surface to form a film layer attached to the surface of the substrate and the side wall and the bottom of the groove, so that the opening distance of the groove is reduced, the acting force of the air pressure in the groove on a second dielectric film formed by the next secondary deposition process is enhanced, and the probability of shrinkage cavity between two adjacent layers of second dielectric films is increased.
In the embodiment, the purpose of introducing nitrogen in the process of the secondary deposition process is to utilize the introduced nitrogen to be dissociated into ions to react with the silicon surface to form silicon nitride, and since the silicon nitride has good step coverage capacity, after the first layer of second dielectric film 401 is formed in the primary deposition process, the second layer of second dielectric film and the third layer of second dielectric film are formed subsequently, and until the nth layer of second dielectric film is filled in the groove, the phenomenon of shrinkage cavities cannot occur between the adjacent layers of second dielectric films, so that good coverage among the formed layers of second dielectric films is ensured, and the probability of holes occurring inside the dielectric layer when the groove isolation structure is formed is reduced.
In the embodiment, a secondary deposition etching process is adopted for 5 times; in other embodiments, a secondary deposition etching process may be adopted for 4 times, 6 times, 8 times, 9 times, and 10 times, and the actual cycle number may be set according to actual needs.
In this embodiment, the secondary deposition process includes a first deposition process and a second deposition process; the secondary etching process comprises a first etching process and a second etching process.
In this embodiment, nitrogen is introduced into the secondary deposition process of the 1 st time, and in the secondary deposition etching processes from the 1 st time to the 2 nd time, the secondary deposition process is a first deposition process, and the secondary etching process is a first etching process.
In this embodiment, the deposition process for forming the first layer of the second dielectric film 401 and the second layer of the second dielectric film 402 is the same as the deposition process for forming the first dielectric film 300, and both the deposition process and the deposition process adopt a first deposition process, and the parameters of the first deposition process include: the gas used comprises SiH4And oxygen, wherein the SiH4The flow rate of the gas is 20-60 sccm, the flow rate of the oxygen gas is 30-70 sccm, the pressure of the chamber is 3-7 mtorr, and the source power is 1000-5000W.
In this embodiment, the etching process for forming the first layer of the second dielectric film 401 and the second layer of the second dielectric film 402 is the same as the etching process for forming the first dielectric film 300, and both the first etching process and the second etching process adopt the following parameters: the adopted gas comprises oxygen and argon, wherein the flow rate of the oxygen is 50 sccm-150 sccm, the flow rate of the argon gas is 300 sccm-700 sccm, the chamber pressure is 30 mtorr-70 mtorr, the source power is 300W-700W, and the bias voltage is-300V-700V.
In other embodiments, the second deposition and etching processes for forming the first layer of the second dielectric film 401 and the second layer of the second dielectric film 402 may also adopt a second deposition process and a second etching process.
Referring to fig. 7, a plurality of second deposition etching processes are adopted, a plurality of second dielectric films are formed on the surface of the second dielectric film, and nitrogen is introduced into at least one of the second deposition etching processes.
In this embodiment, the plurality of layers of overlapped second dielectric films include: a second dielectric film 402 on the first second dielectric film 401, a third second dielectric film 403 on the second dielectric film 402, a fourth second dielectric film 404 on the third second dielectric film 403, and a fifth second dielectric film 405 on the fourth second dielectric film 404.
In this embodiment, the process of forming the third layer of the second dielectric film 403 includes: forming an initial third dielectric film on the second dielectric film 402 by a secondary deposition process; after the second deposition process, etching the initial third layer of second dielectric film by using a second etching process to form the third layer of second dielectric film 403.
In this embodiment, in the N +2 th to nth secondary deposition etching processes, the secondary deposition process is a second deposition process, and the secondary etching process is a second etching process, that is, in the 3 rd to 5 th secondary deposition etching processes, the secondary deposition process is a second deposition process, and the secondary etching process is a second etching process.
In this embodiment, the second deposition process is a high density plasma chemical deposition process (HDPCVD), and the process parameters of the second deposition process include: the gas used comprises SiH4And oxygen, wherein the SiH4The flow rate of the gas is 20 sccm-60 sccm, the flow rate of the oxygen gas is 30 sccm-70 sccm, the pressure of the chamber is 3 mtorr-7 mtorr, and the source power is 2000W-6000W.
In this embodiment, the second etching process includes a dry etching process, and the dry etching process includes: the adopted gas comprises oxygen and argon, wherein the flow rate of the oxygen is 50 sccm-150 sccm, the flow rate of the argon gas is 300 sccm-700 sccm, the chamber pressure is 30 mtorr-70 mtorr, the source power is 400W-800W, and the bias voltage is-400V-800V.
In this embodiment, the process of forming the fourth layer second dielectric film 404 and the fifth layer second dielectric film 405 is the same as the process of forming the third layer second dielectric film 403, and will not be described redundantly here.
In this embodiment, the ratio of the deposition rate in the deposition process to the etching rate in the etching process is defined as a deposition etching ratio, that is: the ratio of the deposition rate of the first deposition process to the etching rate of the first etching process is defined as a first deposition etching ratio; and defining the deposition rate of the second deposition process and the etching rate of the second etching process as a second deposition etching ratio.
In this embodiment, the source power in the second deposition process is increased, and the source power and the bias voltage in the second etching process are increased, so that the second deposition-etching ratio is smaller than the first deposition-etching ratio, which can increase the second etching rate and decrease the second deposition rate, thereby avoiding the defect of shrinkage cavity in the dielectric layer due to premature sealing in the deposition process.
In this embodiment, the second deposition-etching ratio is smaller than the first deposition-etching ratio, and the range of the second deposition-etching ratio is 10% to 80%; when the second deposition etching ratio is less than 10%, the etching rate is too high, over-etching is easily caused, and the isolation effect of the trench isolation structure is influenced; when the second deposition etching ratio is greater than 80%, the deposition rate is faster, the etching rate is too slow, deposition is carried out without etching, the distance of the opening of the trench is smaller, the acting force of the air pressure in the trench on the deposited dielectric film is large, the defect that a hole exists in the formed dielectric layer is caused, and the isolation effect of the formed trench isolation structure is influenced.
In the embodiment, because the nitrogen is introduced in the secondary deposition process, the introduced nitrogen is dissociated into ions under the action of external force and reacts with the silicon surface to form the silicon nitride, and the silicon nitride has good compactness, the external impurities can be isolated from the formed dielectric layer in the process of forming the second dielectric film, so that the formed dielectric layer is not polluted by the external impurities.
In this embodiment, nitrogen is introduced when the first second dielectric film 401 is formed, and during the process of forming the second dielectric film 402, the third second dielectric film 403, the fourth second dielectric film 404, and the fifth second dielectric film 405, nitrogen is always involved in the formation of the second dielectric film 402, the third second dielectric film 403, the fourth second dielectric film 404, and the fifth second dielectric film 405.
In this embodiment, nitrogen is introduced when the first layer of the second dielectric film 401 is formed, and the nitrogen can be consumed cleanly; if nitrogen is introduced in the process of forming the second dielectric film 402, the third dielectric film 403 or the fourth dielectric film 404, the residual nitrogen will not affect the formation of the next trench isolation structure, because silicon nitride has good step coverage capability, the dielectric films with uniform thickness can be formed, and the adjacent dielectric films can be tightly attached together, so that the defect of holes in the dielectric layers can not occur. After forming the fifth layer of the second dielectric film 405, the second dielectric film 400 is planarized.
Accordingly, referring to fig. 7, the present invention also provides a trench isolation structure formed by the above method, including: a substrate 100; a trench 200 in the substrate 100; a dielectric layer on the surface of the substrate 100 and in the trench 200, wherein the dielectric layer includes: a first dielectric film 300 on the surface of the substrate 100, the sidewall and the bottom surface of the trench 200; a second dielectric film 400 located on the surface of the first dielectric film 300, wherein the second dielectric film 400 includes a first layer of second dielectric film 401, a second layer of second dielectric film 402, a third layer of second dielectric film 403, a fourth layer of second dielectric film 404 and a fifth layer of second dielectric film 405, and the first layer of second dielectric film 401 is located on the surface of the first dielectric film 300; the second layer of second dielectric film 402 is positioned on the surface of the first layer of second dielectric film 401; the third layer of second dielectric film 403 is located on the surface of the second layer of second dielectric film 402; the fourth layer of second dielectric film 404 is located on the surface of the third layer of second dielectric film 403; the fifth layer second dielectric film 405 is located on the surface of the fourth layer second dielectric film 404.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method for forming a trench isolation structure, comprising:
providing a substrate;
forming a groove in the substrate;
forming a dielectric layer on the surface of the substrate and in the groove by adopting a high-density plasma deposition process, wherein the high-density plasma deposition process comprises the following steps:
forming a first dielectric film on the surface of the substrate and the side wall and the bottom surface of the groove by adopting a one-time deposition etching process;
the one-time deposition etching process comprises the following steps: forming an initial first dielectric film on the surface of the substrate and the side wall and the bottom of the groove by adopting a first deposition process; after the first deposition process, etching an initial first dielectric film by adopting a first etching process, wherein the parameters of the first etching process comprise: the adopted gas comprises oxygen and argon, wherein the flow rate of the oxygen is 50 sccm-150 sccm, and the flow rate of the argon gas is 300 sccm-700 sccm;
and forming a plurality of layers of overlapped second dielectric films on the surface of the first dielectric film by adopting a plurality of secondary deposition etching processes, and introducing nitrogen into at least one secondary deposition etching process.
2. The method of claim 1, wherein the parameters of the first deposition process comprise: the gas used comprises SiH4And oxygen, wherein the SiH4The flow rate of the gas is 20-60 sccm, the flow rate of the oxygen gas is 30-70 sccm, the pressure of the chamber is 3-7 mtorr, and the source power is 1000-5000W.
3. The method of forming a trench isolation structure of claim 1 wherein the parameters of the first etch process further comprise: the chamber pressure is 30-70 mtorr, the source power is 300-700W, and the bias voltage is-300V-700V.
4. The method for forming a trench isolation structure as claimed in claim 1, wherein the secondary deposition etching process comprises: forming an initial second dielectric film on the first dielectric film by adopting a secondary deposition process; and after the secondary deposition process, etching the initial second dielectric film by adopting a secondary etching process.
5. The method for forming a trench isolation structure as claimed in claim 4, wherein the secondary deposition process comprises a first deposition process and a second deposition process; the secondary etching process comprises a first etching process and a second etching process.
6. The method of claim 5, wherein the parameters of the second deposition process comprise: the gas used comprises SiH4And oxygen, wherein the SiH4The flow rate of the gas is 20 sccm-60 sccm, the flow rate of the oxygen gas is 30 sccm-70 sccm, the pressure of the chamber is 3 mtorr-7 mtorr, and the source power is 2000W-6000W.
7. The method for forming a trench isolation structure as claimed in claim 5, wherein the parameters of the second etching process include: the adopted gas comprises oxygen and argon, wherein the flow rate of the oxygen is 50 sccm-150 sccm, the flow rate of the argon gas is 300 sccm-700 sccm, the chamber pressure is 30 mtorr-70 mtorr, the source power is 400W-800W, and the bias voltage is-400V-800V.
8. The method for forming a trench isolation structure as claimed in claim 5, wherein a ratio of a deposition rate of the first deposition process to an etching rate of the first etching process is a first deposition-etching ratio, a ratio of a deposition rate of the second deposition process to an etching rate of the second etching process is a second deposition-etching ratio, and the first deposition-etching ratio is greater than the second deposition-etching ratio.
9. The method of claim 8, wherein the second deposition/etch ratio is in a range of 10% to 80%.
10. The method for forming a trench isolation structure as claimed in claim 5, wherein the number of times of the secondary deposition etching process is N times; and introducing nitrogen into at least one secondary deposition process in the secondary deposition and etching processes from 1 st to N-1 st, wherein N is a natural number more than or equal to 2.
11. The method for forming a trench isolation structure as claimed in claim 10, wherein nitrogen is introduced into the N-th secondary deposition process, and in the 1 st to N +1 st secondary deposition etching processes, the secondary deposition process is a first deposition process, the secondary etching process is a first etching process, and N is a natural number less than N.
12. The method for forming a trench isolation structure as claimed in claim 11, wherein in the (N + 2) th to nth secondary deposition etching processes, the secondary deposition process is a second deposition process, and the secondary etching process is a second etching process.
13. The method for forming a trench isolation structure as claimed in claim 1 or 12, wherein the number of times of the secondary deposition etching process is 4 or 5.
14. The method for forming a trench isolation structure as claimed in claim 1, wherein the trench has an aspect ratio of 2:1 to 6: 1.
15. The method of forming a trench isolation structure of claim 1, further comprising: and flattening the plurality of layers of overlapped second dielectric films.
16. The method of claim 1 or 10, wherein a volume of the nitrogen gas is between 10 ml and 300 ml.
17. The method of claim 1, wherein the first dielectric film comprises silicon oxide.
18. The method of claim 1, wherein the second dielectric film comprises silicon oxide, silicon nitride or silicon oxynitride.
19. A trench isolation structure formed by the method of any of claims 1 through 18, comprising:
a substrate;
a trench in the substrate;
the dielectric layer is positioned on the surface of the substrate and in the groove, and comprises:
the first dielectric film is positioned on the surface of the substrate, the side wall and the bottom surface of the groove;
and the second dielectric films are overlapped and positioned on the surface of the first dielectric film, and the second dielectric films contain nitrogen elements.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040055350A (en) * 2002-12-20 2004-06-26 아남반도체 주식회사 Method of manufacturing semiconductor
CN101345205A (en) * 2007-07-09 2009-01-14 茂德科技股份有限公司 Preparation method for shallow trench isolation structure
CN101459111A (en) * 2007-12-13 2009-06-17 中芯国际集成电路制造(上海)有限公司 Shallow groove isolation region forming method and dielectric layer forming method
CN105390438A (en) * 2014-08-21 2016-03-09 朗姆研究公司 Method for void-free cobalt gap fill
CN109585357A (en) * 2017-09-29 2019-04-05 台湾积体电路制造股份有限公司 The manufacturing method of dielectric layer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100035000A (en) * 2008-09-25 2010-04-02 삼성전자주식회사 Semiconductor device having isolation layer with isolation trench of different aspect ratio and isolation trench gap fill method of fabricating the same
KR102037869B1 (en) * 2013-02-08 2019-10-29 삼성전자주식회사 Methods of Fabricating Semiconductor Devices Having an STI

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040055350A (en) * 2002-12-20 2004-06-26 아남반도체 주식회사 Method of manufacturing semiconductor
CN101345205A (en) * 2007-07-09 2009-01-14 茂德科技股份有限公司 Preparation method for shallow trench isolation structure
CN101459111A (en) * 2007-12-13 2009-06-17 中芯国际集成电路制造(上海)有限公司 Shallow groove isolation region forming method and dielectric layer forming method
CN105390438A (en) * 2014-08-21 2016-03-09 朗姆研究公司 Method for void-free cobalt gap fill
CN109585357A (en) * 2017-09-29 2019-04-05 台湾积体电路制造股份有限公司 The manufacturing method of dielectric layer

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