KR20040093558A - Method for forming element isolation layer of semiconductor device - Google Patents
Method for forming element isolation layer of semiconductor device Download PDFInfo
- Publication number
- KR20040093558A KR20040093558A KR1020030027473A KR20030027473A KR20040093558A KR 20040093558 A KR20040093558 A KR 20040093558A KR 1020030027473 A KR1020030027473 A KR 1020030027473A KR 20030027473 A KR20030027473 A KR 20030027473A KR 20040093558 A KR20040093558 A KR 20040093558A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- linear
- oxide film
- layer
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000002955 isolation Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 93
- 238000000151 deposition Methods 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 소자 분리막 형성방법에 관한 것으로서, 보다 상세하게는 기존의 STI공정에 적용되는 선형 질화막과 선형 산화막으로 구성된 다중층 선형 구조막중 선형 산화막 상부에 선형비정질 실리콘 박막을 추가 적용하여 소자 분리막을 형성하는 반도체 소자의 소자 분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation layer of a semiconductor device, and more particularly, to a device by adding a linear amorphous silicon thin film on top of a linear oxide film in a multilayer linear structure film composed of a linear nitride film and a linear oxide film applied to a conventional STI process. The present invention relates to a device isolation film forming method of a semiconductor device for forming a separator.
메모리 반도체 소자의 개별 셀(cell)의 절연 방법으로 현재 보편적으로 사용되는 것은 STI(Shallow Trench Isolation)공정이다.A widely used method of insulating individual cells of a memory semiconductor device is a shallow trench isolation (STI) process.
이하 기존의 STI공정을 이용한 소자 분리막 형성방법을 간략하게 설명하도록 한다.Hereinafter, a method of forming an isolation layer using an existing STI process will be briefly described.
먼저, 도면에는 도시하지 않았지만, 실리콘 기판상에 패드 산화막과 패드 질화막을 차례로 형성한 다음, 공지의 공정에 따라 상기 막들을 패터닝하여 소자분리 영역에 해당하는 기판 부분을 노출시키고, 이어 노출된 기판 부분을 식각하여 트렌치를 형성한다.First, although not shown in the drawing, a pad oxide film and a pad nitride film are sequentially formed on a silicon substrate, and then the films are patterned according to a known process to expose a substrate portion corresponding to an isolation region, and then the exposed substrate portion. Etch to form a trench.
이어서, 식각데미지를 회복시키기 위해 상기 트렌치를 포함한 기판전체에 측벽 산화막 공정및 선형 질화막, 선형 산화막 공정을 차례로 수행하고, 상기 트렌치를 매립하도록 상기 기판상에 PECVD(Plasma Enhanced Chemical Vapor Deposition)방법을 이용해 HDP산화막을 증착한다.Subsequently, a sidewall oxide process, a linear nitride film, and a linear oxide film process are sequentially performed on the entire substrate including the trench in order to recover the etch damage, and using PECVD (Plasma Enhanced Chemical Vapor Deposition) method on the substrate to fill the trench. An HDP oxide film is deposited.
그 다음, 상기 HDP산화막의 표면을 CMP공정을 통하여 평탄화 시킨후, 상기 선형 산화막 선형 질화막,측벽 산화막및 패드 질화막과 패드 산화막을 차례로 제거하여 소자 분리막을 형성한다.Then, the surface of the HDP oxide film is planarized through a CMP process, and then the linear oxide film, the linear nitride film, the side wall oxide film, the pad nitride film, and the pad oxide film are sequentially removed to form a device isolation film.
그러나 기존의 STI공정방법에서, 상기 선형 질화막과 갭매립산화막인 HDP산화막의 스트레스(stress)물성은 정반대이므로 직접 콘택(contact)이 되면 버블(bubble) 형태의 결함이 발생하게 된다.However, in the conventional STI process, since the stress properties of the linear nitride film and the HDP oxide film, which is a gap buried oxide film, are opposite, direct contact causes bubble defects to occur.
이러한 문제를 해결하기 위해 HTO(High Temperature Oxide)계열의 선형 산화막이 선형 질화막과 갭매립 산화막 사이에 버퍼역할을 하게 된다.In order to solve this problem, the HTO (Linear Oxide) -based linear oxide film serves as a buffer between the linear nitride film and the gap buried oxide film.
그러나 상기 구조를 형성하기 위해 PECVD공법으로 HDP산화막을 증착하는 과정에서 선형 산화막이 증착 초기에 플라즈마 압력을 견디지 못하고 손실(loss)되는 문제가 발생한다.However, in the process of depositing the HDP oxide film by PECVD to form the structure, a problem occurs that the linear oxide film does not endure plasma pressure at the initial stage of deposition and is lost.
이러한 문제를 해결하기 위해 현재 당사에서 사용되는 방법으로, 갭매립 산화막을 증착시 2-스텝으로 증착하는 공정을 사용하고 있다. 즉, 갭매립 산화막 증착초기에는 낮은 압력으로 일정 두께의 산화막층을 형성한 후 후속으로 높은 압력을 이용해 나머지 부분을 채워주는 방법을 사용한다.In order to solve this problem, the present method used by the company uses a process of depositing a gap-filled oxide film in two steps during deposition. That is, in the initial gap-filling oxide deposition, a method of forming an oxide layer having a predetermined thickness at a low pressure and subsequently filling the remaining portion using a high pressure is performed.
하지만 이러한 2 -스텝증착방법을 이용하게 되면, 트렌치로 파내야 하는 스페이서 부분의 CD(critical dimension) 는 줄어들게 되고 HDP산화막으로 채울 수 있는 스텝 커버리지 (Step-coverage)는 3.5~5.0사이이므로 초기 단계에서 낮은 압력으로 산화막을 증착함에 따라 트렌치 스페이서(spacer)사이즈가 줄어들게 되어 갭매립 마진(margin)은 더욱 줄어드는 상황이다.However, when using this two-step deposition method, the CD (critical dimension) of the spacer portion to be dug into the trench is reduced and the step coverage that can be filled with HDP oxide is 3.5 ~ 5.0 As the oxide film is deposited at a low pressure, the trench spacer size is reduced, and thus the gap filling margin is further reduced.
따라서, 선형 질화막 상부에 버퍼 층으로 형성되는 물질이 현재 사용되고 있는 HTO계열의 산화막보다 식각내성이 강화되어야 하며, 그렇지 않을 경우 갭매립 산화막 증착시 갭매립에 문제가 생겨 트렌치 내부에 보이드결함(Void defect)이 발생하는 문제점이 있다.Therefore, the etch resistance of the material formed as a buffer layer on the linear nitride layer must be enhanced than that of the HTO-based oxide, which is otherwise used. Otherwise, there is a problem of gap filling during deposition of the gap-filling oxide film, resulting in void defects in the trench. ) Is a problem that occurs.
또한, 갭매립 마진을 고려해 선형 질화막만을 증착할 경우에는 주변 회로 지역의 크기(size)가 큰 패턴에서 선형 질화막과 갭매립 산화막의 접착(adhesion) 불량에 의해 발생되는 버블결함(bubble defect)을 피할 수가 없게 된다.In addition, when only the linear nitride film is deposited in consideration of the gap filling margin, a bubble defect caused by poor adhesion between the linear nitride film and the gap-filling oxide film is avoided in a pattern having a large size of the peripheral circuit area. You will not be able to.
이에 본 발명은 상기 종래 기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 기존의 STI공정과정에서 사용되는 선형 산화막 구조가 후속 갭매립 산화막 증착초기단계에서 공격(attack)을 받아 손실되는 것을 막기위해 선형비정질 (Amorphous) 실리콘층을 추가 증착함으로서 갭매립 산화막증착시 마진을 확보할 수 있는 반도체 소자의 소자 분리막 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, the linear oxide film structure used in the existing STI process is a linear to prevent the loss of the attack (attach) during the initial gap-buried oxide film deposition initial stage It is an object of the present invention to provide a method for forming a device isolation layer of a semiconductor device which can secure a margin when depositing an amorphous silicon layer by further depositing an amorphous silicon layer.
도 1a내지 도 1d는 본 발명의 실시예에 따른 비정질 실리콘 증착 과정을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating an amorphous silicon deposition process according to an embodiment of the present invention.
-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing
1 : 실리콘 기판 11 : 선형 질화막1: silicon substrate 11: linear nitride film
3 : 패드 산화막 13 : 선형 산화막3: pad oxide film 13: linear oxide film
5 : 패드 질화막 15 : 비정질 실리콘5: pad nitride film 15: amorphous silicon
7 : 트렌치 17 : 갭매립 산화막7: trench 17: gap filling oxide film
9 : 측벽 산화막 17a : 소자 분리막9 side wall oxide film 17a device isolation film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법은, 실리콘 기판상에 패드 산화막과 패드 질화막을 차례로 형성하는 단계; 상기 패드 질화막상에 STI마스크 패턴을 형성하는 단계; 상기 STI마스크 패턴을 마스크로 상기 패드 질화막과 패드 산화막 및 실리콘 기판을 순차적으로 식각하여 실리콘 기판내에 트렌치를 형성하는 단계; 상기 트렌치 상에 측벽 산화막을 형성한 후 다중층 선형 구조막을 형성하는 단계; 상기 선형 산화막상에 선형 비정질 실리콘을 증착하는 단계; 상기 선형 비정질 실리콘상에 HDP산화막을 형성하는 단계; 상기 HDP산화막을 CMP공정으로 평탄화시킨후 트렌치 이외 부분의 상기 비정질실리콘, 선형 산화막, 선형 질화막을 차례로 제거하는 단계; 및According to another aspect of the present invention, there is provided a method of forming a device isolation film of a semiconductor device, the method comprising: sequentially forming a pad oxide film and a pad nitride film on a silicon substrate; Forming an STI mask pattern on the pad nitride film; Sequentially etching the pad nitride layer, the pad oxide layer, and the silicon substrate using the STI mask pattern as a mask to form a trench in the silicon substrate; Forming a multilayer linear structured film after forming a sidewall oxide film on said trench; Depositing linear amorphous silicon on the linear oxide film; Forming an HDP oxide film on the linear amorphous silicon; Planarizing the HDP oxide film by a CMP process, and then removing the amorphous silicon, the linear oxide film, and the linear nitride film in a portion other than the trench; And
상기 패드 질화막, 패드 산화막을 차례로 제거하여 상기 트렌치내에 소자 분리막을 형성하는 단계를 포함하여 구성되는 것을 특징으로 한다.And removing the pad nitride layer and the pad oxide layer in order to form an isolation layer in the trench.
(실시예)(Example)
이하, 본 발명에 따른 반도체 소자의 소자 분리막 형성방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a device isolation layer of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a내지 도 1d는 본 발명에 따른 반도체 소자의 소자 분리막 형성방법을 설명하기 위한 공정 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a device isolation layer of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 소자 분리막 형성방법은, 도 1a에 도시된 바와 같이, 실리콘 기판(1)상에 패드 산화막(3)및 패드 질화막(5)을 차례로 증착한다.In the method of forming a device isolation film of a semiconductor device according to the present invention, as shown in FIG. 1A, a pad oxide film 3 and a pad nitride film 5 are sequentially deposited on a silicon substrate 1.
그다음, 도 1b에 도시된 바와 같이, 상기 패드 질화막(5)상에 감광 물질을 도포하고 포토리소그라피 공정기술에 의한 노광 및 현상공정을 거쳐, 이를 선택적으로 제거하여 소자 분리 영역을 한정하는 STI마스크 패턴을 형성한다.Next, as shown in FIG. 1B, an STI mask pattern is applied to the pad nitride layer 5 to apply a photosensitive material, and is subjected to an exposure and development process using a photolithography process technology to selectively remove the STI mask pattern to define an isolation region of the device. To form.
이어서, 상기 STI마스크 패턴을 마스크로 상기 패드 질화막(5)과 패드 산화막(3)및 실리콘 기판(1)을 선택적으로 식각하여 상기 실리콘 기판(1)내에 트렌치 (7)를 형성한다.Subsequently, the pad nitride film 5, the pad oxide film 3, and the silicon substrate 1 are selectively etched using the STI mask pattern as a mask to form a trench 7 in the silicon substrate 1.
그다음, 도 1c에 도시된 바와 같이, 상기 트렌치 내에 식각데미지를 회복시키기 위해 측벽 산화막(9)및 선형 질화막(11)을 차례로 증착한다. 다음으로 상기 선형 질화막상(11)에 스트레스 버퍼가 될 선형 산화막(13)및 선형 비정질 실리콘층(15)을 차례로 증착한다. 이때 버퍼층으로 증착되는 선형 산화막(13)은 LP-CVD(low pressure CVD)방법으로 증착할 수 있으며, 10~50Å으로 증착하여 버퍼층 두께를 최소화 한다. 또한 비정질 실리콘 박막역시 LP-CVD 방법으로 증착할 수 있으며 후속 갭매립 산화막 증착및 산화(oxidation) 공정을 고려하여 두께는 50~200Å으로 증착한다. 상기 선형 비정질 실리콘층(15)을 사용함으로써 선형 질화막과의 스트레스가 반대인 점을 이용하여 버블결함(bubble defect)을 제거할 수 있다.Next, as shown in FIG. 1C, the sidewall oxide film 9 and the linear nitride film 11 are sequentially deposited to recover etch damage in the trench. Next, a linear oxide film 13 and a linear amorphous silicon layer 15 to be a stress buffer are deposited on the linear nitride film 11 in order. In this case, the linear oxide film 13 deposited as the buffer layer may be deposited by low pressure CVD (LP-CVD), and the thickness of the buffer layer may be minimized by depositing at 10 to 50Å. In addition, amorphous silicon thin film can also be deposited by LP-CVD method and the thickness is deposited to 50 ~ 200Å considering the gap gap oxide film deposition and oxidation process. By using the linear amorphous silicon layer 15, bubble defects can be removed by using a point where the stress with the linear nitride film is opposite.
이어서, 1d에 도시된 바와 같이, 상기 비정질 실리콘상에 갭매립 산화막(17)을 증착후 CMP공정으로 평탄화 시킨후 상기 다중층 선형 구조막 및 패드 질화막과 패드산화막을 적절히 제거하여 소자 분리막(17a)을 남길 수 있다.Subsequently, as shown in 1d, the gap buried oxide film 17 is deposited on the amorphous silicon and then planarized by a CMP process, and then the multilayer linear structure film, the pad nitride film, and the pad oxide film are appropriately removed to remove the device isolation film 17a. You can leave
이상에서와 같이, 본 발명에 따른 반도체 소자의 소자 분리막 형성방법에 의하면, 비정실 실리콘 버퍼층을 사용하여 갭매립 산화막과 선형 질화막사이의 버블 결함(bubble defect)을 방지 할 수 있으며 기존의 2-단계로 증착되었던 CVD갭매립 산화막 증착 공정을 1단계로 줄임으로써 갭필 마진을 늘려줄 수 있다.As described above, according to the device isolation film forming method of the semiconductor device according to the present invention, it is possible to prevent bubble defects between the gap buried oxide film and the linear nitride film by using an amorphous silicon buffer layer, and the conventional two-step The gap fill margin can be increased by reducing the CVD gap buried oxide deposition process, which has been deposited as a single step.
또한, 기존의 선형 산화막으로서, HTO(High temperature oxide)계열의 산화막만을 사용후 갭매립 산화막을 형성했을때 문제가 되었던 버퍼층의 손실을 막을 수 있어 갭매립 산화막의 트랜치 내의 마진을 확보할 수 있다.In addition, as a conventional linear oxide film, only a high temperature oxide (HTO) -based oxide film can be used to prevent the loss of the buffer layer, which is a problem when forming a gap buried oxide film, thereby securing a margin in the trench of the gap buried oxide film.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구 범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030027473A KR20040093558A (en) | 2003-04-30 | 2003-04-30 | Method for forming element isolation layer of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030027473A KR20040093558A (en) | 2003-04-30 | 2003-04-30 | Method for forming element isolation layer of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20040093558A true KR20040093558A (en) | 2004-11-06 |
Family
ID=37373521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020030027473A KR20040093558A (en) | 2003-04-30 | 2003-04-30 | Method for forming element isolation layer of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20040093558A (en) |
-
2003
- 2003-04-30 KR KR1020030027473A patent/KR20040093558A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100590383B1 (en) | Method of forming a field oxide layer in semiconductor device | |
| KR20020085390A (en) | Trench isolation method | |
| KR19990061066A (en) | Method of forming device isolation film of semiconductor device | |
| KR20040093558A (en) | Method for forming element isolation layer of semiconductor device | |
| KR100305026B1 (en) | Manufacturing method of semiconductor device | |
| KR20000020909A (en) | Method for isolating trench device having double layer nitride liner | |
| KR100344765B1 (en) | Method for isolating semiconductor devices | |
| KR100811258B1 (en) | Method of fabricating the semiconductor device having WSix gate structure | |
| KR19990057375A (en) | Device Separating Method of Semiconductor Device | |
| KR100361765B1 (en) | A method for fabricating of a semiconductor device | |
| KR100274349B1 (en) | Method of forming a field oxide firm in a semiconductor device | |
| KR100482749B1 (en) | Method of manufacturing a semiconductor device | |
| KR20010005303A (en) | Forming method for self aligned contact | |
| KR100861307B1 (en) | Method of manufacturing isolation layer for semiconductor device | |
| KR20050002479A (en) | method for forming landing plug | |
| KR20040072269A (en) | Method for forming dual storage node contact plug | |
| KR20030000490A (en) | Manufacturing method for semiconductor device | |
| KR20030055804A (en) | method for fabricating bit line | |
| KR20040086691A (en) | Method for manufacturing semiconductor device | |
| KR20020087557A (en) | Method of forming a floating gate in a flash memory cell | |
| KR20030003306A (en) | Method for fabricating a landing plug of semiconductor device | |
| KR20050000056A (en) | Method for forming isolation layer of semiconductor device | |
| KR20010061012A (en) | Manufacturing method of semiconductor device | |
| KR20040057605A (en) | method for manufacturing storage node contact in semiconductor device | |
| KR20020010799A (en) | A method for forming of a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |