KR20000020909A - Method for isolating trench device having double layer nitride liner - Google Patents

Abstract

PURPOSE: A method for isolating trench device having double layer nitride liner is provided to prevent the reduction of a threshold voltage and the double turn-on of a transistor due to a dent or a groove formed on the interface between an active region and a field region. CONSTITUTION: A trench(117) comprises a double layered nitride liner on a side wall of the trench to prevent a stress generated with a post oxidation process. An etch mask pattern(115) revealing a top of a semiconductor substrate(110) of a field region is formed by patterning an etch mask film deposited on the top of the semiconductor substrate. After forming a trench on the semiconductor substrate of the revealed field region, a first and a second nitride liner(125,130) are deposited in sequence to wrap the inside of the trench and the etch mask pattern. An isolation film(135) is formed by filling the inside of the trench with an insulation material and is flatted until a top surface of the second nitride liner is revealed. As revealing the etch mask pattern, two nitride liners are removed until the top revealed surface is as high as the top surface of the semiconductor substrate of the active region. Thus, by the method the generation of a dent or a groove is prevented, and the reliability of a device is improved by removing the hump phenomenon and the reduction of the threshold voltage.

Description

Trench device isolation method with double layer nitride liner

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench isolation method for semiconductor devices, and more particularly, to a trench isolation method having a double layer nitride nitride liner on a sidewall to prevent stress caused by subsequent oxidation processes.

The trench isolation method, which has recently been in the spotlight as a device isolation technology of the semiconductor manufacturing process, has a semiconductor device having dimensions that are impossible with conventional LOCOS technology because the separation distance between devices becomes very narrow due to the high integration of semiconductor devices. It is used for device isolation of devices.

However, in the trench isolation method, the stress of the lower and upper corners of the trench and the high temperature heat treatment process and subsequent oxidation process for densification of the buried material exert excessive stress on the substrate silicon. There is a problem that causes a stacking fault. To prevent this, a method of preventing a stress applied to a silicon substrate by developing a thin silicon nitride layer on the trench sidewalls has been developed.

However, the conventional trench isolation method using a single layer of silicon nitride layer proceeds approximately to the following process. First, a silicon nitride layer is stacked on the semiconductor substrate in order to define an active region and a field region of the semiconductor substrate and use it as an etching mask for forming trenches in the semiconductor substrate defined by the field region. After the patterning and etching process is performed to form a trench in the semiconductor substrate in the field region, an isolation material is embedded in the trench to form an isolation layer. Meanwhile, a buffer oxide film is formed on the sidewalls of the trench before the insulation is buried in the trench, and a nitride liner is formed on the buffer oxide film to prevent stress caused by the above-described problem, that is, a subsequent oxidation process. Buried insulation inside. Thereafter, a process of removing the material layer stacked on the semiconductor substrate is performed. The planarization and etching processes are performed appropriately to expose the upper surface of the semiconductor substrate in the active region, and the top surface of the device isolation layer is the exposed semiconductor of the active region. Match to the substrate surface.

In the conventional device isolation method, during the etching process for removing the silicon nitride layer formed on the semiconductor substrate in the active region, the nitride liner on the sidewall of the trench used as an anti-stress layer is etched due to excessive etching. Problem occurs. This causes a groove (dent or groove) at the boundary between the active region of the semiconductor substrate and the field region filled with the insulator material, which reduces the hump phenomenon and the threshold voltage of the transistor to be turned on later. Provide a cause.

Hereinafter, a trench isolation method for a semiconductor device according to the related art will be described with reference to the accompanying drawings and a problem thereof will be described.

1 and 2 are cross-sectional views illustrating a conventional trench device isolation method.

1 is a cross-sectional view illustrating a method of forming a trench in a field region of a semiconductor substrate. An etching mask layer having a predetermined thickness is deposited on the semiconductor substrate 10. In this case, the etch mask film may form a single layer or a multilayer, and it is common to form and use a multilayer structure in which a pad oxide film, a silicon nitride layer, and a silicon oxide layer are sequentially stacked. Meanwhile, the silicon oxide layer, which is the uppermost layer of the multilayer, is not essential and is a material layer that can be arbitrarily selected. Subsequently, in order to separate the semiconductor substrate into the active region and the field region, the etching mask layer is patterned to form the etching mask patterns 15, 20, and 25 exposing the upper surface of the field region of the semiconductor substrate. The trench 40 is formed by etching the semiconductor substrate of the field region exposed by the etching mask patterns 15, 20, and 25 to a predetermined depth. A sidewall oxide film 30 is formed by depositing an oxide film having a predetermined thickness on the sidewalls 27 of the trench 40. Finally, the nitride liner 35 is deposited on the entire surface of the resultant substrate.

FIG. 2 is a cross-sectional view illustrating a groove formed at a boundary between an isolation layer formed by filling an insulating material in a trench and an upper portion of a semiconductor substrate in an active region. First, an isolation material is embedded in the trench 40 of FIG. 1 to form an isolation layer 45. Thereafter, the material layers stacked on the upper surface of the semiconductor substrate in the active region are removed. In this case, since the silicon nitride layer (20 in FIG. 1) used as an etching mask is deposited to a considerable thickness or more, a pad oxide film pattern (FIG. 1) is removed by a planarization process to a predetermined thickness and then the remaining thickness is removed by an etching process to remove it. 15) it is common to proceed to the step of exposing. However, the nitride liner exposed in the process of removing the silicon nitride layer 20 of FIG. 1 may also be etched. However, if the process of completely removing the silicon nitride layer (20 in FIG. 1) stacked on the semiconductor substrate in the active region is performed, the etching of the nitride liner may be excessively performed. Meanwhile, the upper surface of the device isolation layer 45 is also deformed to some extent by the etching process. Through the above-mentioned steps, as shown in FIG. 2, grooves are formed at the boundary between the upper portion of the semiconductor substrate in the active region and the device isolation layer 45 (see reference numeral “A”).

When such a groove is generated, it is obvious that serious problems as described above are occurring, and efforts to prevent this are incessantly progressed in the art.

The technical problem to be achieved by the present invention is a single layer nitride liner formed on the upper sidewall of the trench during the etching process to remove the etching mask pattern made of silicon nitride formed on the semiconductor substrate to form a trench, the upper surface of the semiconductor substrate of the active region As a result, grooves or grooves are formed at the boundary between the excessively etched semiconductor substrate in the active region and the field region where the device isolation layer is formed, thereby causing a double turn-on of the transistor using the substrate. And the problem that the threshold voltage is reduced is prevented from occurring.

1 and 2 are cross-sectional views illustrating a conventional trench device isolation method.

3 to 6 are cross-sectional views illustrating an embodiment of a trench isolation method according to the present invention.

The trench device isolation method provided by the present invention for achieving the technical problem described above is as follows.

(A) An etching mask film having a predetermined thickness is deposited on the semiconductor substrate. (B) The etching mask layer is patterned to separate the semiconductor substrate into an active region and a field region. Thus, an etch mask pattern exposing the upper portion of the semiconductor substrate in the field region is formed. (C) A trench is formed by etching the semiconductor substrate in the field region exposed by the etching mask pattern to a predetermined depth. (D) A sidewall oxide film is formed by depositing an oxide film having a predetermined thickness on the trench sidewalls. Thereafter, the first nitride liner and the second nitride liner each having a predetermined thickness are sequentially deposited to surround the sidewall oxide layer and the etching mask pattern. (E) An isolation layer is formed by filling an insulator in the trench surrounded by the stacked two nitride liners. (F) The device isolation layer is planarized until the upper surface of the second nitride liner is exposed. (G) The etching mask pattern is exposed by removing the second nitride liner and the first nitride liner below the upper surface. Subsequently, the two nitride liners are etched to remove the two nitride liners of the exposed sidewalls of the etch mask pattern until the top exposed surface thereof coincides with the top surface of the semiconductor substrate in the active region below the etch mask pattern. As a result, sidewalls of the etch mask pattern are exposed, and the planarized device isolation layer protrudes. (H) The exposed etching mask pattern is completely removed. This exposes the upper surface of the semiconductor substrate in the active region below it. An etching process is performed so that the upper surface of the protruding device isolation layer matches the upper surface of the semiconductor substrate. Thereafter, the subsequent process proceeds in a conventional manner appropriate to the semiconductor device to be manufactured.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art related to the present invention. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. In the drawings like reference numerals refer to like elements. In addition, where a layer is described as being "on top" of another layer or substrate, the layer may be present directly on top of the other layer or substrate, with a third layer intervening therebetween.

3 to 6 are cross-sectional views illustrating an embodiment of a trench isolation method according to the present invention.

In this case, the trench device isolation method provided by the present invention described above may be specifically performed by the following.

3 is a cross-sectional view illustrating a method of forming a device isolation film by forming a trench in a field region of a semiconductor substrate and filling an insulator therein. An etching mask layer having a predetermined thickness is deposited on the semiconductor substrate 110. The etching mask layer is preferably formed to a thickness of 500 to 2000Å. Subsequently, an etch mask film is patterned to separate the semiconductor substrate into an active region and a field region to form an etch mask pattern 115 exposing an upper surface of the field region of the semiconductor substrate. The trench 117 is formed by etching the semiconductor substrate in the field region exposed by the etching mask pattern 115 to a predetermined depth. Trench 117 is formed to a thickness of 500 to 10000Å. Meanwhile, after the trench 117 is formed, the etching mask pattern may be further etched so that only a thickness of 100 to 500 내지 remains. A sidewall oxide film 120 is formed by depositing an oxide film having a predetermined thickness on the sidewalls of the trench 117. Subsequently, the first nitride liner 125 and the second nitride liner 130 having a predetermined thickness are deposited in order to surround the sidewall oxide layer 120 and the etching mask pattern 115. On the other hand, the first nitride liner 125 is formed of silicon nitride, the thickness is preferably 30 to 300 내지. The second nitride liner 130 is formed of boron (B) nitride, the thickness is preferably 100 to 300 내지. The first nitride liner 125 is used to prevent defects in the semiconductor substrate and to prevent diffusion of a material constituting the second nitride liner 130, for example, boron, into the semiconductor substrate. Subsequently, the isolation layer 135 is formed by filling an insulating material in the trench surrounded by the stacked two nitride liners 125 and 130. The device isolation layer is planarized until the upper surface of the second nitride liner 130 is exposed. In this case, it is preferable that the device isolation film is carried out by a chemical mechanical polishing (CMP) method.

FIG. 4 is a cross-sectional view for describing a method of removing a nitride layer deposited on an active region of a semiconductor substrate and exposing an etching mask pattern under the nitride layer. On the upper surface of the semiconductor substrate of the active region, the second nitride liner 130 (see FIG. 3) and the first nitride liner 125 (125 below) of which the upper surface is exposed are sequentially removed to remove the etching mask pattern 115. Expose the top surface of the. In this process, the two nitride liners are illustrated as the modified forms 125a and 130a, and the upper portions of the device isolation layers 135 of FIG. 3 are partially etched, and thus, the nitride liners are illustrated as the modified device isolation layers 135a.

FIG. 5 is a cross-sectional view illustrating etching two nitride liners exposed between an active region and a field region of a semiconductor substrate to coincide with an upper surface of the semiconductor substrate of the active region. An etching mask pattern may be removed by removing the top exposed surfaces of the two nitride liners 125a and 130a of the semiconductor substrate resulting from the description with reference to FIG. 4 until they coincide with the top surface of the semiconductor substrate in the active region below the etching mask pattern 115. The two nitride liners are etched such that the planarized isolation layer protrudes by exposing the sidewall of the substrate 115. At this time, the two nitride liners (125a, 130a) are removed by the etching process, there is no particular limitation in the etching process, such as wet or dry, it can be selected arbitrarily proceed. As a result of this etching process, the two dilide liners are shown in modified forms 125b and 130b.

FIG. 6 completely removes the exposed etch mask pattern (115 in FIG. 5) to expose the upper surface of the semiconductor substrate 110 in the lower active region, and activates the upper surface of the protruding device isolation layer (125b in FIG. 5). The device isolation film 135b is illustrated by performing an etching process to match the upper surface of the semiconductor substrate 110 in the region. At this time, the etching process is preferably carried out by a wet etching method. On the other hand, it can be seen from the drawings that no groove, which is a problem of the prior art (see part "A" in Fig. 2), is generated (see reference numeral B).

The trench device isolation method described with reference to FIGS. 4 to 6 can be obtained by performing the following. An etching mask film for forming an etching mask pattern (115 in FIG. 3) is formed to a thickness of 500 to 2000 내지. The trench 117 of FIG. 3 is formed to a thickness of 500 to 10000 mm 3. After forming the trench 117 of FIG. 3, the etch mask pattern 115 of FIG. 3 is etched so that only a thickness of 100 to 500 μm remains. The sidewall oxide film (120 in FIG. 3) is formed to a thickness of 100 to 500 GPa. The first nitride liner (125 in Fig. 3) is made of silicon nitride, and its thickness is about 30 to 300 m 3. The second nitride liner (130 in FIG. 3) is formed of boron (B) nitride, and its thickness is about 100 to 300 m 3. The device isolation film (135 in FIG. 3) is performed by a chemical mechanical polishing (CMP) method. The two nitride liners 125 and 130 of FIG. 3 are removed by a wet etching method or a dry etching method. All of the etch mask pattern 115 (in FIG. 5) and the upper portion of the device isolation layer 135a are removed by a wet etching method.

Embodiments of the present invention described with reference to the accompanying drawings are optimal embodiments. Although specific terms have been used herein, they are used only for the purpose of describing the present invention in detail and are not used to limit the scope of the present invention as defined in the meaning or claims. For example, the semiconductor substrate may be replaced with an epitaxial layer.

In the process of removing the silicon nitride film pattern used as an etch mask pattern on the active region of the semiconductor substrate, a large portion of the nitride liner is excessively etched to form grooves at the boundary between the active region and the field region of the semiconductor substrate. Can be prevented. That is, by forming the nitride liner of the thin film instead of the thick silicon nitride film pattern formed on the active region, the etching amount can be reduced, thereby preventing the excessive etching of the nitride liner formed along the trench sidewalls.

Claims (13)

(A) depositing an etching mask film having a predetermined thickness on the semiconductor substrate; (B) forming an etch mask pattern exposing an upper portion of the semiconductor substrate in the field region by patterning the etch mask layer to separate the semiconductor substrate into an active region and a field region; (C) forming a trench by etching the semiconductor substrate of the field region exposed by the etching mask pattern to a predetermined depth; (D) forming a sidewall oxide film by depositing an oxide film having a predetermined thickness on the trench sidewalls, and then sequentially forming a material layer of each of the first nitride liner and the second nitride liner so as to surround the sidewall oxide film and the etching mask pattern. Depositing with; (E) forming an isolation layer by filling an insulating material in a trench surrounded by the stacked two nitride liners; (F) planarizing the device isolation layer until the top surface of the second nitride liner is exposed; (G) removing the second nitride liner and the first nitride liner under which the top surface is exposed to expose the etch mask pattern, and subsequently, the two nitride liners of the exposed etch mask pattern sidewalls with their top exposed surfaces. Etching the two nitride liners so that the planarized device isolation layer is protruded by removing the etch mask until it matches the upper surface of the semiconductor substrate in the active region below the etch mask pattern to expose sidewalls of the etch mask pattern; And (H) completely removing the exposed etch mask pattern to expose the upper surface of the semiconductor substrate in the lower active region, and perform an etching process to match the upper surface of the protruding device isolation layer with the upper surface of the semiconductor substrate. Trench device isolation method comprising the step of. The method of claim 1, The etching mask layer of the step (A) is formed trench trench isolation, characterized in that formed to a thickness of 500 to 2000Å. The method of claim 1, The trench of step (c) is a trench device isolation method, characterized in that to form a thickness of 500 to 10000Å. The method of claim 1, After forming the trench of step (c), the etching mask pattern is further etched so that only a thickness of 100 to 500Å remains, and then the step (d) is performed. . The method of claim 1, The sidewall oxide film of step (d) is formed with a thickness of 100 to 500Å trench trench isolation method. The method of claim 1, The trench isolation method of claim 1, wherein the first nitride liner of step (d) is formed of silicon nitride. The method of claim 1, The trench nitride isolation method of claim 1, wherein the first nitride liner is formed to a thickness of 30 to 300. The method of claim 1, The second nitride liner of the step (d) is a trench device isolation method, characterized in that formed with boron (B) nitride. The method of claim 1, The second nitride liner of the step (d) is formed trench trench isolation, characterized in that to form a thickness of 100 to 300Å. The method of claim 1, The device isolation film of step (bar) is a trench device isolation method, characterized in that proceeding by chemical mechanical polishing (CMP) method. The method of claim 1, The two nitride liners of step (g) are removed by a wet etching method. The method of claim 1, The two nitride liners of step (g) are removed by a trench etching method. The method of claim 1, And removing the entire etching mask pattern and the upper portion of the device isolation layer of step (h) by a wet etching method.