KR20030055804A - method for fabricating bit line - Google Patents

Abstract

PURPOSE: A method for forming a bit line is provided to be capable of preventing bridge generated between a gate and the bit line. CONSTITUTION: After forming a gate(206) on a semiconductor substrate(200), a buffer oxide layer(208) is formed at both sidewalls of the gate. After forming a source/drain region(203) in the substrate, the first insulating layer(222) having the first opening for exposing the source region is formed on the resultant structure. A conductive plug(220) is filled into the first opening. After selectively etching the first insulating layer and the buffer oxide layer, a silicon nitride layer(230) is formed. The second insulating layer having the second opening is formed on the silicon nitride layer(230). A bit line(236) is formed in the second opening.

Description

Method for fabricating bit line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a bit line forming method capable of preventing a bridge phenomenon occurring between a gate and a bit line.

A bit line contact forming process is performed to connect a source and a bit line of a cell transistor. However, during the etching process for forming the bit line contact, a bridge phenomenon in which the gate buffer bit is insulated from the gate and the bit line occurs due to damage of the gate buffer oxide.

1A to 1C are cross-sectional views illustrating a method of forming a bit line according to the related art.

In the bit line forming method according to the related art, as shown in FIG. 1A, first, an isolation layer 202 is formed in an isolation region (not shown) of the semiconductor substrate 100.

Next, a cell transistor is manufactured by forming impurity regions 103 such as a gate 104 and a source / drain on the substrate 100 including the isolation layer 102.

In this case, a buffer oxide layer 108 and an insulating spacer 210 are sequentially formed on the side of the gate 104, and a silicon nitride 106, a cap oxide layer, is formed on the top surface thereof. have.

Next, a first insulating layer 122 is formed on the substrate including the gate 104, and then the first insulating layer 122 is etched by photolithography to expose the impurity region 103. A contact hole (not shown) is formed, and a conductive plug 120 filling the contact hole is formed.

Thereafter, as illustrated in FIG. 1B, the second insulating layer 132 is deposited on the first insulating layer including the conductive plug 120 by a chemical vapor deposition process, and then, as illustrated in FIG. 1C. As described above, the second insulating layer is selectively etched to form a bit line contact hole 134 exposing a portion of the impurity region 103 corresponding to a source.

Subsequently, a bit line metal layer 136 is deposited on the second insulating layer including the bit line contact hole 134.

Next, although not shown in the drawing, the bit line metal film is selectively etched to form bit lines.

However, in the related art, when a bit line contact hole for connecting a source and a bit line of a cell transistor is formed, the buffer oxide layer of the gate is also etched, thereby preventing the gate and the bit line from being insulated and bridged.

Accordingly, an object of the present invention is to provide a bit line forming method capable of preventing a bridge phenomenon occurring between a gate and a bit line.

1A to 1C are cross-sectional views illustrating a method of forming a bit line according to the prior art.

2A through 2D are cross-sectional views illustrating a method of forming a bit line according to the present invention.

Explanation of symbols for main parts of the drawings

200. Semiconductor substrate 202. Device isolation film

203. Impurity region 204. Gate insulating film

206. Gate 208. Buffer Oxide

210. Insulation spacer 220. Conductive plug

222, 232. Insulating film 230. Silicon nitride film

234. Contact hole 236. Metal film for bit line

The bit line forming method of the present invention for achieving the above object comprises the steps of sequentially forming a buffer oxide film on the gate and the gate side on the semiconductor substrate, forming a source / drain on the lower substrate on both sides of the gate including the buffer oxide film; Forming a first insulating film having a first opening that exposes the source on the substrate having the structure, forming a conductive plug covering the first opening, and etching a portion of the first insulating film and the buffer oxide film; And forming a silicon nitride film covering the resultant, the silicon nitride film covering the etched portion of the buffer oxide film, and forming the second insulating film having a second opening for exposing the conductive plug on the silicon nitride film. Forming a covering bit line.

The silicon nitride film is preferably formed in a thickness of 10 to 1000 GPa.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating a method of forming a bit line according to the present invention.

In the bit line forming method of the present invention, as shown in FIG. 2A, first, a shallow trench is formed in an isolation region (not shown) of a semiconductor substrate 200 on which a semiconductor well (not shown) is formed. Device isolation layer 202 is formed using the < RTI ID = 0.0 >

Subsequently, the gate 204 and the impurity regions 203 such as the source / drain are sequentially formed on the substrate 200 including the device isolation layer 202.

In this case, the gate 204 has a structure in which a buffer oxide film 208 and an insulating spacer 210 are sequentially arranged on side surfaces thereof, and a silicon nitride film 206 which is a cap oxide film is arranged on an upper surface thereof.

Next, a first insulating film 222 is deposited on a substrate including the gate 206 having the structure, and then the first insulating film 222 is etched by a photolithography process to expose the impurity region 203. A first contact hole (not shown) is formed, and a conductive plug 220 filling the first contact hole is formed. In this case, the buffer oxide layer 208 is partially exposed at the upper end of the gate 206.

Thereafter, as shown in FIG. 2B, the first insulating layer 222 is partially etched by wet etching. In this case, during the wet etching process, not only the first insulating layer 222 but also the buffer oxide layer 208 may be partially removed.

Subsequently, as illustrated in FIG. 2C, a silicon nitride film 230 having a thickness of 10 to 1000 Å is deposited on the entire surface of the resultant product. In this case, the silicon nitride film 230 covers a portion where the buffer oxide film 208 is removed.

Next, after depositing the second insulating film 232 on the silicon nitride film 230, as shown in Figure 2d, the second insulating film is selectively etched to remove the portion of the impurity region (source of the second) A second contact hole 234 exposing is formed.

Thereafter, after depositing a bit line forming metal film on the second insulating layer including the second contact hole 234, the metal film is selectively etched to form a bit line (not shown).

As described above, in the method of the present invention, when the silicon nitride film covers the buffer oxide film of the gate so that the gate and the bit line are insulated from each other, the contact hole for the bit line for connecting the source and the bit line of the cell transistor is formed. The bridge phenomenon between the gate and the bit line due to the damage of the buffer oxide layer of the gate can be prevented.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (2)

Sequentially forming a gate and a buffer oxide film on the gate side of the semiconductor substrate; Forming a source / drain on both lower substrates of the gate including the buffer oxide layer; Forming a first insulating film having a first opening that exposes the source on the substrate having the structure; Forming a conductive plug covering the first opening; Etching a portion of the first insulating layer and the buffer oxide layer; Forming a silicon nitride film covering the resultant material, the silicon nitride film covering an etched portion of the buffer oxide film; Forming the second insulating film having a second opening on the silicon nitride film to expose the conductive plug; And forming a bit line covering the second opening. 2. The method as claimed in claim 1, wherein the silicon nitride film is formed to a thickness of 10 to 1000 kHz.