KR20040059938A - Method for fabricating semiconductor device with analog capacitor - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device with an analog capacitor is provided to be capable of preventing the generation of residues of the second polysilicon layer due to the step of a lower electrode. CONSTITUTION: A gate oxide layer(12) is formed on a substrate with a field oxide layer(11). A trench is formed by dry-etching of the field oxide layer. A lower electrode(15a) is formed by filling the first polysilicon layer in the trench. A dielectric film(16) is formed on the lower electrode. The second polysilicon layer is formed on the entire surface of the resultant structure. By patterning the second polysilicon layer, an upper electrode(17A) is formed on the dielectric film and a gate electrode(17B) is formed on the gate oxide layer.

Description

Method for fabricating a semiconductor device with an analog capacitor {Method for fabricating semiconductor device with analog capacitor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having an analog capacitor using dielectric constant of an insulator between polysilicon layers.

A method of manufacturing an analog capacitor and a MOS transistor according to the prior art will be described with reference to FIGS. 1A to 1D.

First, as shown in FIG. 1A, a field oxide film 1 and a gate oxide film 2 for insulation between semiconductor devices are formed in a predetermined region on a semiconductor substrate (not shown), and then used as a lower electrode of an analog capacitor. The first polysilicon 3 is deposited on the field oxide film 1 and the gate oxide film 2 and doped with impurities. Subsequently, an oxide film / nitride film 4 to be used as a dielectric material is deposited on the first polysilicon layer 3 by low pressure chemical vapor deposition (LPCVD), and then shown in FIG. 1B by a selective dry etching method using a predetermined mask (5). As described above, the analog capacitor lower electrode 3A and the dielectric film 4A are formed on the field oxide film 1. Next, the mask 5 is removed.

Subsequently, as shown in FIG. 1C, the second polysilicon 6 to be used as the upper electrode of the analog capacitor and the gate electrode of the MOS transistor is deposited and doped on the entire surface of the substrate, and then a dry etching method using a predetermined mask 7 is performed. The second polysilicon layer 6 is etched to form the upper electrode 6A of the analog capacitor and the gate electrode B of the MOS transistor as shown in FIG. 1D. At this time, the oxide film / nitride film 4A remains at the lower end of the upper electrode 6A of the analog capacitor formed of the second polysilicon layer 6, and the remaining part is removed by dry etching.

The source and the drain of the MOS transistor are formed by an ion implantation method, and then a TEOS film and a BPSG film are formed by chemical vapor deposition to insulate the metal wiring, which is not shown in the drawings. Subsequently, contact holes are formed to connect the metal wires, the source electrodes, the drain electrodes, and the lower electrodes and the upper electrodes of the analog capacitor, and are connected by metal wires.

In the conventional analog capacitor forming method as described above, after forming the lower electrode 3A of the capacitor using the first polysilicon layer, the gate electrode 6B and the capacitor upper electrode 6A using the second polysilicon layer are formed. do. At this time, the lower electrode 3A of the capacitor formed of the first polysilicon, the gate electrode 6B formed of the second polysilicon, and the upper electrode 6A of the capacitor further increase the step difference of the semiconductor device together with the field oxide film 1. Let's do it. Sidewalls of the lower electrode 3A of the analog capacitor formed of the first polysilicon and the gate electrode 6B formed of the second polysilicon during the second polysilicon etching using the mask after the deposition of the second polysilicon due to the step generated as described above Second polysilicon residues are generated due to the lack of selectivity and the step of the dry etching equipment, which causes a short circuit between the gate polysilicon.

In addition, damage to the gate oxide film is inevitably caused during excessive dry etching to remove the second polysilicon residue, and junction leakage occurs through the damaged gate oxide film.

The present invention is to solve the problems of the prior art, the manufacturing of a semiconductor device having an analog capacitor that can fundamentally solve the generation of the second polysilicon residues due to the step of the capacitor lower electrode formed of the first polysilicon The purpose is to provide a method.

1A to 1D are cross-sectional views illustrating a method of manufacturing an analog capacitor according to the prior art;

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device having an analog capacitor according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11 field oxide film 12 gate oxide film

14 trench 15a lower electrode

16: oxide film / nitride film 17B: lower electrode

17A: gate electrode

The semiconductor device manufacturing method of the present invention for achieving the above object is to form a field oxide film and a gate oxide film in a predetermined region on the semiconductor substrate, forming a trench in the field oxide film by dry etching, the trench formed in the field oxide film Embedding the first polysilicon in the capacitor to form a lower electrode of the capacitor, forming a capacitor dielectric film on the capacitor lower electrode, forming a second polysilicon on the entire surface including the dielectric film, and the second polysilicon And forming a gate electrode on the gate oxide layer by patterning a predetermined pattern, and simultaneously forming an upper electrode of the capacitor on the capacitor dielectric layer, wherein the trench has a size of 0.5 smaller than that of the predetermined capacitor lower electrode. It is characterized by forming large -1.0 micrometer.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device having an analog capacitor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, a field oxide film 11 and a gate oxide film 12 are formed in a predetermined region on a semiconductor substrate (not shown) to insulate the semiconductor devices, and then a step between the gate electrode and the capacitor electrode is formed. The trench structure 14 is formed in the field oxide layer 11 by dry etching using the capacitor lower electrode forming mask 13 to reduce the thickness. At this time, the size of the trench 14 is formed to be 0.5 to 1.0㎛ larger than the predetermined capacitor lower electrode. That is, it is generally formed larger than the capacitor lower electrode formed by deposition and etching.

As shown in FIG. 2B, after depositing the first polysilicon 15, the lower electrode 15a of the analog capacitor deposited on the trench 14 by dry etching using a predetermined mask as shown in FIG. 2C. The remaining portions except for the first polysilicon 15 to be used are removed. In this case, the mask to be applied is about 0.5 to 1.0 μm larger than the mask for forming the upper electrode of the analog capacitor, and the lower electrode 15a of the capacitor has a flat shape embedded in the trench 14.

Subsequently, a double layer of an oxide film and a nitride film to be used as a dielectric of an analog capacitor, that is, an oxide film / nitride film 16, is deposited to a thickness of 50 to 300 Å, and portions except the portions formed on the capacitor lower electrode 15a are removed by dry etching.

Next, as shown in FIG. 2D, a second polysilicon 17 to be used as the gate electrode and the capacitor upper electrode is deposited and doped by ion implantation.

Subsequently, as shown in FIG. 2E, the second polysilicon 17 is patterned to form a gate electrode 17B on the gate oxide film 12, and a capacitor upper electrode 17A is formed on the oxide film / nitride film 16. . Thereafter, a source and a drain are formed using an ion implantation process to complete the transistor.

Next, as shown in FIG. 2F, the TEOS film 18 is deposited on the gate electrode 17B to a thickness of 700 to 300 kPa at a temperature of 650 to 750 ° C by chemical vapor deposition (CVD) to prevent the transistor from changing the threshold voltage.

Subsequently, although not shown, a contact hole for electrically connecting the lower electrode and the upper electrode of the metal wiring, the source, the drain, and the analog capacitor is formed, and then connected by the metal wiring.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, by fundamentally preventing the generation of the second polysilicon residue due to the step of the capacitor lower electrode formed of the first polysilicon to prevent the generation of the bridge of the first polysilicon due to the second polysilicon residue There is an effect that can be prevented.

In addition, since the trench is formed in the field oxide film by 0.5 to 1.0 µm larger than the capacitor lower electrode, the lower electrode is formed in the field oxide film, thereby reducing the step difference problem of the capacitor lower electrode.

Claims (6)

Forming a field oxide film and a gate oxide film in a predetermined region on the semiconductor substrate; Forming a trench in the field oxide layer by dry etching; Filling the first polysilicon in the trench formed in the field oxide layer to form a lower electrode of the capacitor; Forming a capacitor dielectric layer on the capacitor lower electrode; Forming a second polysilicon on the entire surface including the dielectric film; And Patterning the second polysilicon in a predetermined pattern to form a gate electrode on the gate oxide layer and simultaneously forming an upper electrode of the capacitor on the capacitor dielectric layer Method for manufacturing a semiconductor device comprising a. The method of claim 1, The trench has a size of 0.5 to 1.0 [mu] m larger than a predetermined capacitor lower electrode. The method of claim 1, And the capacitor dielectric film is formed of a double film of an oxide film and a nitride film. The method of claim 3, A double film of the oxide film and the nitride film is formed to a thickness of 50 ~ 300Å. The method of claim 1, The method of manufacturing a semiconductor device, characterized in that for forming the trench using a mask for forming a lower electrode. The method of claim 1, After forming the capacitor upper electrode and the gate electrode, And forming a TEOS film on the gate electrode to a thickness of 700 to 1300 Å at a temperature of 650 to 750 DEG C by chemical vapor deposition.