KR20010077235A - Method of fabricating plug - Google Patents

Method of fabricating plug Download PDF

Info

Publication number
KR20010077235A
KR20010077235A KR1020000004897A KR20000004897A KR20010077235A KR 20010077235 A KR20010077235 A KR 20010077235A KR 1020000004897 A KR1020000004897 A KR 1020000004897A KR 20000004897 A KR20000004897 A KR 20000004897A KR 20010077235 A KR20010077235 A KR 20010077235A
Authority
KR
South Korea
Prior art keywords
contact hole
insulating film
forming
plug
semiconductor substrate
Prior art date
Application number
KR1020000004897A
Other languages
Korean (ko)
Inventor
서광동
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1020000004897A priority Critical patent/KR20010077235A/en
Publication of KR20010077235A publication Critical patent/KR20010077235A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for manufacturing a plug is provided to prevent adjacent contact holes from being connected to each other, by performing a process for filling the contact hole formed on an insulating sidewall after the insulating sidewall is formed on a sidewall of the contact hole exposing an impurity region. CONSTITUTION: A gate electrode(204) is formed on a semiconductor substrate(200) by interposing a gate insulation layer. A source/drain impurity region is formed on the semiconductor substrate by using the gate electrode as a mask. An interlayer dielectric(208a) having a contact hole covering the gate electrode and exposing the impurity region is formed on the semiconductor substrate. An insulating sidewall(230a) is so formed that the insulating sidewall remains on a side surface of the contact hole. A plug(220a) filling the contact hole including the insulating sidewall is formed.

Description

플러그 형성방법{Method of fabricating plug}Method of fabricating plug

본 발명은 콘택홀(contact hole)을 채우는 플러그(plug) 형성방법에 관한 것으로, 특히, 반도체소자가 고집적화되어 게이트전극 간의 간격이 좁아진 경우, 콘택홀 내의 갭필(gap fill)불량에 의한 보이드 발생을 통해서 이웃한 콘택홀끼리 연결되는 현상을 방지할 수 있는 플러그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a plug to fill a contact hole. In particular, when semiconductor devices are highly integrated and the gap between gate electrodes is narrowed, void generation due to a gap fill defect in the contact hole is prevented. The present invention relates to a plug forming method capable of preventing a phenomenon in which neighboring contact holes are connected to each other.

반도체소자가 고집적화됨에 따라, 게이트전극 간의 간격도 매우 좁아지게 된다. 따라서, 게이트전극 사이에 기판 하부의 소오스/드레인인 불순물영역을 노출시키는 콘택홀 형성 및 상기 불순물영역과 연결되도록 콘택홀을 채우는 플러그 형성 과정에서, 콘택홀 내에 우수한 스텝커버리지를 갖는 물질을 이용하여 갭필시키는 기술이 중요하다.As semiconductor devices are highly integrated, the spacing between gate electrodes also becomes very narrow. Accordingly, in the process of forming a contact hole exposing source / drain impurity regions under the substrate between the gate electrodes and forming a plug filling the contact hole to be connected to the impurity region, a gap fill is formed using a material having excellent step coverage in the contact hole. The skill of letting is important.

도 1a 내지 도 1e는 종래기술에 따른 플러그 형성 과정을 보인 공정단면도이다.1A to 1E are cross-sectional views illustrating a plug forming process according to the related art.

도 1a 와 같이, 도면번호 100은 반도체기판(substrate)으로, 웰(well) 및 필드산화막(field oxide layer)가 형성되어져 있다.As shown in Fig. 1A, reference numeral 100 denotes a semiconductor substrate, in which a well and a field oxide layer are formed.

상기 반도체기판(100) 상에 산화실리콘, 다결정실리콘 및 질화실리콘을 순차적을 증착한 후, 소정부위 식각하여 각각의 게이트절연막(102), 게이트전극(104) 및 캡절연막(106)을 형성한다.Silicon oxide, polycrystalline silicon, and silicon nitride are sequentially deposited on the semiconductor substrate 100, and then predetermined portions are etched to form respective gate insulating films 102, gate electrodes 104, and cap insulating films 106.

이 후, 반도체기판(100) 상에 게이트전극(104)을 포함한 캡절연막(106)을 마스크로 하여 불순물을 주입시킴으로써, 소오스/드레인인 불순물영역(101)이 형성된다.Thereafter, an impurity is implanted on the semiconductor substrate 100 using the cap insulating film 106 including the gate electrode 104 as a mask, thereby forming a source / drain impurity region 101.

도 1b와 같이, 반도체기판(100)상에 게이트전극(104)을 포함하여 캡절연막(106)을 덮도록 층간절연막(108)을 형성한다.As shown in FIG. 1B, the interlayer insulating film 108 is formed on the semiconductor substrate 100 to cover the cap insulating film 106 by including the gate electrode 104.

이 후, 층간절연막(108) 상에 감광막(photoresist)을 도포한 후, 게이트전극(104)과 대응되는 부위를 덮고 불순물영역(101)과 대응되는 부위를 노출시키도록 패턴 식각하여 감광막패턴(110)을 형성한다.Thereafter, a photoresist is applied on the interlayer insulating film 108, and then a pattern is etched to cover a portion corresponding to the gate electrode 104 and to expose a portion corresponding to the impurity region 101. ).

도 1c와 같이, 감광막패턴을 마스크로 하여 층간절연막을 식각함으로써 콘택홀(c1)이 형성된다.As illustrated in FIG. 1C, a contact hole c1 is formed by etching the interlayer insulating film using the photosensitive film pattern as a mask.

콘택홀(c1)은 불순물영역(101)을 노출시키며, 이 후의 공정에서 플러그를 통해 불순물영역(101)과 캐패시터 등을 전기적으로 연결시키어 주는 통로가 된다.The contact hole c1 exposes the impurity region 101 and serves as a path for electrically connecting the impurity region 101 and a capacitor through a plug in a subsequent process.

이 때, 기판(100) 상에 식각되어져 잔류된 층간절연막을 도면번호 108a로 표시하였다.At this time, the interlayer insulating film etched and remaining on the substrate 100 is indicated by reference numeral 108a.

이 후, 감광막패턴을 제거한 후, 세정공정을 진행시킨다.Thereafter, the photosensitive film pattern is removed, and then the washing step is performed.

도 1d와 같이, 층간절연막(108a) 상에 콘택홀(c1)을 덮어 불순물영역(101)과 연결되도록 다결정실리콘을 증착하여 도전막(120)을 형성한다.As illustrated in FIG. 1D, the conductive film 120 is formed by depositing polysilicon to cover the contact hole c1 on the interlayer insulating film 108a so as to be connected to the impurity region 101.

도 1e와 같이, 층간절연막(108a)이 노출되는 시점까지 도전막을 식각한다.As illustrated in FIG. 1E, the conductive film is etched until the interlayer insulating film 108a is exposed.

이 결과, 콘택홀(c1)을 채우는 종래기술에 따른 플러그(120a)가 형성된다.As a result, a plug 120a according to the related art for filling the contact hole c1 is formed.

이 플러그(120a)는 기판 하부의 불순물영역(101)과 연결된다.The plug 120a is connected to the impurity region 101 under the substrate.

그러나, 종래의 기술에서는 반도체소자가 고집적화되어 게이트전극 간의 간격이 좁아지게 됨에 따라, 게이트전극을 덮는 층간절연막 형성 시에 게이트전극 사이 공간을 완전히 채우지 못하여 이 부분에 보이드가 형성되었다.However, in the related art, since semiconductor devices are highly integrated and the gap between the gate electrodes is narrowed, voids are formed in this part because the space between the gate electrodes is not completely filled when the interlayer insulating film covering the gate electrodes is formed.

따라서, 보이드가 발생된 층간절연막 상에 콘택홀 형성하고, 이 콘택홀을 채우는 플러그 형성용 도전막 증착 및 전세정 시, 이웃한 콘택홀끼리 보이드를 통해 연결되어 플러그 쇼트를 유발하게 된 문제점이 있었다.Therefore, when a contact hole is formed on an interlayer insulating film in which voids are generated, and a plug forming conductive film for filling the contact hole is deposited and pre-cleaned, neighboring contact holes are connected through a void to cause a plug short. .

상기의 문제점을 해결하고자, 본 발명의 목적은 이웃한 콘택홀끼리 연결되는 것을 방지할 수 있는 플러그 형성방법을 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to provide a plug forming method that can prevent the adjacent contact holes are connected.

상기 목적을 달성하고자, 본 발명의 플러그 형성방법은 본 발명의 플러그 형성방법은 반도체기판 상에 게이트절연막을 개재시키어 게이트전극을 형성하는 공정과, 반도체기판 상에 게이트전극을 마스크로 소오스/드레인인 불순물영역을 형성하는 공정과, 반도체기판 상에 게이트전극을 덮고 불순물영역을 노출시키는 콘택홀을 갖도록 층간절연막을 형성하는 공정과, 콘택홀의 측면에 잔류되도록 절연측벽을 형성하는 공정과, 절연측벽을 포함한 콘택홀을 채우도록 플러그를 형성하는 공정을 구비한 것이 특징이다.In order to achieve the above object, the plug forming method of the present invention is a plug forming method of the present invention comprising the steps of forming a gate electrode by interposing a gate insulating film on a semiconductor substrate, and the source / drain in the gate electrode as a mask on the semiconductor substrate as a mask Forming an impurity region, forming an interlayer insulating film so as to have a contact hole covering the gate electrode and exposing the impurity region on the semiconductor substrate, forming an insulating side wall so as to remain on the side of the contact hole, and And a step of forming a plug so as to fill the contact hole included therein.

도 1a 내지 도 1e는 종래기술에 따른 플러그 형성 과정을 보인 공정단면도이고,1a to 1e is a cross-sectional view showing a process for forming a plug according to the prior art,

도 2a 내지 도 2f는 본 발명에 따른 플러그 형성 과정을 보인 공정단면도이다.2A to 2F are cross-sectional views illustrating a process of forming a plug according to the present invention.

*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100, 200. 반도체기판 101, 201. 불순물영역100, 200. Semiconductor substrate 101, 201. Impurity region

102, 202. 게이트절연막 104, 204. 게이트전극102, 202. Gate insulating film 104, 204. Gate electrode

106, 206. 캡절연막 c1, c2. 콘택홀106, 206. Cap insulation films c1 and c2. Contact hole

120a, 220a. 플러그 230a. 절연측벽120a, 220a. Plug 230a. Insulation side wall

108, 108a, 208, 208a. 층간절연막108, 108a, 208, 208a. Interlayer insulation film

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

반도체소자가 고집적화됨에 따라, 게이트전극 간의 간격이 좁아진 경우, 본 발명에서는 먼저, 기판 하부의 불순물영역을 노출시키는 콘택홀 측면에 절연측벽을 형성한 후, 절연측벽이 형성된 콘택홀을 채우는 플러그 형성 공정을 진행시킴으로써, 이웃한 콘택홀끼리 연결되는 현상을 방지하려는 것이다.As the semiconductor device is highly integrated, when the gap between the gate electrodes is narrowed, in the present invention, first, an insulating side wall is formed on the side of the contact hole exposing the impurity region under the substrate, and then a plug forming process of filling the contact hole having the insulating side wall is formed. By proceeding to prevent the phenomenon that the adjacent contact holes are connected.

도 2a 내지 도 2f는 본 발명에 따른 플러그 형성 과정을 보인 공정단면도이다.2A to 2F are cross-sectional views illustrating a process of forming a plug according to the present invention.

도 2a 와 같이, 반도체기판(200)에는 도면에 도시되지 않았지만, 웰 및 필드산화막이 형성되어져 있다.As shown in FIG. 2A, a well and a field oxide film are formed on the semiconductor substrate 200, although not shown in the drawing.

상기 반도체기판(200) 상에 산화실리콘, 다결정실리콘 및 질화실리콘을 순차적으로 증착한 후, 소정부위 식각하여 게이트절연막(202)을 개재시키어 게이트전극(204) 및 캡절연막(206)을 형성한다.After sequentially depositing silicon oxide, polycrystalline silicon, and silicon nitride on the semiconductor substrate 200, a predetermined portion is etched to form a gate electrode 204 and a cap insulating film 206 through the gate insulating film 202.

이 후, 반도체기판(200) 상에 캡절연막(206)을 마스크로 하여 불순물을 주입함으로써, 게이트전극(204) 양측 하부에는 소오스/드레인인 불순물영역(201)이 형성된다.Thereafter, impurities are implanted onto the semiconductor substrate 200 using the cap insulating film 206 as a mask, so that source / drain impurity regions 201 are formed under both sides of the gate electrode 204.

상기에서, 불순물영역(201) 형성 시, 질화실리콘 성분인 캡절연막(206)은 불순물블로킹 마스크로 사용된다.In the above, when the impurity region 201 is formed, the cap insulating film 206 which is a silicon nitride component is used as an impurity blocking mask.

도 2b와 같이, 반도체기판(200) 상에 게이트전극(204)을 포함한 캡절연막(206)을 덮도록 층간절연막(208)을 형성한다.As shown in FIG. 2B, an interlayer insulating film 208 is formed on the semiconductor substrate 200 to cover the cap insulating film 206 including the gate electrode 204.

그리고 층간절연막(208) 상에 감광막을 도포한 후, 게이트전극(204)과 대응되는 부위를 덮고 불순물영역(201)과 대응되는 부위를 노출시키도록 패턴 식각하여 감광막패턴(210)을 형성한다.After the photoresist film is applied on the interlayer insulating film 208, the photoresist film pattern 210 is formed by pattern etching to cover a portion corresponding to the gate electrode 204 and to expose a portion corresponding to the impurity region 201.

도 2c와 같이, 감광막패턴을 마스크로 하여 층간절연막을 식각함으로써, 불순물영역(201)을 노출시키는 콘택홀(c2)이 형성된다.As shown in FIG. 2C, a contact hole c2 exposing the impurity region 201 is formed by etching the interlayer insulating film using the photosensitive film pattern as a mask.

식각 공정이 진행된 후, 기판(200) 상에 잔류된 층간절연막은 최초의 층간절연막과 구분하도록 도면번호 208a로 표시된다.After the etching process, the interlayer insulating film remaining on the substrate 200 is indicated by reference numeral 208a to distinguish it from the first interlayer insulating film.

이 후, 감광막패턴을 제거한다.Thereafter, the photosensitive film pattern is removed.

도 2d와 같이, 층간절연막(208a) 상에 콘택홀(c2)의 바닥면 및 측면을 모두 덮도록 절연막(230)을 형성한다.As illustrated in FIG. 2D, an insulating film 230 is formed on the interlayer insulating film 208a to cover both the bottom surface and the side surface of the contact hole c2.

이 절연막으로는 저압상태에서 갭필능력이 우수한 USG(Undoped Silicate Glass)를 증착하여 얻을 수 있다.This insulating film can be obtained by depositing USG (Undoped Silicate Glass) having excellent gap fill capability at low pressure.

도 2e와 같이, 층간절연막(208a) 표면 및 콘택홀(c2)의 바닥면이 노출되는 시점되는 시점까지 절연막을 에치백한다.As shown in FIG. 2E, the insulating film is etched back to the point where the surface of the interlayer insulating film 208a and the bottom surface of the contact hole c2 are exposed.

에치백 결과, 절연막은 콘택홀(c2)의 측면에만 잔류된다.As a result of the etch back, the insulating film remains only on the side surface of the contact hole c2.

이하에서, 식각되어지고 잔류된 절연막을 절연측벽(230a)이라 칭한다.Hereinafter, the etched and remaining insulating film is referred to as insulating side wall 230a.

이 후, 전세정 공정을 진행시킨 후, 층간절연막(208a) 상에 절연측벽(230a)을 포함한 콘택홀(c2)을 채우도록 다결정실리콘을 증착하여 도전막(220)을 형성한다.Thereafter, after the pre-cleaning process is performed, polysilicon is deposited to fill the contact hole c2 including the insulating side wall 230a on the interlayer insulating film 208a to form the conductive film 220.

도 2f와 같이, 층간절연막(208a)이 노출되는 시점까지 도전막을 식각한다.As shown in FIG. 2F, the conductive film is etched until the interlayer insulating film 208a is exposed.

이 때, 식각되어진 후 잔류된 도전막은 절연측벽(230a)이 포함된 콘택홀(c2)을 채우는 플러그(220a)가 된다.At this time, the conductive film remaining after etching becomes a plug 220a filling the contact hole c2 including the insulating side wall 230a.

상술한 바와 같이, 본 발명에서는 반도체소자가 고집적화됨에 따라, 게이트전극 간의 간격이 좁아진 경우, 기판 하부의 불순물영역을 노출시키는 콘택홀 측면에 절연측벽을 형성한 후, 절연측벽이 형성된 콘택홀을 채우는 플러그 형성 공정을 진행시킴으로써, 이웃한 콘택홀끼리 연결되는 현상을 방지할 수 있다.As described above, in the present invention, as the semiconductor device is highly integrated, when the gap between the gate electrodes is narrowed, the insulating side wall is formed on the side of the contact hole exposing the impurity region under the substrate, and then the contact hole in which the insulating side wall is formed is filled. By advancing a plug formation process, the phenomenon that adjacent contact holes are connected can be prevented.

따라서, 본 발명에서는 콘택홀 내의 갭필 불량에 의한 보이드 발생을 통해서 이웃한 콘택홀끼리 연결되는 현상을 방지할 수 있다.Therefore, in the present invention, it is possible to prevent a phenomenon in which neighboring contact holes are connected through void generation due to a gap fill defect in the contact hole.

Claims (4)

반도체기판 상에 게이트절연막을 개재시키어 게이트전극을 형성하는 공정과,Forming a gate electrode by interposing a gate insulating film on the semiconductor substrate; 상기 반도체기판 상에 상기 게이트전극을 마스크로 소오스/드레인인 불순물영역을 형성하는 공정과,Forming a source / drain impurity region on the semiconductor substrate using the gate electrode as a mask; 상기 반도체기판 상에 상기 게이트전극을 덮고 상기 불순물영역을 노출시키는 콘택홀을 갖도록 층간절연막을 형성하는 공정과,Forming an interlayer insulating film on the semiconductor substrate to have a contact hole covering the gate electrode and exposing the impurity region; 상기 콘택홀의 측면에 잔류되도록 절연측벽을 형성하는 공정과,Forming an insulating side wall so as to remain on the side of the contact hole; 상기 절연측벽을 포함한 콘택홀을 채우도록 플러그를 형성하는 공정을 구비한 플러그 형성방법.And a plug forming step of filling the contact hole including the insulating side wall. 청구항 1에 있어서,The method according to claim 1, 상기 절연측벽의 재료로는 갭필력이 우수한 USG(Undoped Silicate Glass)가 이용된 것이 특징인 플러그 형성방법.The material of the insulating side wall is a plug forming method characterized in that the use of USG (Undoped Silicate Glass) excellent in the gap peel force. 청구항 1에 있어서,The method according to claim 1, 상기 절연측벽 형성은The insulating side wall is formed 상기 층간절연막 상에 상기 콘택홀의 바닥면과 측면을 모두 덮도록 절연막을 형성하는 제 1공정과,Forming an insulating film on the interlayer insulating film so as to cover both the bottom and side surfaces of the contact hole; 상기 층간절연막 표면과 상기 콘택홀의 바닥면이 노출되는 시점까지 상기 절연막을식각하는 제 2공정을 포함하여 이루어진 것이 특징인 플러그 형성방법.And forming a second step of etching the insulating film until the surface of the interlayer insulating film and the bottom surface of the contact hole are exposed. 청구항 1에 있어서,The method according to claim 1, 상기 플러그 형성은The plug formation 상기 층간절연막 상에 상기 상기 절연측벽을 포함한 콘택홀을 채우도록 도전막을 형성하는 제 1공정과,Forming a conductive film on the interlayer insulating film so as to fill the contact hole including the insulating side wall; 상기 층간절연막이 노출되는 시점까지 상기 도전막을 식각하는 제 2공정을 포함하여 이루어진 것이 특징인 플러그 형성방법.And a second step of etching the conductive film until a time point at which the interlayer insulating film is exposed.
KR1020000004897A 2000-02-01 2000-02-01 Method of fabricating plug KR20010077235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000004897A KR20010077235A (en) 2000-02-01 2000-02-01 Method of fabricating plug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000004897A KR20010077235A (en) 2000-02-01 2000-02-01 Method of fabricating plug

Publications (1)

Publication Number Publication Date
KR20010077235A true KR20010077235A (en) 2001-08-17

Family

ID=19643400

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000004897A KR20010077235A (en) 2000-02-01 2000-02-01 Method of fabricating plug

Country Status (1)

Country Link
KR (1) KR20010077235A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101128893B1 (en) * 2010-07-15 2012-03-27 주식회사 하이닉스반도체 Method for Manufacturing Semiconductor Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101128893B1 (en) * 2010-07-15 2012-03-27 주식회사 하이닉스반도체 Method for Manufacturing Semiconductor Device

Similar Documents

Publication Publication Date Title
KR100264773B1 (en) Method of manufacturing a semiconductor device having self aligned contact hole
KR20010077235A (en) Method of fabricating plug
KR100289661B1 (en) Manufacturing method of semiconductor device
KR100694996B1 (en) Method for manufacturing capacitor in semiconductor device
KR100506050B1 (en) Contact formation method of semiconductor device
KR100436063B1 (en) Method of forming contact hole of semiconductor device using spacer made of undoped polysilicon layer
KR100198637B1 (en) Fabricating method of semiconductor device
KR100226753B1 (en) Forming method for metallization of semiconductor device
KR100258202B1 (en) Method for manufacturing semiconductor device
KR100218735B1 (en) Forming method for contact hole of semiconductor device
KR0147770B1 (en) Manufacture method of semiconductor device
KR100280528B1 (en) Internal wiring formation method of semiconductor device
KR20000027911A (en) Method of forming contact of semiconductor device
KR100253326B1 (en) Method for semiconductor device
KR100358568B1 (en) A method for fabricating of a semiconductor device
KR20010056884A (en) Method for forming bit line contact of semiconductor
KR100386625B1 (en) method for manufacturing of semiconductor device
KR100230735B1 (en) Process for fabricating semiconductor device
KR20040057609A (en) Method of manufacturing semiconductor device
KR20000050330A (en) Method for forming contact of semiconductor device
KR20000041077A (en) Method for forming a wire of semiconductor devices
KR20060109053A (en) Method of manufacturing semiconductor device
KR20010068951A (en) Method of forming memory contact hole
KR20000051805A (en) Manufacturing method for semiconductor memory
KR20000038332A (en) Method of fabricating semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application