KR20000050330A - Method for forming contact of semiconductor device - Google Patents

Method for forming contact of semiconductor device Download PDF

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Publication number
KR20000050330A
KR20000050330A KR1019990000112A KR19990000112A KR20000050330A KR 20000050330 A KR20000050330 A KR 20000050330A KR 1019990000112 A KR1019990000112 A KR 1019990000112A KR 19990000112 A KR19990000112 A KR 19990000112A KR 20000050330 A KR20000050330 A KR 20000050330A
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KR
South Korea
Prior art keywords
contact
contact hole
film
insulating film
mask pattern
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KR1019990000112A
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Korean (ko)
Inventor
김병철
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윤종용
삼성전자 주식회사
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Priority to KR1019990000112A priority Critical patent/KR20000050330A/en
Publication of KR20000050330A publication Critical patent/KR20000050330A/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A contact forming method of a semiconductor device is to prevent a contact fail generated as a void is exposed to an upper surface of a substrate. CONSTITUTION: A first insulating film(110), a second insulating film(112), and a third insulating film(114) are deposited in this sequence on a semiconductor substrate(100) with a lower conductive region(105,108) formed thereon. A mask pattern is then formed on the third insulating film to form a contact hole. A first contact hole is then formed by etching the third insulating film and the second insulating film by using the mask pattern. The mask pattern is partially etched in its thickness. An expanded first contact hole(118a) is formed by etching the third insulating film by using the mask pattern. A second contact hole(120a,120b) are formed by etching the first insulating film by using the second insulating film as a mask to expose the lower conductive region. After removing the mask pattern, a first metal film is disposed on the entire surface of the substrate to fill the second contact holes and the expanded first contact hole. A contact plug(124a,124b) are then formed by partially removing the first metal film. A metal line(126) is formed to be electrically connected to the contact plugs by depositing and patterning a second metal film overall surface of the substrate.

Description

반도체 장치의 콘택 형성 방법{METHOD FOR FORMING CONTACT OF SEMICONDUCTOR DEVICE}TECHNICAL FOR FORMING CONTACT OF SEMICONDUCTOR DEVICE

본 발명은 반도체 장치의 제조 방법에 관한 것으로, 좀 더 구체적으로는 반도체 장치의 콘택 형성 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact of a semiconductor device.

반도체 장치의 콘택 형성에 있어서 특히, DRAM 소자의 콘택 형성에 있어서 콘택홀의 종횡비(aspect ratio)가 증가함에 따라 콘택홀을 금속막으로 채우는 공정이 어려워지고 있다. 이에 따라, 콘택홀을 채우는 금속막을 종래의 알루미늄(Al)막 보다 스텝 커버리지(step coverage)가 우수한 텅스텐(W)막으로 대체하고 있다.In forming a contact of a semiconductor device, in particular, in forming a contact of a DRAM device, a process of filling a contact hole with a metal film becomes difficult as the aspect ratio of the contact hole increases. As a result, the metal film filling the contact hole is replaced with a tungsten (W) film having better step coverage than the conventional aluminum (Al) film.

도 1a 내지 도 1e는 종래의 반도체 장치의 콘택 형성 방법의 공정들을 순차적으로 보여주는 흐름도이다.1A through 1E are flowcharts sequentially illustrating processes of a method for forming a contact of a conventional semiconductor device.

도 1a를 참조하면, 종래의 반도체 장치의 콘택 형성 방법은 먼저, 반도체 기판(2) 상에 활성 영역(active region)과 비활성 영역(inactive region)을 정의하기 위해 소자 격리(device isolation)로서, 트렌치 격리(trench isolation)(4)가 형성된다.Referring to FIG. 1A, a method of forming a contact of a conventional semiconductor device is first formed as a device isolation to define an active region and an inactive region on a semiconductor substrate 2. A trench isolation 4 is formed.

상기 활성 영역 상에 트랜지스터(transistor)(6)가 형성된다. 상기 트랜지스터(6)는 게이트 전극(gate electrode)(7), 게이트 마스크(gate mask)(8), 게이트 스페이서(gate spacer)(9), 그리고 소오스/드레인 영역(source/drain region)(10)을 포함한다.A transistor 6 is formed on the active region. The transistor 6 includes a gate electrode 7, a gate mask 8, a gate spacer 9, and a source / drain region 10. It includes.

상기 트랜지스터(6)를 포함하여 반도체 기판(2) 전면에 절연막(12)이 증착 된다.The insulating layer 12 is deposited on the entire surface of the semiconductor substrate 2 including the transistor 6.

도 1b에 있어서, 상기 절연막(12) 상에 콘택홀 형성용 포토레지스트 패턴(photoresist pattern)(14)이 형성된 후, 상기 포토레지스트 패턴(14)을 마스크로 사용하여 상기 절연막(12)이 식각 되어 콘택홀(16a, 16b)이 형성된다.In FIG. 1B, after the photoresist pattern 14 for forming a contact hole is formed on the insulating layer 12, the insulating layer 12 is etched using the photoresist pattern 14 as a mask. Contact holes 16a and 16b are formed.

상기 콘택홀(16a, 16b)은 상기 소오스/드레인 영역(10)이 노출되도록 형성된 콘택홀(16a)과, 상기 게이트 전극(8)이 노출되도록 형성된 콘택홀(16b)을 포함한다.The contact holes 16a and 16b include a contact hole 16a formed to expose the source / drain region 10 and a contact hole 16b formed to expose the gate electrode 8.

도 1c를 참조하면, 상기 포토레지스트 패턴(14)이 제거된 후, 상기 콘택홀(16a, 16b)을 포함하여 절연막(12) 상에 배리어 금속막(barrier metal layer)(18)이 예를 들어, Ti/TiN막이 100Å 내지 900Å의 두께 범위 내로 증착 된다. 다음, 상기 배리어 금속막(18) 상에 텅스텐막(20)이 상기 콘택홀(16a, 16b)이 완전히 채워지도록 3000Å 내지 6000Å의 두께 범위 내로 증착 된다.Referring to FIG. 1C, after the photoresist pattern 14 is removed, a barrier metal layer 18 is formed on the insulating layer 12 including the contact holes 16a and 16b, for example. , Ti / TiN film is deposited within a thickness range of 100 kPa to 900 kPa. Next, a tungsten film 20 is deposited on the barrier metal film 18 in a thickness range of 3000 kPa to 6000 kPa so that the contact holes 16a and 16b are completely filled.

그러나, 상기 콘택홀(16a, 16b)을 알루미늄막보다 스텝 커버리지가 우수한 텅스텐막으로 채운다 하더라도, 높은 종횡비(high aspect ratio)를 갖는 콘택홀(16a, 16b)의 경우 도 1c에 도시된 바와 같이, 콘택홀(16a, 16b) 내에 보이드(21)가 발생된다.However, even when the contact holes 16a and 16b are filled with a tungsten film having better step coverage than the aluminum film, as shown in FIG. 1C in the case of the contact holes 16a and 16b having a high aspect ratio, The voids 21 are generated in the contact holes 16a and 16b.

상기 콘택홀(16a, 16b) 양측의 배리어 금속막(18)이 노출되도록 텅스텐막(20)이 에치 백(etchback) 공정으로 식각 되어 도 1d에서와 같이, 콘택 플러그(contact plug)(20a, 20b)가 형성된다.The tungsten film 20 is etched by an etchback process so that the barrier metal films 18 on both sides of the contact holes 16a and 16b are exposed. As shown in FIG. 1D, the contact plugs 20a and 20b are exposed. ) Is formed.

상기 콘택 플러그(20a, 20b)를 포함하여 배리어 금속막(18) 상에 알루미늄막이 증착된 후, 도 1e에 도시된 바와 같이, 상기 배리어 금속막(18)과 함께 패터닝(patterning) 되어 상기 콘택 플러그(20a, 20b)와 전기적으로 접속되는 알루미늄 라인(22)이 형성된다.After the aluminum film is deposited on the barrier metal film 18 including the contact plugs 20a and 20b, as shown in FIG. 1E, the contact plugs are patterned together with the barrier metal film 18 to form the contact plug. An aluminum line 22 is formed which is electrically connected to the 20a and 20b.

그러나, 상기 콘택 플러그(20a, 20b) 형성을 위한 에치 백 공정시 상기 보이드(21)가 표면에 노출되어 도 2의 참조 번호 24와 같이, 콘택홀(16a, 16b)의 하부면에 형성되어 있는 배리어 금속막(18)이 식각 되어 콘택 플러그(20a, 20b)와 게이트 전극(7) 내지 콘택 플러그(20a, 20b)와 소오스/드레인 영역(10)의 콘택 불량(contact fail)이 발생된다.However, during the etch back process for forming the contact plugs 20a and 20b, the voids 21 are exposed on the surface and are formed on the lower surfaces of the contact holes 16a and 16b as shown by reference numeral 24 of FIG. 2. The barrier metal layer 18 is etched to generate contact failures between the contact plugs 20a and 20b and the gate electrodes 7 to 20a and 20b and the source / drain regions 10.

또한, 상기 콘택 플러그(20a, 20b) 형성 후, 알루미늄 라인(22) 형성을 위한 패터닝시, 상기 콘택 플러그(20a, 20b)와의 오정렬 마진(misalign margin)이 부족하여 도 3의 참조 번호 26과 같이, 콘택 플러그(20a, 20b)와 알루미늄 라인(22)의 콘택 불량이 발생된다.In addition, after forming the contact plugs 20a and 20b, when patterning the aluminum line 22 to be formed, a misalign margin with the contact plugs 20a and 20b is insufficient, as shown by reference numeral 26 of FIG. 3. The contact failure of the contact plugs 20a and 20b and the aluminum line 22 occurs.

본 발명은 상술한 제반 문제점을 해결하기 위해 제안된 것으로서, 보이드 발생을 억제할 수 있고, 콘택 플러그 형성을 위한 식각 공정시 보이드가 노출되는 것을 방지할 수 있으며, 금속 라인 형성시 콘택 플러그와의 오버랩 마진(overlap margin)을 향상시킬 수 있는 반도체 장치의 콘택 형성 방법을 제공함에 그 목적이 있다.The present invention has been proposed to solve the above-mentioned problems, can suppress the generation of voids, prevent the exposure of the voids during the etching process for forming the contact plug, overlapping with the contact plug when forming the metal line It is an object of the present invention to provide a method for forming a contact of a semiconductor device capable of improving a margin margin.

도 1a 내지 도 1e는 종래의 반도체 장치의 콘택 형성 방법의 공정들을 순차적으로 보여주는 흐름도;1A to 1E are flowcharts sequentially showing processes of a method for forming a contact of a conventional semiconductor device;

도 2 및 도 3은 각각 종래의 반도체 장치의 콘택 형성시 발생되는 문제점을 설명하기 위한 단면도;2 and 3 are cross-sectional views illustrating problems caused when forming contacts in a conventional semiconductor device, respectively;

도 4a 내지 도 4g는 본 발명의 실시예에 따른 반도체 장치의 콘택 형성 방법의 공정들을 순차적으로 보여주는 흐름도.4A through 4G are flowcharts sequentially illustrating processes of a method for forming a contact of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

2, 100 : 반도체 기판4, 102 : 트렌치 격리2, 100: semiconductor substrate 4, 102: trench isolation

6, 104 : 트랜지스터12 : 절연막6, 104 transistor 12: insulating film

14, 116 : 포토레지스트 패턴16a, 16b : 콘택홀14 and 116 photoresist patterns 16a and 16b contact holes

18, 122 : 배리어 금속막20, 124 : 텅스텐막18, 122: barrier metal film 20, 124: tungsten film

21 : 보이드20a, 20b, 124a, 124b : 콘택 플러그21: void 20a, 20b, 124a, 124b: contact plug

22, 126 : 알루미늄 라인110 : 제 1 절연막22, 126: aluminum line 110: first insulating film

112 : 제 2 절연막114 : 제 3 절연막112: second insulating film 114: third insulating film

118 : 제 1 콘택홀118a : 확장된 제 1 콘택홀118: first contact hole 118a: expanded first contact hole

120a, 120b : 제 2 콘택홀120a, 120b: second contact hole

(구성)(Configuration)

상술한 목적을 달성하기 위한 본 발명에 의하면, 반도체 장치의 콘택 형성 방법은, 하부 도전 영역이 형성된 반도체 기판 상에 제 1 절연막, 제 2 절연막, 그리고 제 3 절연막을 증착하되, 상기 제 2 절연막을 상기 제 1 절연막과 제 3 절연막에 대해 식각 선택비를 갖는 물질로 증착하는 단계; 상기 제 3 절연막 상에 콘택홀 형성을 위한 마스크 패턴을 형성하는 단계; 상기 마스크 패턴을 사용하여 상기 제 3 절연막 및 제 2 절연막을 차례로 식각하여 제 1 콘택홀을 형성하는 단계; 상기 마스크 패턴의 일부 두께를 식각하는 단계; 상기 마스크 패턴을 다시 사용하여 상기 제 1 콘택홀 양측벽의 제 3 절연막을 식각하여 확장된 제 1 콘택홀을 형성하되, 상기 제 2 절연막을 식각 정지층으로 사용하여 형성하고, 동시에 상기 하부 도전 영역이 노출되도록 상기 제 1 콘택홀 하부의 제 1 절연막을 식각하여 제 2 콘택홀을 형성하되, 상기 제 2 절연막을 마스크로 사용하여 형성하는 단계; 상기 마스크 패턴을 제거하는 단계; 상기 제 2 콘택홀 및 확장된 제 1 콘택홀이 채워지도록 반도체 기판 전면에 제 1 금속막을 증착하는 단계; 상기 제 1 금속막이 상기 제 2 콘택홀 및 확장된 제 1 콘택홀 내에만 남도록 나머지 영역의 제 1 금속막을 제거하여 콘택 플러그를 형성하는 단계; 및 상기 반도체 기판 전면에 제 2 금속막을 증착 및 패터닝하여 상기 콘택 플러그와 전기적으로 접속되는 금속 라인을 형성하는 단계를 포함한다.According to the present invention for achieving the above object, in the contact forming method of a semiconductor device, a first insulating film, a second insulating film, and a third insulating film is deposited on a semiconductor substrate having a lower conductive region, the second insulating film Depositing a material having an etch selectivity with respect to the first insulating film and the third insulating film; Forming a mask pattern for forming a contact hole on the third insulating layer; Forming a first contact hole by sequentially etching the third insulating film and the second insulating film using the mask pattern; Etching a part thickness of the mask pattern; The mask pattern is used again to etch a third insulating film on both sidewalls of the first contact hole to form an extended first contact hole, wherein the second insulating film is used as an etch stop layer, and at the same time, the lower conductive region. Forming a second contact hole by etching the first insulating layer under the first contact hole to expose the second contact hole, wherein the second insulating layer is used as a mask; Removing the mask pattern; Depositing a first metal film on an entire surface of the semiconductor substrate to fill the second contact hole and the extended first contact hole; Forming a contact plug by removing the first metal film in the remaining area such that the first metal film remains only in the second contact hole and the extended first contact hole; And depositing and patterning a second metal film on the entire surface of the semiconductor substrate to form a metal line electrically connected to the contact plug.

(작용)(Action)

도 4g를 참조하면, 본 발명의 실시예에 따른 신규한 반도체 장치의 콘택 형성 방법은, 식각 선택비(etch selectivity)를 갖는 다층 절연막을 사용하여 콘택홀의 개구부를 선택적으로 확장시킨다. 이로써, 콘택홀 내의 금속막 증착 공정을 용이하게 할 수 있고, 콘택 플러그 형성을 위한 에치 백 공정시 보이드가 노출되는 것을 방지할 수 있으며, 따라서 보이드 노출에 따른 콘택 페일을 방지할 수 있다. 또한, 콘택홀의 개구부가 확장됨에 따라, 콘택 플러그와 금속 라인의 오버랩 마진(overlap margin)을 향상시킬 수 있다.Referring to FIG. 4G, the contact forming method of the novel semiconductor device according to the embodiment of the present invention selectively extends the opening of the contact hole by using a multilayer insulating film having an etch selectivity. As a result, the deposition process of the metal film in the contact hole can be facilitated, and the voids can be prevented from being exposed during the etch back process for forming the contact plug, thus preventing contact fail due to the void exposure. In addition, as the opening of the contact hole is expanded, an overlap margin of the contact plug and the metal line may be improved.

(실시예)(Example)

이하, 도 4를 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 4.

도 4a 내지 도 4g는 본 발명의 실시예에 따른 반도체 장치의 콘택 형성 방법의 공정들을 순차적으로 보여주는 흐름도이다.4A through 4G are flowcharts sequentially illustrating processes of a method for forming a contact of a semiconductor device according to an embodiment of the present invention.

도 4a를 참조하면, 본 발명의 실시예에 따른 반도체 장치의 콘택 형성 방법은 먼저, 반도체 기판(100) 상에 활성 영역과 비활성 영역을 정의하기 위해 소자 격리 예를 들어, 트렌치 격리(102)가 형성된다.Referring to FIG. 4A, a method for forming a contact in a semiconductor device according to an embodiment of the present invention may first include device isolation, for example, trench isolation 102, to define active and inactive regions on a semiconductor substrate 100. Is formed.

상기 활성 영역 상에 트랜지스터(104)가 형성된다. 상기 트랜지스터(104)는 게이트 전극(105), 게이트 마스크(106), 게이트 스페이서(106), 그리고 소오스/드레인 영역(108)을 포함한다.Transistor 104 is formed on the active region. The transistor 104 includes a gate electrode 105, a gate mask 106, a gate spacer 106, and a source / drain region 108.

상기 트랜지스터(104)를 포함하여 반도체 기판(100) 전면에 제 1 절연막(110)이 증착 된다. 상기 제 1 절연막(110) 상에 제 1 절연막(110)과 식각 선택비(etch selectivity)를 갖는 제 2 절연막(112)이 증착 된다. 이어서, 상기 제 2 절연막(112) 상에 제 2 절연막(112)과 식각 선택비를 갖는 제 3 절연막(114)이 증착 된다.The first insulating layer 110 is deposited on the entire surface of the semiconductor substrate 100 including the transistor 104. A second insulating layer 112 having an etch selectivity with the first insulating layer 110 is deposited on the first insulating layer 110. Subsequently, a third insulating layer 114 having an etch selectivity with the second insulating layer 112 is deposited on the second insulating layer 112.

예를 들어, 상기 제 1 및 제 3 절연막(110, 114)은 동일한 물질로 형성된다.For example, the first and third insulating layers 110 and 114 are formed of the same material.

바람직하게, 상기 제 1 및 제 3 절연막(110, 114)은 산화막 예를 들어, PTEOS막 내지 O3-TEOS막으로 형성되고, 1000Å 내지 7000Å의 두께 범위 내로 증착 된다. 그리고, 상기 제 2 절연막(112)은 질화막으로 형성되고, 1000Å 내지 5000Å의 두께 범위 내로 증착 된다.Preferably, the first and third insulating films 110 and 114 are formed of an oxide film, for example, a PTEOS film or an O3-TEOS film, and are deposited within a thickness range of 1000 kPa to 7000 kPa. In addition, the second insulating film 112 is formed of a nitride film and is deposited within a thickness range of 1000 kPa to 5000 kPa.

도 4b에 있어서, 상기 제 3 절연막(114) 상에 콘택홀 형성용 포토레지스트 패턴(116)이 형성된다. 상기 포토레지스트 패턴(116)을 마스크로 사용하여 상기 제 3 절연막(114) 및 제 2 절연막(112)이 차례로 이방성 식각 공정으로 식각 되어 'a'의 폭을 갖는 제 1 콘택홀(118)이 형성된다.In FIG. 4B, a photoresist pattern 116 for forming a contact hole is formed on the third insulating layer 114. Using the photoresist pattern 116 as a mask, the third insulating layer 114 and the second insulating layer 112 are sequentially etched by an anisotropic etching process to form a first contact hole 118 having a width of 'a'. do.

상기 포토레지스트 패턴(116)이 예를 들어, 등방성 식각 공정으로 식각 되어 'b'의 폭을 갖도록 확장된 후, 다시 상기 포토레지스트 패턴(116)을 마스크로 사용하여 상기 제 3 절연막(114) 및 상기 제 1 절연막(110)이 이방성 식각 공정으로 식각된다. 그러면, 도 4c에서와 같이, 확장된 제 1 콘택홀(118a)과, 확장된 제 1 콘택홀(118a)의 하부에 연결된 제 2 콘택홀(120a, 120b)이 형성된다.After the photoresist pattern 116 is etched by, for example, an isotropic etching process and expanded to have a width 'b', the third insulating layer 114 and the photoresist pattern 116 are used again as a mask. The first insulating layer 110 is etched by an anisotropic etching process. Then, as shown in FIG. 4C, the extended first contact hole 118a and the second contact holes 120a and 120b connected to the lower portion of the extended first contact hole 118a are formed.

상기 제 2 콘택홀(120a, 120b)은 상기 소오스/드레인 영역(108)이 노출되도록 형성된 콘택홀(120a) 및 상기 게이트 전극(105)이 노출되도록 형성된 콘택홀(120b)을 포함한다.The second contact holes 120a and 120b include a contact hole 120a formed to expose the source / drain region 108 and a contact hole 120b formed to expose the gate electrode 105.

상기 확장된 제 1 콘택홀(118a) 형성 및 제 2 콘택홀(120a, 120b) 형성시, 상기 제 2 절연막(112)이 식각 정지층 및 식각 마스크로 각각 사용된다.In forming the extended first contact hole 118a and forming the second contact hole 120a and 120b, the second insulating layer 112 is used as an etch stop layer and an etch mask, respectively.

상술한 바와 같이 형성된 확장된 제 1 콘택홀(118a)은 종래 콘택홀의 개구부에 해당되며, 상기 제 2 콘택홀(120a, 120b)은 종래 콘택홀의 하부에 해당된다. 이때, 상기 확장된 제 1 콘택홀(118a)은 종래 콘택홀의 개구부보다 상기 확장된 폭만큼 더 크게 되고, 상기 제 2 콘택홀(120a, 120b)은 종래 콘택홀의 하부의 폭과 같게 된다.The extended first contact hole 118a formed as described above corresponds to an opening of the conventional contact hole, and the second contact holes 120a and 120b correspond to a lower portion of the conventional contact hole. In this case, the expanded first contact hole 118a is larger than the opening of the conventional contact hole by the expanded width, and the second contact holes 120a and 120b are equal to the width of the lower portion of the conventional contact hole.

이와 같이, 콘택홀의 개구부가 종래 보다 확장됨으로써 콘택홀을 금속막으로 채우는 공정이 용이하게 되고, 또한 콘택 플러그 형성시 발생되는 보이드 노출에 따른 콘택 불량을 방지하게 된다.As described above, since the opening of the contact hole is extended than before, the process of filling the contact hole with the metal film is facilitated, and the contact failure caused by the exposure of the void generated when forming the contact plug is prevented.

상기 포토레지스트 패턴(116)이 제거된 후(도 4d), 상기 제 2 콘택홀(120a, 120b) 및 확장된 제 1 콘택홀(118a)을 포함하여 상기 제 3 절연막(114) 상에 배리어 금속막(122)이 증착 된다. 상기 배리어 금속막(122)은 예를 들어, Ti/TiN막으로서 100Å 내지 1000Å의 두께 범위 내로 증착 된다.After the photoresist pattern 116 is removed (FIG. 4D), the barrier metal is formed on the third insulating layer 114 including the second contact holes 120a and 120b and the extended first contact hole 118a. The film 122 is deposited. The barrier metal film 122 is, for example, deposited as a Ti / TiN film within a thickness range of 100 kPa to 1000 kPa.

상기 제 2 콘택홀(120a, 120b) 및 확장된 제 1 콘택홀(118a)이 완전히 채워지도록 상기 배리어 금속막(122) 상에 제 1 금속막(124) 예를 들어, 텅스텐막(124)이 증착 된다. 상기 텅스텐막(124)은 2000Å 내지 6000Å의 두께 범위 내로 증착 된다. 이때, 상기 제 2 콘택홀(120a, 120b) 내에 보이드가 생성될 수 있으나, 이 보이드는 후속 콘택 플러그 형성을 위한 에치 백 공정시 노출되지 않는 깊이에 형성된다.A first metal film 124, for example, a tungsten film 124, is formed on the barrier metal film 122 so that the second contact holes 120a and 120b and the extended first contact hole 118a are completely filled. Is deposited. The tungsten film 124 is deposited in a thickness range of 2000 kV to 6000 kV. In this case, voids may be generated in the second contact holes 120a and 120b, but the voids are formed at a depth that is not exposed during an etch back process for forming a subsequent contact plug.

도 4f에 있어서, 상기 텅스텐막(124)이 상기 확장된 제 1 콘택홀(118a) 양측의 제 3 절연막(114) 상의 배리어 금속막(122)이 노출되도록 에치 백 공정으로 식각 되어 콘택 플러그(124a, 124b)가 형성된다.In FIG. 4F, the tungsten film 124 is etched by an etch back process so that the barrier metal film 122 on the third insulating film 114 on both sides of the extended first contact hole 118a is exposed. , 124b).

상기 콘택 플러그(124a, 124b)를 포함하여 배리어 금속막(122) 상에 상기 텅스텐막보다 저항이 낮은 금속막인 알루미늄막이 증착된 후, 상기 알루미늄막이 상기 배리어 금속막(122)과 함께 패터닝되어 도 4g에 도시된 바와 같이, 알루미늄 라인(126)이 형성된다. 상기 알루미늄막은 예를 들어, 2000Å 내지 6000Å의 두께 범위 내로 증착 된다.After the aluminum film including the contact plugs 124a and 124b is deposited on the barrier metal film 122, which is a metal film having a lower resistance than the tungsten film, the aluminum film is patterned together with the barrier metal film 122. As shown in 4g, an aluminum line 126 is formed. The aluminum film is deposited in a thickness range of, for example, 2000 kPa to 6000 kPa.

이때, 콘택홀의 개구부가 확장됨에 따라, 상기 알루미늄 라인(126) 형성시 콘택 플러그(124a, 124b)와 알루미늄 라인(126)간의 오버랩 마진이 종래 보다 더 향상되며, 종래의 문제점인 오정렬에 의한 콘택 페일 내지 보이드가 노출됨에 따라 발생되는 콘택 페일이 방지된다. 이때, 상기 알루미늄막과 텅스텐막의 식각 선택비는 20 : 1 이상으로 높게 유지되도록 한다.At this time, as the opening of the contact hole is expanded, the overlap margin between the contact plugs 124a and 124b and the aluminum line 126 when the aluminum line 126 is formed is further improved than before, and the contact fail due to misalignment is a conventional problem. To contact failing as the void is exposed is prevented. In this case, the etching selectivity of the aluminum film and the tungsten film is maintained at 20: 1 or more.

본 발명은 식각 선택비를 갖는 다층 절연막을 사용하여 콘택홀의 개구부를 확장시킴으로써, 콘택 플러그 형성시 보이드가 노출되는 것을 방지할 수 있고, 따라서 보이드 노출에 따른 콘택 페일을 방지할 수 있는 효과가 있다.The present invention extends the opening of the contact hole by using a multilayer insulating film having an etch selectivity, thereby preventing the voids from being exposed when forming the contact plug, thus preventing contact fail due to the void exposure.

또한, 콘택홀의 개구부를 확장함에 따라, 콘택 플러그와 금속 라인의 오버랩 마진을 향상시킬 수 있는 효과가 있다.In addition, as the opening of the contact hole is expanded, an overlap margin between the contact plug and the metal line may be improved.

Claims (3)

하부 도전 영역(105, 108)이 형성된 반도체 기판(100) 상에 제 1 절연막(110), 제 2 절연막(112), 그리고 제 3 절연막(114)을 증착하되, 상기 제 2 절연막(112)을 상기 제 1 절연막(110)과 제 3 절연막(114)에 대해 식각 선택비(etch selectivity)를 갖는 물질로 증착하는 단계;The first insulating layer 110, the second insulating layer 112, and the third insulating layer 114 are deposited on the semiconductor substrate 100 on which the lower conductive regions 105 and 108 are formed, and the second insulating layer 112 is deposited. Depositing a material having an etch selectivity with respect to the first insulating film 110 and the third insulating film 114; 상기 제 3 절연막(114) 상에 콘택홀 형성을 위한 마스크 패턴(mask pattern)(116)을 형성하는 단계;Forming a mask pattern 116 on the third insulating layer 114 to form contact holes; 상기 마스크 패턴(116)을 사용하여 상기 제 3 절연막(114) 및 제 2 절연막(112)을 차례로 식각하여 제 1 콘택홀(118)을 형성하는 단계;Forming a first contact hole (118) by sequentially etching the third insulating film (114) and the second insulating film (112) using the mask pattern (116); 상기 마스크 패턴(116)의 일부 두께를 식각하는 단계;Etching a portion thickness of the mask pattern 116; 상기 마스크 패턴(116)을 다시 사용하여 상기 제 1 콘택홀(118) 양측벽의 제 3 절연막(114)을 식각하여 확장된 제 1 콘택홀(118a)을 형성하되, 상기 제 2 절연막(112)을 식각 정지층(etch stopping layer)으로 사용하여 형성하고,The mask pattern 116 is used again to etch the third insulating layer 114 on both sides of the first contact hole 118 to form an extended first contact hole 118a, wherein the second insulating layer 112 is formed. Is formed using an etch stopping layer, 동시에 상기 하부 도전 영역(105, 108)이 노출되도록 상기 제 1 콘택홀(118) 하부의 제 1 절연막(110)을 식각하여 제 2 콘택홀(120a, 120b)을 형성하되, 상기 제 2 절연막(112)을 마스크로 사용하여 형성하는 단계;At the same time, the first insulating layer 110 under the first contact hole 118 is etched to expose the lower conductive regions 105 and 108 to form second contact holes 120a and 120b. Forming using 112 as a mask; 상기 마스크 패턴(116)을 제거하는 단계;Removing the mask pattern 116; 상기 제 2 콘택홀(120a, 120b) 및 확장된 제 1 콘택홀(118a)이 채워지도록 반도체 기판(100) 전면에 제 1 금속막(124)을 증착하는 단계;Depositing a first metal film (124) on the entire surface of the semiconductor substrate (100) to fill the second contact holes (120a, 120b) and the extended first contact holes (118a); 상기 제 1 금속막(124)이 상기 제 2 콘택홀(120a, 120b) 및 확장된 제 1 콘택홀(118a) 내에만 남도록 나머지 영역의 제 1 금속막(124)을 제거하여 콘택 플러그(contact plug)(124a, 124b)를 형성하는 단계; 및The contact plug is removed by removing the first metal layer 124 in the remaining area so that the first metal layer 124 remains only in the second contact holes 120a and 120b and the extended first contact hole 118a. Forming 124a, 124b; And 상기 반도체 기판(100) 전면에 제 2 금속막을 증착 및 패터닝(patterning)하여 상기 콘택 플러그(124a, 124b)와 전기적으로 접속되는 금속 라인(metal line)(126)을 형성하는 단계를 포함하는 반도체 장치의 콘택 형성 방법.Depositing and patterning a second metal layer on the entire surface of the semiconductor substrate 100 to form metal lines 126 electrically connected to the contact plugs 124a and 124b. Contact formation method. 제 1 항에 있어서,The method of claim 1, 상기 제 1 및 제 3 절연막(110, 114)은 산화막으로 형성되고, 상기 제 2 절연막(112)은 질화막으로 형성되는 반도체 장치의 콘택 형성 방법.Wherein the first and third insulating films (110, 114) are formed of an oxide film, and the second insulating film (112) is formed of a nitride film. 제 1 항에 있어서,The method of claim 1, 상기 마스크 패턴(116)의 일부 두께의 식각은 등방성 식각(anisotropic etch) 공정으로 수행되는 반도체 장치의 콘택 형성 방법.The etching of the part thickness of the mask pattern 116 may be performed by an anisotropic etching process.
KR1019990000112A 1999-01-06 1999-01-06 Method for forming contact of semiconductor device KR20000050330A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100632658B1 (en) * 2004-12-29 2006-10-12 주식회사 하이닉스반도체 Method of forming metal line in semiconductor device
KR100833417B1 (en) 2006-04-13 2008-05-29 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100632658B1 (en) * 2004-12-29 2006-10-12 주식회사 하이닉스반도체 Method of forming metal line in semiconductor device
KR100833417B1 (en) 2006-04-13 2008-05-29 주식회사 하이닉스반도체 Method for fabricating semiconductor device

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