KR20010036183A - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
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- KR20010036183A KR20010036183A KR1019990043088A KR19990043088A KR20010036183A KR 20010036183 A KR20010036183 A KR 20010036183A KR 1019990043088 A KR1019990043088 A KR 1019990043088A KR 19990043088 A KR19990043088 A KR 19990043088A KR 20010036183 A KR20010036183 A KR 20010036183A
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- insulating film
- film
- plug
- contact hole
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title description 8
- 239000003990 capacitor Substances 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- 238000003860 storage Methods 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000000206 photolithography Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 230000008021 deposition Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 239000004020 conductor Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 커패시터의 스토리지노드(storage node) 전극과 비트라인(bit line)의 단락을 방지하기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for preventing a short circuit between a storage node electrode and a bit line of a capacitor.
종래 반도체소자의 제조방법을 첨부한 도1a 내지 도1e의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A detailed description will now be made with reference to the procedure cross-sectional view of FIGS. 1A to 1E attached to a conventional method of manufacturing a semiconductor device.
먼저, 도1a에 도시한 바와같이 소자(미도시)가 형성된 반도체기판(1) 상부에 절연막(2)을 형성한 다음 일부를 식각하고, 도전물질을 채워 소자의 특정영역과 선택적으로 접속되는 플러그(3)를 형성하고, 상부전면에 절연막(4)을 형성하여 층간절연 및 평탄화한 다음 절연막(4) 상부에 도전성물질을 증착 및 패터닝하여 비트라인(5)을 형성한다.First, as shown in FIG. 1A, an insulating film 2 is formed on a semiconductor substrate 1 on which an element (not shown) is formed, and then a portion thereof is etched, and a plug is selectively connected to a specific region of the element by filling a conductive material. (3) is formed, and an insulating film 4 is formed on the upper surface to interlayer insulation and planarization, and then a bit line 5 is formed by depositing and patterning a conductive material on the insulating film 4.
그리고, 도1b에 도시한 바와같이 상기 비트라인(5)이 패터닝된 구조물의 상부전면에 절연막(6) 및 폴리실리콘(7)을 순차적으로 형성한 다음 폴리실리콘(7)의 상부에 상기 플러그(3)가 형성된 영역이 오픈되는 감광막(PR1) 패턴을 형성하고, 이를 마스크로 적용하여 폴리실리콘(7) 및 절연막(6)을 식각함으로써, 플러그(3)가 노출되는 콘택홀(8)을 형성한다.In addition, as shown in FIG. 1B, an insulating film 6 and a polysilicon 7 are sequentially formed on the upper surface of the structure in which the bit line 5 is patterned, and then the plugs are formed on the polysilicon 7. The photoresist film PR1 pattern in which the region where 3) is formed is opened is formed, and the polysilicon 7 and the insulating film 6 are etched by applying the mask as a mask to form the contact hole 8 through which the plug 3 is exposed. do.
그리고, 도1c에 도시한 바와같이 상기 감광막(PR1) 패턴을 제거하고, 폴리실리콘을 증착 및 에치-백(etch-back)하여 상기 콘택홀(8)을 채우는 폴리플러그(9)를 형성한다. 이때, 폴리실리콘의 에치-백으로 인해 상기 절연막(6) 상부에 형성된 폴리실리콘(7)도 제거된다.As shown in FIG. 1C, the photoresist film PR1 pattern is removed and polysilicon is deposited and etched back to form a poly plug 9 filling the contact hole 8. At this time, the polysilicon 7 formed on the insulating film 6 is also removed due to the etch-back of the polysilicon.
그리고, 도1d에 도시한 바와같이 상기 폴리플러그(9)가 형성된 구조물의 상부에 식각차단 질화막(10) 및 커패시터 산화막(11)을 형성한다.As shown in FIG. 1D, an etch-blocking nitride film 10 and a capacitor oxide film 11 are formed on the structure where the poly plug 9 is formed.
그리고, 도1e에 도시한 바와같이 상기 커패시터 산화막(11) 상에 스토리지 노드 사진식각을 적용하여 상기 폴리플러그(9)가 노출되도록 커패시터 산화막(11) 및 식각차단 질화막(10)을 식각한다.As shown in FIG. 1E, the capacitor oxide film 11 and the etch-blocking nitride film 10 are etched by applying the storage node photolithography on the capacitor oxide film 11 to expose the polyplug 9.
이후에, 상기 결과물의 상부전면에 폴리실리콘을 증착 및 에치-백하고, 상기 커패시터 산화막(11)을 제거하여 커패시터의 스토리지 노드를 형성한다.Thereafter, polysilicon is deposited and etched back on the upper surface of the resultant, and the capacitor oxide layer 11 is removed to form a storage node of the capacitor.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 스토리지 노드 사진식각을 적용할 때, 리세스(recess)된 폴리플러그가 노출되도록 과도식각을 수행함에 따라 하부에 패터닝된 비트라인과 후속공정을 통해 형성되는 스토리지 노드의 단락이 발생하여 반도체소자의 신뢰성을 저하시키는 문제점이 있었다.However, in the method of manufacturing a conventional semiconductor device as described above, when applying the storage node photoetch, the overetching is performed so that the recessed polyplug is exposed. There is a problem in that a short circuit occurs in the storage node to be formed, thereby reducing the reliability of the semiconductor device.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 커패시터의 스토리지 노드와 비트라인의 단락을 방지할 수 있는 반도체소자의 제조방법을 제공하는데 있다.The present invention has been made to solve the conventional problems as described above, an object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the short circuit of the storage node and the bit line of the capacitor.
도1a 내지 도1e는 종래 반도체소자의 제조방법을 보인 수순단면도.1A to 1E are cross-sectional views showing a conventional method for manufacturing a semiconductor device.
도2a 내지 도2e는 본 발명의 일 실시예를 보인 수순단면도.Figures 2a to 2e is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
21:반도체기판 22,24,26:절연막21: semiconductor substrate 22, 24, 26: insulating film
23:플러그 25:비트라인23: Plug 25: Bit line
27:캡질화막 28:콘택홀27: capsulating film 28: contact hole
29:폴리플러그 30:커패시터 산화막29: polyplug 30: capacitor oxide film
PR21:감광막PR21: Photosensitive film
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 제조방법은 소자의 특정영역과 선택적으로 접속되는 플러그가 형성된 반도체기판 상에 제1절연막을 형성하고, 그 제1절연막의 상부에 비트라인을 패터닝하는 공정과; 상기 비트라인이 패터닝된 구조물의 상부에 제2절연막과 캡질화막을 순차적으로 형성하는 공정과; 상기 캡질화막 상에 사진식각을 적용하여 캡질화막 및 제2절연막을 식각함으로써, 상기 플러그가 노출되는 콘택홀을 형성하는 공정과; 상기 콘택홀이 형성된 구조물 상에 폴리실리콘을 증착 및 에치-백하여 상기 콘택홀을 채우는 폴리플러그를 형성하는 공정과; 상기 폴리플러그가 형성된 구조물 상에 커패시터 산화막을 형성한 다음 스토리지 노드 사진식각을 적용하여 상기 폴리플러그가 노출되도록 커패시터 산화막을 과도식각하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A semiconductor device manufacturing method for achieving the object of the present invention as described above forms a first insulating film on a semiconductor substrate having a plug selectively connected to a specific region of the device, and a bit line on the first insulating film Patterning the; Sequentially forming a second insulating film and a cap nitride film on the bit patterned structure; Forming a contact hole through which the plug is exposed by etching the cap nitride layer and the second insulating layer by applying photolithography on the cap nitride layer; Depositing and etching back polysilicon on the structure in which the contact hole is formed to form a polyplug filling the contact hole; And forming a capacitor oxide layer on the polyplug formed structure and then overetching the capacitor oxide layer to expose the polyplug by applying a storage node photolithography.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법을 첨부한 도2a 내지 도2e의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.The procedure of the semiconductor device according to the present invention as described above will be described in detail with reference to the embodiment of the cross-sectional view of Figures 2a to 2e as an embodiment.
먼저, 도2a에 도시한 바와같이 소자(미도시)가 형성된 반도체기판(21) 상부에 절연막(22)을 형성한 다음 일부를 식각하고, 도전물질을 채워 소자의 특정영역과 선택적으로 접속되는 플러그(23)를 형성하고, 상부전면에 절연막(24)을 형성하여 층간절연 및 평탄화한 다음 절연막(24) 상부에 도전성물질을 증착 및 패터닝하여 비트라인(25)을 형성한다.First, as shown in FIG. 2A, an insulating film 22 is formed on a semiconductor substrate 21 on which an element (not shown) is formed, and then a portion thereof is etched, and a plug is selectively connected to a specific region of the element by filling a conductive material. (23) is formed, the insulating film 24 is formed on the entire upper surface, interlayer insulation and planarization, and then the bit line 25 is formed by depositing and patterning a conductive material on the insulating film 24.
그리고, 도2b에 도시한 바와같이 상기 비트라인(25)이 패터닝된 구조물의 상부전면에 절연막(26) 및 캡질화막(27)을 순차적으로 형성한 다음 캡질화막(27)의 상부에 상기 플러그(23)가 형성된 영역이 오픈되는 감광막(PR21) 패턴을 형성하고, 이를 마스크로 적용하여 캡질화막(27) 및 절연막(26)을 식각함으로써, 플러그(23)가 노출되는 콘택홀(28)을 형성한다. 이때, 캡질화막(27)은 후속 공정의 스토리지 노드 사진식각을 통해 커패시터 산화막(30)의 과도식각하여 폴리플러그(29)를 노출시킬 때, 비트라인(25) 상에 형성된 절연막(26)이 식각되는 것을 방지하는 식각차단막의 역할을 위해 형성하는 것으로, 커패시터 산화막(30)의 과도식각을 고려하여 충분한 두께로 형성하는 것이 바람직하다.As shown in FIG. 2B, an insulating film 26 and a cap nitride film 27 are sequentially formed on the upper surface of the structure in which the bit line 25 is patterned, and then the plug () is formed on the cap nitride film 27. The photoresist film PR21 pattern in which the region in which the 23 is formed is opened is formed, and the capsylation film 27 and the insulating film 26 are etched by applying the mask as a mask to form the contact hole 28 through which the plug 23 is exposed. do. In this case, when the cap nitride layer 27 exposes the polyplug 29 by overetching the capacitor oxide layer 30 through the storage node photolithography in a subsequent process, the insulating layer 26 formed on the bit line 25 is etched. It is formed for the role of the etch barrier film to prevent the formation, it is preferable to form a sufficient thickness in consideration of the transient etching of the capacitor oxide film 30.
그리고, 도2c에 도시한 바와같이 상기 감광막(PR21) 패턴을 제거하고, 폴리실리콘을 증착 및 에치-백하여 콘택홀(28)을 채우는 폴리플러그(29)를 형성한다.As shown in FIG. 2C, the photoresist film PR21 pattern is removed, and polysilicon is deposited and etched back to form a poly plug 29 filling the contact hole 28.
그리고, 도2d에 도시한 바와같이 상기 폴리플러그(29)가 형성된 구조물의 상부에 커패시터 산화막(30)을 형성한다.As shown in FIG. 2D, the capacitor oxide layer 30 is formed on the structure in which the poly plug 29 is formed.
그리고, 도2e에 도시한 바와같이 상기 커패시터 산화막(30) 상에 스토리지 노드 사진식각을 적용하여 상기 폴리플러그(29)가 노출되도록 커패시터 산화막(30)을 과도식각한다. 이때, 상기 캡질화막(27)은 커패시터 산화막(30)을 과도식각할 때, 하부 절연막(26)의 식각을 방지하여 비트라인(25)이 노출되지 않도록 한다.As shown in FIG. 2E, the capacitor oxide film 30 is overetched so that the polyplug 29 is exposed by applying a storage node photolithography on the capacitor oxide film 30. In this case, the cap nitride layer 27 prevents etching of the lower insulating layer 26 when the capacitor oxide layer 30 is excessively etched so that the bit line 25 is not exposed.
이후에, 상기 결과물의 상부전면에 폴리실리콘을 증착 및 에치-백하고, 상기 커패시터 산화막(30)을 제거하여 커패시터의 스토리지 노드를 형성한다.Thereafter, polysilicon is deposited and etched back on the upper surface of the resultant, and the capacitor oxide layer 30 is removed to form a storage node of the capacitor.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 스토리지 노드 사진식각을 통해 커패시터 산화막을 과도식각할 때, 식각차단 역할을 하는 캡질화막을 통해 하부에 패터닝된 비트라인이 노출되지 않도록 함으로써, 후속 공정을 통해 형성되는 스토리지 노드와 비트라인의 단락을 방지하여 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention as described above is performed by over-etching a capacitor oxide layer through photolithography of a storage node, thereby preventing the patterned bit line from being exposed through the capzilization layer which serves as an etch barrier. By preventing the short circuit between the storage node and the bit line formed through the process, it is possible to improve the reliability of the semiconductor device.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990043088A KR20010036183A (en) | 1999-10-06 | 1999-10-06 | Fabricating method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990043088A KR20010036183A (en) | 1999-10-06 | 1999-10-06 | Fabricating method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR20010036183A true KR20010036183A (en) | 2001-05-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019990043088A KR20010036183A (en) | 1999-10-06 | 1999-10-06 | Fabricating method of semiconductor device |
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| Country | Link |
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| KR (1) | KR20010036183A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7030439B2 (en) | 2003-03-15 | 2006-04-18 | Samsung Electronics Co., Ltd. | DRAM memory cell and method of manufacturing the same |
-
1999
- 1999-10-06 KR KR1019990043088A patent/KR20010036183A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7030439B2 (en) | 2003-03-15 | 2006-04-18 | Samsung Electronics Co., Ltd. | DRAM memory cell and method of manufacturing the same |
| US7321146B2 (en) | 2003-03-15 | 2008-01-22 | Samsung Electronics Co., Ltd. | DRAM memory cell and method of manufacturing the same |
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