KR20000045434A - Method for fabricating metal wiring - Google Patents
Method for fabricating metal wiring Download PDFInfo
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- KR20000045434A KR20000045434A KR1019980061992A KR19980061992A KR20000045434A KR 20000045434 A KR20000045434 A KR 20000045434A KR 1019980061992 A KR1019980061992 A KR 1019980061992A KR 19980061992 A KR19980061992 A KR 19980061992A KR 20000045434 A KR20000045434 A KR 20000045434A
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- South Korea
- Prior art keywords
- metal wiring
- layer
- metal
- film
- etching
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 85
- 239000002184 metal Substances 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000010410 layer Substances 0.000 claims abstract description 62
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 15
- 239000010937 tungsten Substances 0.000 claims abstract description 15
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 150000003608 titanium Chemical class 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 15
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000003667 anti-reflective effect Effects 0.000 abstract 1
- 239000003292 glue Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- -1 or the like Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 금속배선의 콘택공정시 중첩마진의 감소로 인하여 유발될 수 있는 금속배선의 손상 및 저항 감소를 방지하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a technique for preventing damage to metal wirings and a reduction in resistance, which may be caused by a reduction in overlap margin during a metal wiring contact process.
금속배선과 콘택 간의 중첩마진이 작고 선폭이 가는 고집적 반도체소자의 제조공정에서 종래의 기술대로 금속막의 증착 및 식각 방법에 의해 금속선을 형성할 경우 금속선의 라인 엔드 쇼트닝 ( line end shortening ) 현상에 의하여 금속배선이 콘택에 플러그된 금속과 완전히 콘택되지 못하는 문제가 야기된다.In the manufacturing process of a highly integrated semiconductor device having a small overlap margin between the metal wiring and the contact and having a large line width, when the metal line is formed by the deposition and etching method of the metal film according to the conventional technique, the metal may be formed by line end shortening of the metal line. The problem arises that the wiring is not completely in contact with the metal plugged into the contact.
또한, 금속막 식각공정시 금속배선 간의 브릿지 ( bridge ) 방지를 위해 금속막 식각이 완료된 후에도 과도식각을 행하게 되는데 앞서 전술한 라인 엔트 쇼트닝 현상이 발생했거나 또는 금속선 포토-리소그래피 ( photo-lithography ) 작업시 오정렬이 발생한 경우 금속막 식각후 과도식각시 플러그가 리세스 ( recess ) 됨으로써 비아 ( via ) 저항의 증가 내지는 불량까지 유발할 수 있다.In addition, during the metal film etching process, overetching is performed even after the metal film etching is completed to prevent the bridge between the metal wires. The above-described line end shortening phenomenon or the metal line photo-lithography operation is performed. In the case of misalignment, the plug may be recessed during the over-etching after the metal film is etched, which may cause an increase or a failure of the via resistance.
도 1a 내지 도 1e 는 종래기술의 실시예에 따른 반도체소자의 금속배선 형성공정을 도시한 단면도이다.1A to 1E are cross-sectional views illustrating a metal wiring forming process of a semiconductor device according to an embodiment of the prior art.
먼저, 반도체기판(51) 상부에 하부절연층(53)을 형성한다. 이때, 상기 하부절연층(53)은 워드라인, 비트라인, 캐패시터 등의 단위 소자가 형성된 것이고, 상기 단위 소자들 상부에 금속배선이 형성되어 있을 수도 있다.First, a lower insulating layer 53 is formed on the semiconductor substrate 51. In this case, the lower insulating layer 53 may be formed of a unit element such as a word line, a bit line, a capacitor, or the like, and a metal wiring may be formed on the unit elements.
그 다음, 금속배선 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(도시안됨)을 형성하고 이를 마스크로하여 상기 하부절연층(53)을 식각하여 상기 단위소자 또는 상기 금속배선을 노출시키는 금속배선 콘택홀(59)을 형성한다.Next, a photoresist pattern (not shown) is formed by an exposure and development process using a metal wiring contact mask (not shown), and the lower insulating layer 53 is etched using the mask to expose the unit device or the metal wiring. A metal wiring contact hole 59 is formed.
그리고, 상기 콘택홀(59)을 포함한 전체표면상부에 글루층(57)을 일정두께 형성한다. 이때, 상기 글루층(57)은 티타늄과 티타늄질화막의 적층구조로 형성한다.The glue layer 57 is formed on the entire surface including the contact hole 59 at a predetermined thickness. At this time, the glue layer 57 is formed in a stacked structure of titanium and titanium nitride film.
그리고, 상기 콘택홀(59)을 매립하는 텅스텐층(61)을 전체표면상부에 형성한다. (도 1a)A tungsten layer 61 filling the contact hole 59 is formed on the entire surface. (FIG. 1A)
그 다음, 상기 하부절연층(53)이 노출되도록 상기 텅스텐층(61)을 평탄화식각하여 상기 금속배선 콘택홀(59)을 매립하는 콘택플러그를 형성한다. (도 1b)Next, the tungsten layer 61 is planarized to expose the lower insulating layer 53 to form a contact plug to fill the metal wiring contact hole 59. (FIG. 1B)
그리고, 전체표면상부에 장벽금속층(65)과 알루미늄합금(67) 및 반사방지막(69)을 각각 일정두께 형성한다. 이때, 상기 장벽금속층(65)과 반사방지막(69)은 티타늄과 티타늄질화막의 적층구조로 형성한다. (도 1c)Then, the barrier metal layer 65, the aluminum alloy 67, and the anti-reflection film 69 are respectively formed on the entire surface. At this time, the barrier metal layer 65 and the anti-reflection film 69 are formed in a stacked structure of titanium and titanium nitride film. (FIG. 1C)
그리고, 상기 반사방지막(69) 상부에 금속배선 마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(71)을 형성한다. (도 1d)The photoresist pattern 71 is formed on the anti-reflection film 69 by an exposure and development process using a metal wiring mask (not shown). (FIG. 1D)
그리고, 상기 감광막패턴(71)을 마스크로하여 상기 상기 반사방지막(69), 알루미늄합금(67) 및 장벽금속층(65)을 식각하여 상기 콘택플러그에 접속되는 금속배선을 형성한다.The anti-reflection film 69, the aluminum alloy 67, and the barrier metal layer 65 are etched using the photoresist pattern 71 as a mask to form a metal wiring connected to the contact plug.
이때, 상기 식각공정시 수반되는 과도식각공정으로 인하여 하부절연층(53)이 ⓒ 만큼 식각되거나 라인 엔드 쇼트닝 현상에 의하여 금속배선 선폭이 양끝에서 각각 ⓔ, ⓕ 만큼 식각되어 결과적으로 ⓓ 부분과 같이 콘택플러그가 노출되는 현상이 유발된다. (도 1e)At this time, the lower insulating layer 53 is etched by ⓒ due to the transient etching process involved in the etching process, or the line width of the metal wiring lines is etched by ⓔ and ⓕ at both ends, respectively, by line end shortening, resulting in contact with ⓓ part. The plug may be exposed. (FIG. 1E)
상기한 바와같이 종래기술에 따른 반도체소자의 금속배선 형성방법은, 과도식각공정으로 인하여 콘택플러그가 손상되는 경우가 유발되고 그에 따른 반도체소자의 특성 및 신뢰성이 저하되는 문제점이 있다.As described above, the metal wiring forming method of the semiconductor device according to the related art has a problem in that a contact plug is damaged due to a transient etching process, and thus the characteristics and reliability of the semiconductor device are deteriorated.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여,The present invention to solve the above problems of the prior art,
콘택플러그가 형성된 부분을 노출시키고 그 상부를 장벽금속층으로 형성한 다음, 그 상부에 알루미늄합금을 형성하고 이를 패터닝함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.A semiconductor device which exposes a portion where a contact plug is formed and forms an upper portion thereof as a barrier metal layer, and then forms an aluminum alloy on the upper portion thereof and patterns it, thereby improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device. The purpose is to provide a method for forming metal wiring.
도 1a 내지 도 1e 는 종래기술에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1A to 1E are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2i 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.2A to 2I are cross-sectional views illustrating a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11,51 : 반도체기판 13,53 : 하부절연층11,51: semiconductor substrate 13,53: lower insulating layer
17,57 : 글루층 19,59 : 금속배선 콘택홀17,57: glue layer 19,59: metal wiring contact hole
21,61 : 텅스텐막 23 : 층간절연막21,61 tungsten film 23 interlayer insulating film
25,71 : 감광막패턴 27,65 : 장벽금속층25,71 photoresist pattern 27,65 barrier metal layer
29,67 : 알루미늄합금 31,69 : 반사방지막29,67: Aluminum alloy 31,69: Anti-reflection film
33 : 다른 감광막패턴 35 : 다른 층간절연막33: other photosensitive film pattern 35: another interlayer insulating film
37 : 비아 콘택홀37: Via Contact Hole
ⓐ : 본 발명에 따른 하부절연층 로스Ⓐ: lower insulation layer loss according to the present invention
ⓑ : 층간절연막 로스Ⓑ: interlayer insulation film loss
ⓒ : 종래기술에 따른 하부절연층 로스Ⓒ: Loss of lower insulation layer according to the prior art
ⓓ : 콘택플러그가 손상된 부분Ⓓ: damaged contact plug
ⓔ, ⓕ : 금속배선이 식각된 끝부분Ⓔ, ⓕ: end of metal wire etched
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,
금속배선 콘택홀이 형성된 하부절연층을 포함한 전체표면상부에 텅스텐을 증착하는 공정과,Depositing tungsten on the entire surface including the lower insulating layer on which metal wiring contact holes are formed;
상기 텅스텐을 평탄화식각하되, 하부절연층을 과도식각하여 상기 콘택홀을 매립하는 돌출된 텅스텐으로 콘택플러그가 형성되는 공정과,Forming a contact plug with flattened etching of the tungsten and overetching a lower insulating layer to form a contact plug with protruding tungsten filling the contact hole;
전체표면상부에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film over the entire surface;
금속배선으로 예정된 영역의 상기 층간절연막을 식각하는 공정과,Etching the interlayer insulating film in a region predetermined by metal wiring;
전체표면상부에 장벽금속층, 금속배선 물질층 및 반사방지막을 적층하는 공정과,Laminating a barrier metal layer, a metal wiring material layer, and an antireflection film on the entire surface;
금속배선 마스크를 이용하여 상기 장벽금속층, 금속배선 물질층 및 반사방지막을 식각함으로써 상기 콘택플러그에 접속되는 금속배선을 형성하는 공정을 포함하는 것과,Forming a metal wiring connected to the contact plug by etching the barrier metal layer, the metal wiring material layer and the anti-reflection film using a metal wiring mask;
상기 콘택플러그는 텅스텐으로 형성하는 것과,The contact plug is formed of tungsten,
상기 평탄화식각공정은 상기 하부절연층의 500 ∼ 1000 Å 이 식각되는 CMP 방법으로 실시하는 것과,The planarization etching process may be performed by a CMP method in which 500 to 1000 GPa of the lower insulating layer is etched.
상기 장벽금속층 및 반사방지막은 티타늄막과 티타늄질화막의 적층구조로 형성하는 것과,The barrier metal layer and the anti-reflection film are formed of a laminated structure of titanium film and titanium nitride film,
상기 금속배선 물질층은 400 ∼ 1000 ℃ 온도에서 알루미늄합금으로 형성하는 것을 특징으로 한다.The metal wiring material layer is formed of an aluminum alloy at a temperature of 400 ~ 1000 ℃.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2i 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A to 2I are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 하부절연층(13)을 형성한다. 이때, 상기 하부절연층(13)은 워드라인, 비트라인, 캐패시터 등의 단위 소자가 형성된 것이고, 상기 단위 소자들 상부에 금속배선이 형성되어 있을 수도 있다.First, a lower insulating layer 13 is formed on the semiconductor substrate 11. In this case, the lower insulating layer 13 may be formed of a unit element such as a word line, a bit line, a capacitor, or the like, and a metal wiring may be formed on the unit elements.
그 다음, 금속배선 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(도시안됨)을 형성하고 이를 마스크로하여 상기 하부절연층(13)을 식각하여 상기 단위소자 또는 상기 금속배선을 노출시키는 금속배선 콘택홀(19)을 형성한다.Next, a photoresist pattern (not shown) is formed by an exposure and development process using a metal wiring contact mask (not shown), and the lower insulating layer 13 is etched using the mask to expose the unit device or the metal wiring. A metal wiring contact hole 19 is formed.
그리고, 상기 콘택홀(19)을 포함한 전체표면상부에 글루층(17)을 일정두께 형성한다. 이때, 상기 글루층(17)은 티타늄과 티타늄질화막의 적층구조로 형성한다.Then, a glue layer 17 is formed on the entire surface including the contact hole 19 at a predetermined thickness. At this time, the glue layer 17 is formed in a stacked structure of titanium and titanium nitride film.
그리고, 상기 콘택홀(19)을 매립하는 텅스텐층(21)을 전체표면상부에 형성한다. (도 2a)A tungsten layer 21 filling the contact hole 19 is formed on the entire surface. (FIG. 2A)
그 다음, 상기 하부절연층(13)이 노출되도록 상기 텅스텐층(21)을 평탄화식각하여 상기 금속배선 콘택홀(19)을 매립하는 콘택플러그를 형성한다.Next, the tungsten layer 21 is planarized to expose the lower insulating layer 13 to form a contact plug to fill the metal wiring contact hole 19.
이때, 상기 평탄화식각공정은 상기 하부절연층(13)이 ⓐ 인 500 ∼ 1000 Å 정도 리세스 되도록 실시하여 상기 콘택플러그가 돌출되도록 형성한다. (도 2b)In this case, the planarization etching process is performed such that the lower insulating layer 13 is recessed about 500 to 1000 인, which is ⓐ, so that the contact plug protrudes. (FIG. 2B)
그 다음, 전체표면상부에 층간절연막(23)을 형성하고 그 상부에 제1금속배선 마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(25)을 형성한다. 이때, 상기 감광막패턴(25)은 일반적인 금속배선 마스크와 상이 반대인 제1 금속배선 마스크를 이용하여 금속배선이 형성될 부분을 노출시키도록 형성된 것이다.Next, the interlayer insulating film 23 is formed on the entire surface, and the photosensitive film pattern 25 is formed by an exposure and development process using a first metal wiring mask (not shown). In this case, the photoresist layer pattern 25 is formed to expose a portion where the metal wiring is to be formed by using a first metal wiring mask that is opposite to the general metal wiring mask.
여기서, 상기 층간절연막(23)은 1000 ∼ 8000 Å 두께로 형성한다.(도 2c, 도 2d)Here, the interlayer insulating film 23 is formed to have a thickness of 1000 to 8000 GPa (FIGS. 2C and 2D).
그 다음, 상기 감광막패턴(25)을 마스크로하여 상기 층간절연막(23)을 식각함으로써 상기 콘택플러그를 돌출시킨다. (도 2e)Next, the contact plug is protruded by etching the interlayer insulating film 23 using the photosensitive film pattern 25 as a mask. (FIG. 2E)
그리고, 상기 감광막패턴(25)을 제거하고 전체표면상부에 장벽금속층(27), 알루미늄합금(29) 및 반사방지막(31)을 적층한다.Then, the photoresist layer pattern 25 is removed, and a barrier metal layer 27, an aluminum alloy 29, and an antireflection film 31 are laminated on the entire surface.
이때, 상기 장벽금속층(27)과 반사방지막(31)은 티타늄막과 티타늄질화막의 적층구조로 형성한다.In this case, the barrier metal layer 27 and the anti-reflection film 31 are formed in a stacked structure of a titanium film and a titanium nitride film.
그리고, 상기 알루미늄합금(29)은 400 ∼ 1000 ℃ 온도에서 증착하여 증착되는 알루미늄합금(29)의 중앙부분과 끝부분의 단차를 완화시킬 수 있다. (도 2f)In addition, the aluminum alloy 29 may alleviate the step difference between the center portion and the end portion of the aluminum alloy 29 deposited by depositing at a temperature of 400 to 1000 ° C. (FIG. 2F)
그 다음에, 상기 반사방지막(31) 상부에 다른 감광막패턴(33)을 형성한다. 이때, 상기 다른 감광막패턴(33)은 금속배선으로 예정된 부분만을 남기는 제2금속배선 마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한 것이다.Next, another photosensitive film pattern 33 is formed on the anti-reflection film 31. In this case, the other photoresist layer pattern 33 is formed by an exposure and development process using a second metal wiring mask (not shown) that leaves only a predetermined portion of the metal wiring.
그리고, 상기 다른 감광막패턴(33)을 마스크로 하여 상기 반사방지막(31), 알루미늄합금(29) 및 장벽금속층(27)을 식각함으로써 상기 콘택플러그에 접속되는 금속배선을 형성한다. (도 2g)The anti-reflection film 31, the aluminum alloy 29, and the barrier metal layer 27 are etched using the other photoresist pattern 33 as a mask to form a metal wiring connected to the contact plug. (Fig. 2g)
그 다음, 상기 감광막패턴(33)을 제거하고 전체표면상부에 다른 층간절연막(37)을 증착하고 이를 평탄화식각하여 평탄화시킨다. (도 2h)Next, the photoresist pattern 33 is removed, and another interlayer insulating layer 37 is deposited on the entire surface of the photoresist pattern 33 and flattened by etching. (FIG. 2H)
그리고, 상기 다른 층간절연막(37) 상부에 비아 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 금속배선을 노출시키는 비아콘택홀(41)을 형성한다. (도 2i)A via contact hole 41 is formed on the other interlayer insulating layer 37 to expose the metal wiring by an etching process using a via contact mask (not shown). (FIG. 2i)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 콘택플러그의 손상없이 금속콘택 및 비아콘택을 용이하게 형성함으로써 안정된 특성을 갖는 금속배선을 형성할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the method for forming the metal wiring of the semiconductor device according to the present invention enables the formation of metal wiring with stable characteristics by easily forming the metal contact and the via contact without damaging the contact plug. There is an effect that can improve the reliability.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980061992A KR20000045434A (en) | 1998-12-30 | 1998-12-30 | Method for fabricating metal wiring |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980061992A KR20000045434A (en) | 1998-12-30 | 1998-12-30 | Method for fabricating metal wiring |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100886703B1 (en) * | 2002-10-30 | 2009-03-04 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100886703B1 (en) * | 2002-10-30 | 2009-03-04 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor device |
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