KR100505605B1 - Method for forming capacitor having metal-insulator-metal structure - Google Patents
Method for forming capacitor having metal-insulator-metal structure Download PDFInfo
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- KR100505605B1 KR100505605B1 KR10-1998-0022384A KR19980022384A KR100505605B1 KR 100505605 B1 KR100505605 B1 KR 100505605B1 KR 19980022384 A KR19980022384 A KR 19980022384A KR 100505605 B1 KR100505605 B1 KR 100505605B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 42
- 239000002184 metal Substances 0.000 title claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 35
- 230000008569 process Effects 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 230000009977 dual effect Effects 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 36
- 239000010936 titanium Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
커패시터의 유전체막의 내압 및 누설전류의 특성을 양호하게 하고 공정의 안정화를 쉽게 이룰 수 있는 MIM(Metal-Insulator-Metal) 구조의 커패시터의 형성방법을 개시한다. 본 발명은, 단위소자가 형성된 반도체 기판 위에 하부 도전막, 유전체막 및 상부 도전막을 순차적으로 증착하는 단계와, 상부 도전막을 패터닝하여 상부 전극 패턴을 형성하는 단계와, 유전체막 및 하부도전막을 차례로 패터닝하여 유전체막 패턴 및 커패시터의 하부전극과 하부금속배선으로 동시에 사용되는 하부도전막 패턴을 형성하는 단계를 구비한다. 본 발명에 의해, 커패시터의 유전체막이 손상되지 아니하고 유전체막 두께를 균일하게 유지함으로써, 커패시터의 유전체막의 내압 및 누설전류의 특성을 양호하게 하고 공정의 안정화를 쉽게 이룰 수 있다.Disclosed is a method of forming a capacitor having a metal-insulator-metal (MIM) structure that can improve the characteristics of the breakdown voltage and the leakage current of a dielectric film of a capacitor, and can easily stabilize a process. According to the present invention, a method of sequentially depositing a lower conductive film, a dielectric film, and an upper conductive film on a semiconductor substrate on which a unit device is formed, forming an upper electrode pattern by patterning the upper conductive film, and patterning the dielectric film and the lower conductive film Forming a lower conductive film pattern which is simultaneously used as a dielectric film pattern and a lower electrode and a lower metal wiring of the capacitor. According to the present invention, by maintaining the dielectric film thickness uniformly without damaging the dielectric film of the capacitor, the characteristics of the breakdown voltage and the leakage current of the dielectric film of the capacitor can be improved and the process can be easily stabilized.
Description
본 발명은 커패시터의 형성방법에 관한 것으로서, 상세하게는 금속층-절연층-금속층(Metal-Insulator-Metal:이하 MIM이라 한다) 구조를 갖는 커패시터 제조방법에 관한 것이다.The present invention relates to a method of forming a capacitor, and more particularly, to a method of manufacturing a capacitor having a metal layer-insulating layer-metal layer (hereinafter referred to as MIM) structure.
오늘날 반도체 소자의 제조 공정이 미세화 및 고집적화되고 아날로그 소자의 정밀도가 증가하고 있다. 이에 따라, 전압변화에 따른 커패시턴스의 변화가 매우 작은 커패시터가 요구되고 있다. 하지만, 상부전극이나 하부전극의 일부 또는 전체를 폴리실리콘으로 구성하고 있는 기존의 반도체 소자의 제조 방법에서는 특성의 한계를 보이고 있다. 이러한 한계를 극복하기 위하여, MIM 구조의 커패시터의 제조방법을 개발하고 있는 추세이다.Today, the manufacturing process of semiconductor devices is becoming more and more compact and the precision of analog devices is increasing. Accordingly, there is a demand for a capacitor having a very small change in capacitance caused by voltage change. However, the conventional method of manufacturing a semiconductor device in which part or all of an upper electrode or a lower electrode is made of polysilicon shows limitations of characteristics. In order to overcome this limitation, there is a trend to develop a manufacturing method of the capacitor of the MIM structure.
MIM 구조의 커패시터는 WSix, Al 또는 Ti와 TiN의 이중구조 등을 전극으로 사용할 수 있으며, Ti, TiN 및 Al의 다층구조는 기존의 다층 금속배선공정을 사용할 수 있다. 따라서, MIM 구조의 커패시터는 제조공정 및 단가면에서 잇점이 있다. The capacitor of the MIM structure may use WSix, Al, or a dual structure of Ti and TiN as an electrode, and the multilayer structure of Ti, TiN, and Al may use a conventional multilayer metallization process. Therefore, the capacitor of the MIM structure has advantages in manufacturing process and unit cost.
앞서 살펴 본 MIM 구조의 커패시터를 형성하기 위하여, 먼저 통상의 단위소자의 제조공정을 진행한 반도체 기판의 상부에 하부전극으로 사용되는 하부 금속배선을 형성한다. 그리고, 층간 절연막을 증착한 후, 사진공정과 건식식각공정을 이용하여 커패시터를 형성하고자 하는 영역을 패터닝하여 층간절연막 패턴을 형성한다. 다음, 반도체 기판의 상부에 유전체막을 증착한다. 이때, 층간 절연막을 패터닝하기 위한 건식식각에 의해 하부 금속배선의 표면이 손상받게 되고, 그 결과 구석부위 등에서 유전체막의 증착두께의 균일도가 떨어지게 된다.In order to form the capacitor of the MIM structure described above, first, a lower metal wiring, which is used as a lower electrode, is formed on an upper portion of a semiconductor substrate in which a conventional unit device manufacturing process is performed. After the deposition of the interlayer insulating film, an area to form a capacitor is patterned by using a photo process and a dry etching process to form an interlayer insulating film pattern. Next, a dielectric film is deposited on top of the semiconductor substrate. At this time, the surface of the lower metal wiring is damaged by the dry etching for patterning the interlayer insulating film, and as a result, the uniformity of the deposition thickness of the dielectric film is reduced at corners or the like.
다음, 하부금속배선의 표면을 식각저지층으로 하여 유전체막과 층간절연막패턴을 식각하여 하부금속배선의 일부를 노출시키는 비아(via) 콘택홀을 형성하고, 비아 콘택홀 부위의 자연산화막 식각공정을 진행한다. 그리고, 상부전극으로 사용되는 상부 금속배선을 형성한다. 이때, 자연산화막 식각공정을 진행하는 동안에 커패시터 부위에 증착되어 있는 유전체막이 한번 더 손상받게 된다. 따라서, 커패시터의 유전체막이 많이 손상되고 유전체막의 두께가 균일하지 않게 됨에 따라, 유전체막의 두께나 균일성에 의해 영향을 받는 커패시터의 내압, 누설전류 및 전압 의존성이 웨이퍼의 위치에 따라 나빠지게 된다. 이러한 현상들은 전체적인 제품 특성이나 수율을 떨어뜨리는 요인으로 작용되는 문제점이 있다. Next, a via contact hole is formed to expose a portion of the lower metal interconnection by etching the dielectric layer and the interlayer insulating layer pattern by using the surface of the lower metal interconnection as an etch stop layer. Proceed. Then, the upper metal wiring used as the upper electrode is formed. At this time, the dielectric film deposited on the capacitor portion is damaged once more during the natural oxide film etching process. Therefore, as the dielectric film of the capacitor is much damaged and the thickness of the dielectric film is not uniform, the breakdown voltage, leakage current, and voltage dependence of the capacitor affected by the thickness or uniformity of the dielectric film become worse depending on the position of the wafer. These phenomena have a problem that acts as a factor that reduces the overall product characteristics or yield.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 커패시터의 제조공정시 하부전극 및 유전체막이 손상되지 않게 하고 유전체막의 두께를 균일하게 유지함으로써, 커패시터의 유전체막의 내압 및 누설전류의 특성을 양호하게 하고 공정의 안정화를 쉽게 이룰 수 있는 MIM 구조의 커패시터의 형성방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the characteristics of the breakdown voltage and leakage current of the dielectric film of the capacitor are good by preventing the lower electrode and the dielectric film from being damaged and maintaining the thickness of the dielectric film uniformly during the manufacturing process of the capacitor. The purpose of the present invention is to provide a method of forming a capacitor with a MIM structure that can easily stabilize the process.
상기 목적을 달성하기 위한 본 발명의 금속막-절연막-금속막 구조의 커패시터의 형성방법은, 단위소자가 형성된 반도체 기판 위에 하부 도전막, 유전체막 및 상부 도전막을 순차적으로 증착하는 단계와, 상부 도전막을 패터닝하여 상부 전극 패턴을 형성하는 단계와, 유전체막 및 하부도전막을 차례로 패터닝하여 유전체막 패턴 및 커패시터의 하부전극과 하부금속배선으로 동시에 사용되는 하부도전막 패턴을 형성하는 단계를 구비하는 것을 특징으로 한다. 이때, 상부 전극 패턴을 형성하는 공정시 상부 전극 패턴과 접촉하는 영역 이외의 영역에 형성되어 있는 상기 유전체막이 상기 하부도전막이 식각에 의해 손상되는 것을 방지하는 식각방지막으로 작용하는 것이 바람직하다.In order to achieve the above object, a method of forming a capacitor having a metal film-insulating film-metal film structure includes sequentially depositing a lower conductive film, a dielectric film, and an upper conductive film on a semiconductor substrate on which a unit device is formed; Patterning the film to form an upper electrode pattern; and sequentially patterning the dielectric film and the lower conductive film to form a dielectric film pattern and a lower conductive film pattern that is simultaneously used as the lower electrode and the lower metal wiring of the capacitor. It is done. In this case, during the process of forming the upper electrode pattern, the dielectric film formed in a region other than the region in contact with the upper electrode pattern may serve as an etch stop layer preventing the lower conductive layer from being damaged by etching.
하부도전막 패턴을 형성하는 단계 이후, 반도체 기판 전면에 절연막을 증착하는 단계와, 상부전극패턴을 식각저지층으로 하여 절연막을 식각하여 상부전극패턴의 일부를 노출시키는 비아를 형성하는 단계 및 비아를 매립하는 상부 금속 배선 패턴을 형성하는 단계를 더 구비하는 것이 바람직하다. 상부 전극 패턴의 일부를 노출시키는 비아를 형성하는 단계는 절연막과 유전체막을 식각하여 하부도전막 패턴중 하부전극이 아니라 하부 금속 배선으로 기능하는 영역을 노출시키는 배선 연결용 비아도 형성하는 단계와 동시에 진행되는 것이 바람직하다.After forming the lower conductive film pattern, depositing an insulating film on the entire surface of the semiconductor substrate; forming a via to expose a portion of the upper electrode pattern by etching the insulating film using the upper electrode pattern as an etch stop layer; and Preferably, the method further includes forming a buried upper metal wiring pattern. The step of forming a via exposing a portion of the upper electrode pattern is performed at the same time as the step of etching the insulating film and the dielectric film to form a wiring connection via exposing a region serving as a lower metal wiring rather than the lower electrode in the lower conductive film pattern. It is desirable to be.
본 발명에 의해, 유전체막이 손상되지 아니하고 유전체막 두께를 균일하게 유지함으로써, 커패시터의 유전체막의 내압 및 누설전류의 특성을 양호하게 하고 공정의 안정화를 쉽게 이룰 수 있다.According to the present invention, by maintaining the dielectric film thickness uniformly without damaging the dielectric film, the characteristics of the breakdown voltage and leakage current of the dielectric film of the capacitor can be improved and the process can be easily stabilized.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시예를 상세히 설명한다. 그러나 본 발명이 하기 실시예에 국한되는 것으로 해석되어져서는 안된다. 또한, 도면에서 층이나 영역들의 두께는 설명을 명확하게 하기 위하여 과장된 것이다. 도면에서 동일한 참조부호는 동일한 구성요소를 나타낸다. 또한 어떤 층이 다른 층 또는 기판의 "상부"에 있다고 기재된 경우, 상기 어떤 층이 상기 다른 층 또는 기판의 상부에 직접 접촉하면서 존재할 수도 있고, 그 사이에 다른 제3의 층이 개재될 수도 있다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention should not be construed as limited to the following examples. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements. In addition, where a layer is described as being on the "top" of another layer or substrate, the layer may be present in direct contact with the top of the other layer or substrate, with another third layer interposed therebetween.
도 1은 본 발명의 일실시예에 따라 커패시터를 형성하기 위한 레이 아웃도이다. 참조부호 10은 반도체 기판을, 12는 하부전극 및 하부 금속 배선 패턴을, 14는 상부전극 패턴을, 16은 비아콘택홀 패턴을, 18은 상부 금속 배선 패턴을 각각 나타낸다. 1 is a layout diagram for forming a capacitor according to an embodiment of the present invention. Reference numeral 10 denotes a semiconductor substrate, 12 a lower electrode and a lower metal wiring pattern, 14 an upper electrode pattern, 16 a via contact hole pattern, and 18 an upper metal wiring pattern.
도 2 내지 도 6은 본 발명의 실시예에 따른 커패시터의 제조 공정을 순차적으로 도시한 단면도들이다. 2 to 6 are cross-sectional views sequentially illustrating a manufacturing process of a capacitor according to an embodiment of the present invention.
도 2를 참조하면, 단위소자(미도시)가 형성된 반도체 기판(20) 위에 하부 금속배선 및 커패시터 하부전극으로 동시에 사용되는 하부 도전막(22), 유전체막(24) 및 상부 도전막(26)을 순차적으로 증착한다. 이때, 하부 도전막(22)은 질화티타늄막(Titanium nitride:이하 TiN이라 한다)이며, 50Å - 2000Å의 두께범위로 형성하는 것이 바람직하다. 유전체막(24)은 산화막, 질화막, 또는 산화막 및 질화막의 이중구조로, 100Å - 2000Å의 두께로 형성되는 것이 바람직하다. 또한, 상부 도전막(26)은 Ti, TiN, Ti 및 TiN의 이중구조, 또는 Ti,TiN 및 Al의 다층구조로 형성되는 것이 바람직하다. 그리고, 상부전극패턴(도3의 26' 참고)과 상부 금속배선패턴(도6의 62 참고)을 연결하는 후속 콘택홀 형성공정에 있어서 충분한 식각마진을 얻기 위하여, 상부 도전막(26)의 두께는 50Å - 7000Å의 범위로 형성하는 것이 바람직하다.Referring to FIG. 2, a lower conductive layer 22, a dielectric layer 24, and an upper conductive layer 26 simultaneously used as a lower metal wiring and a capacitor lower electrode on a semiconductor substrate 20 on which a unit device (not shown) is formed. Are deposited sequentially. At this time, the lower conductive film 22 is a titanium nitride film (hereinafter referred to as TiN), and preferably formed in a thickness range of 50 kV to 2000 kV. The dielectric film 24 has an oxide film, a nitride film, or a dual structure of an oxide film and a nitride film, and is preferably formed to a thickness of 100 kPa to 2000 kPa. The upper conductive film 26 is preferably formed of a dual structure of Ti, TiN, Ti, and TiN, or a multilayer structure of Ti, TiN, and Al. Then, in order to obtain sufficient etching margin in the subsequent contact hole forming process connecting the upper electrode pattern (see 26 'in FIG. 3) and the upper metal wiring pattern (see 62 in FIG. 6), the thickness of the upper conductive film 26 Is preferably formed in the range of 50 kPa to 7000 kPa.
도 3을 참조하면, 상부 도전막(26)을 패터닝하여 상부전극패턴(26')을 형성한다. 이때, 커패시터의 하부전극과 하부 금속배선으로 사용되는 하부 도전막(22)의 표면은 그 위에 증착된 유전체막(24)에 의해 보호되고 식각되지 않으며, 유전체막(24')중 커패시터를 형성하는 부분 또한 상부 전극 패턴(26')에 의해 보호된다. 이는 종래의 커패시터 제조공정에서 하부전극이 과다하게 식각되어 하부전극 위에 증착되는 유전체막 두께의 균일도가 떨어지는 문제점을 개선하며, 유전체막 또한 식각공정에 의해 손상되지 않는다. 따라서 유전체막(24) 두께의 균일성을 유지할 수 있게 되고, 그 결과 커패시터의 유전체막(24)의 내압과 누설전류의 특성이 양호하게 된다. Referring to FIG. 3, the upper conductive layer 26 is patterned to form an upper electrode pattern 26 ′. At this time, the surface of the lower conductive layer 22 used as the lower electrode of the capacitor and the lower metal wiring is protected and not etched by the dielectric layer 24 deposited thereon, and forms a capacitor in the dielectric layer 24 '. The portion is also protected by the upper electrode pattern 26 '. This improves the problem that the lower electrode is excessively etched in the conventional capacitor manufacturing process and the uniformity of the thickness of the dielectric film deposited on the lower electrode is inferior, and the dielectric film is not damaged by the etching process. Therefore, the uniformity of the thickness of the dielectric film 24 can be maintained, and as a result, the characteristics of the breakdown voltage and the leakage current of the dielectric film 24 of the capacitor become good.
도 4를 참조하면, 상부전극패턴(26')을 형성한 후, 사진 식각공정을 이용하여 하부 도전막(22)과 유전체막(24)을 패터닝하여 하부전극패턴 및 하부금속배선 패턴(22')과 유전체막 패턴(24')을 형성한다. Referring to FIG. 4, after forming the upper electrode pattern 26 ′, the lower conductive layer 22 and the dielectric layer 24 are patterned using a photolithography process to form the lower electrode pattern and the lower metallization pattern 22 ′. ) And the dielectric film pattern 24 'are formed.
도 5를 참조하면, 앞서 설명한 결과물 전면에 절연막(50)을 증착한다. 다음, 상부전극패턴(26')을 식각저지층으로 하여, 절연막(50)을 식각하여 상부전극패턴(26')을 노출시키는 비아 콘택홀(52)을 형성한다. 이 콘택홀(52)은 상부전극패턴(26')을 후속공정에서 형성되는 상부 금속배선패턴(62)과 연결하기 위한 것이다. 콘택홀(52)을 형성하기 위한 식각공정에 있어서, 상부전극패턴(26')의 과식각에 의한 공정 마진의 감소는 상부 도전막의 종류 및 상부 도전막의 두께 증가를 통하여 쉽게 해결할 수 있다. 콘택홀(52)을 형성시에, 하부 금속배선패턴(22')을 식각저지층으로 하여 절연막(50) 및 유전체막 패턴(24')을 식각하여, 하부 금속배선패턴(22')을 노출시키고 후속공정에서 형성되는 상부 금속배선패턴(62)과 연결하는 비아 콘택홀(54) 또한 동시에 형성하는 것이 바람직하다.Referring to FIG. 5, an insulating film 50 is deposited on the entire surface of the resultant material described above. Next, the via contact hole 52 exposing the upper electrode pattern 26 ′ is formed by etching the insulating layer 50 by using the upper electrode pattern 26 ′ as an etch stop layer. The contact hole 52 is for connecting the upper electrode pattern 26 'with the upper metal wiring pattern 62 formed in a subsequent process. In the etching process for forming the contact hole 52, the reduction of the process margin due to the overetching of the upper electrode pattern 26 'can be easily solved by increasing the type of the upper conductive layer and the thickness of the upper conductive layer. When the contact hole 52 is formed, the insulating layer 50 and the dielectric layer pattern 24 'are etched using the lower metal wiring pattern 22' as an etch stop layer to expose the lower metal wiring pattern 22 '. The via contact hole 54 is also formed at the same time as the upper metal wiring pattern 62 formed in a subsequent process.
도 6을 참조하면, 콘택홀들(52,54)이 형성된 반도체 기판(20) 위에 콘택플러그용 도전막, 예컨대 텅스텐(W)을 증착한 후, 평탄화하여 콘택플러그(60)를 형성한다. 다음, 상부 금속배선용 도전막을 증착하고, 사진 식각공정을 이용하여 상부 금속배선용 도전막을 패터닝하여 상부 금속 배선 패턴(62)을 형성한다. Referring to FIG. 6, a contact plug conductive film, such as tungsten (W), is deposited on the semiconductor substrate 20 on which the contact holes 52 and 54 are formed, and then planarized to form the contact plug 60. Next, the upper metal wiring conductive layer is deposited and the upper metal wiring conductive layer is patterned by using a photolithography process to form the upper metal wiring pattern 62.
이상 실시예를 들어 본 발명에 대해 설명하였으나, 본발명은 상술한 실시예에 한정되는 것은 아니며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위하여 제공되는 것으로서, 본 발명의 기술사상 및 범위내에서 당 분야의 통상의 지식을 가진 자에 의하여 각종 변형 및 개량이 가능함은 명백하다.Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above-described embodiments, only these embodiments are intended to complete the disclosure of the present invention, and the scope of the invention to those skilled in the art. It is apparent that various modifications and improvements are possible to those skilled in the art without departing from the spirit and scope of the present invention as provided to fully inform the present invention.
이상에서 살펴본 바와 같이 본 발명에 따른 커패시터의 형성방법은, 커패시터의 제조공정시 하부 도전막, 유전체막 및 상부 도전막을 차례로 증착한 후 상부전극패턴을 형성하여 유전체막이 손상되지 아니하고 유전체막 두께를 균일하게 유지함으로써, 커패시터의 유전체막의 내압 및 누설전류의 특성을 양호하게 하고 공정의 안정화를 쉽게 이룰 수 있다.As described above, the method of forming a capacitor according to the present invention includes depositing a lower conductive layer, a dielectric layer, and an upper conductive layer in sequence during the manufacturing process of the capacitor, and then forming an upper electrode pattern so that the dielectric layer is not damaged and the dielectric layer thickness is uniform. By keeping it stable, the characteristics of the breakdown voltage and the leakage current of the dielectric film of the capacitor can be improved and the stabilization of the process can be easily achieved.
도 1은 본 발명의 실시예에 따른 금속막-절연막-금속막 구조를 갖는 커패시터의 평면도이다.1 is a plan view of a capacitor having a metal film-insulating film-metal film structure according to an embodiment of the present invention.
도2 내지 도 6은 본 발명의 실시예에 따른 금속막-절연막-금속막 구조를 갖는 커패시터 제조방법을 순차적으로 도시한 단면도들이다.2 to 6 are cross-sectional views sequentially illustrating a method of manufacturing a capacitor having a metal film-insulating film-metal film structure according to an embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10,20:반도체 기판 14:커패시터10, 20: semiconductor substrate 14: capacitor
16:콘택 22:하부 도전막16: Contact 22: Lower conductive film
12,22':하부 도전막패턴 24:유전체막12,22 ': Lower conductive film pattern 24: Dielectric film
24':유전체막 패턴 26:상부 도전막24 ': Dielectric film pattern 26: Upper conductive film
26':상부전극패턴 50:절연막26 ': upper electrode pattern 50: insulating film
52,54:콘택홀 60:콘택플러그52, 54: Contact hole 60: Contact plug
18,62:상부 금속배선패턴18,62: upper metal wiring pattern
Claims (9)
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| KR100370131B1 (en) * | 2000-10-17 | 2003-02-05 | 주식회사 하이닉스반도체 | Metal-Insulator-Metal Capacitor and Method for Fabricating the Same |
| KR100459937B1 (en) * | 2002-06-11 | 2004-12-03 | 동부전자 주식회사 | Method for manufacturing semiconductor device with mim type capacitor |
| KR100744038B1 (en) * | 2002-07-19 | 2007-07-30 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
| KR100750051B1 (en) * | 2002-10-30 | 2007-08-16 | 매그나칩 반도체 유한회사 | Method of forming an MIM structure |
| KR20060006592A (en) * | 2004-07-16 | 2006-01-19 | 매그나칩 반도체 유한회사 | Metal-insulator-metal capacitor and forming method thereof |
| KR100682246B1 (en) * | 2005-04-30 | 2007-02-15 | 매그나칩 반도체 유한회사 | A semiconductor device and method for manufacturing the same |
| KR100707676B1 (en) * | 2005-12-30 | 2007-04-13 | 동부일렉트로닉스 주식회사 | Method for fabricating of mim capacitor |
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| JPH0613565A (en) * | 1992-02-25 | 1994-01-21 | Ramtron Internatl Corp | Method for forming ferroelectric memory circuit and method for forming ferroelectric capacitor |
| JPH07235639A (en) * | 1994-02-24 | 1995-09-05 | Matsushita Electron Corp | Semiconductor device |
| KR970003926A (en) * | 1995-06-13 | 1997-01-29 | 스기야마 가즈히코 | Semiconductor integrated circuit device and manufacturing method thereof |
| KR100187601B1 (en) * | 1994-06-28 | 1999-06-01 | 모리 가즈히로 | Semiconductor device and manufacturing method thereof |
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| JPS60105263A (en) * | 1983-11-14 | 1985-06-10 | Toshiba Corp | Semiconductor device |
| JPH0613565A (en) * | 1992-02-25 | 1994-01-21 | Ramtron Internatl Corp | Method for forming ferroelectric memory circuit and method for forming ferroelectric capacitor |
| JPH07235639A (en) * | 1994-02-24 | 1995-09-05 | Matsushita Electron Corp | Semiconductor device |
| KR100187601B1 (en) * | 1994-06-28 | 1999-06-01 | 모리 가즈히로 | Semiconductor device and manufacturing method thereof |
| KR970003926A (en) * | 1995-06-13 | 1997-01-29 | 스기야마 가즈히코 | Semiconductor integrated circuit device and manufacturing method thereof |
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