KR101043440B1 - Method for forming semiconductor device - Google Patents

Abstract

In the method of forming a semiconductor device of the present invention, a buffer layer is formed over the entire surface including a gate on a semiconductor substrate, the buffer layer is etched to expose the semiconductor substrate, an interlayer insulating film is formed on the semiconductor substrate, and then the interlayer is formed. By forming the contact hole by etching the insulating film, the problem that the lower portion of the contact hole is not opened is improved, thereby providing an effect of preventing the contact resistance from increasing.

Contact Holes, Buffer Oxides

Description

Method for forming semiconductor device

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a contact hole.

As semiconductor devices are increasingly integrated, the size of the devices is gradually reduced accordingly.

This prevents the etching from being performed correctly in the process of forming the semiconductor device in which the photolithography process is repeated, or causes defects that are bridged with neighboring patterns, thereby lowering the reliability of the semiconductor device.

Among them, there is a problem that the self-aligned contact is not formed correctly because the lower part of the landing plug is not opened.

 1A to 1F are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

As shown in FIG. 1A, the hard mask pattern (not shown) formed on the semiconductor substrate 10 having the active region 12 defined as the device isolation layer 14 is formed as an etch mask in the active region 12. After the recess is formed, the gate oxide layer 16, the polysilicon layer 18 for the gate electrode 18, and the hard mask layer 20 are sequentially formed on the entire surface, and then patterned to form the gate pattern 22.

Next, as shown in FIG. 1B, a nitride film 24 for a gate spacer and an oxide film (not shown) for a gate spacer are deposited on the semiconductor substrate 10 including the gate pattern 22.

At this time, since the gate spacer oxide film is necessary to form the ferrite channel, and the cell spacer is preferably removed, the gate spacer oxide film of the cell spacer is removed using a mask that opens only the cell spacer.

Then, a nitride film 26 for cell spacers is deposited.

Next, as shown in FIG. 1C, an interlayer insulating film 28 for forming a landing plug is formed on the entire upper surface, and a planarization etching process is performed to expose the upper portion of the hard mask layer 20. 30 is formed.

Next, as shown in FIG. 1D, a landing plug photoresist pattern (not shown) is formed on the hard mask layer 30, and the hard mask layer 30 is patterned using an etching mask to hard mask pattern (not shown). After forming the interconnection layer 28, the landing plug hole 32 is formed by etching the interlayer insulating layer 28 using a hard mask pattern (not shown) as an etching mask.

Thereafter, the hard mask pattern (not shown) is removed.

In this case, in order to form the landing plug hole 32, the interlayer insulating film 28 needs to be etched to be 3000 Å or more. In this case, the interlayer insulating film 28 may be locally etched by the difference in the etching rate because the same etching rate is not obtained in all regions. Since it is not etched, an interlayer insulating film may remain at the bottom of the landing plug hole 32 such as 'A'.

As described above, in the case where the transient etching is performed to remove the interlayer insulating film remaining under the landing plug hole 32, the loss of the cell spacer nitride film 26 and the gate spacer nitride film 24 is caused. Failure of a contact can occur.

Next, as shown in FIG. 1E, the buffer oxide layer 34 is deposited on the entire surface including the landing plug hole 32.

In this case, the buffer oxide layer 34 is formed so that the nitride layer 26 for the cell spacer is not lost in the process of exposing the active region 14 of the semiconductor substrate in a subsequent process, since the buffer oxide layer 34 is formed on the entire upper portion. In the 'A' area, unlike other areas, it has a high step.

Next, as shown in FIG. 1F, an etch back is performed on the buffer oxide layer 34 to expose the active region 14 of the semiconductor substrate.

In this case, since the buffer oxide layer 34 is formed in the region 'A' to have a higher level than other regions, the active region 14 is not exposed and does not open at all like the other regions even when the etch back is performed. There is a problem of reducing the yield.

In addition, even if the active region 14 is exposed, since the region in which the active region 14 is exposed is significantly smaller than other regions, this causes a problem of increasing the contact resistance and greatly deteriorating the characteristics of the semiconductor device.

The present invention is to solve the problem that the lower portion of the contact hole is not opened because it is not uniformly etched by the difference in the etching rate for etching the interlayer insulating film to form the contact hole.

The method of forming a semiconductor device of the present invention comprises the steps of forming a buffer layer over the whole including a gate on a semiconductor substrate, etching the buffer layer to expose the semiconductor substrate, and forming an interlayer insulating film on the semiconductor substrate; And etching the interlayer insulating layer to form contact holes.

In this case, the forming of the buffer layer may further include forming an insulating film for spacers over the entire area including the gate.

The spacer insulating film is a nitride film.

In addition, the etching of the buffer layer may be performed by an etch back process.

The etching of the buffer layer may include forming a trench by etching the buffer layer and the semiconductor substrate.

At this time, the trench is characterized in that it is formed to a depth of 100Å to 400Å,

The forming of the interlayer insulating layer may further include planarization etching of the interlayer insulating layer to expose the gate.

In addition, the forming of the interlayer insulating film may further include forming a hard mask layer on the entire surface.

The forming of the contact hole may include forming a hard mask layer pattern by etching the hard mask layer using the photoresist pattern formed on the hard mask layer as an etching mask, and forming the hard mask layer pattern as an etching mask. And etching the insulating film.

The forming of the contact hole may include a first etching step of etching the interlayer insulating film and a second etching step of removing the interlayer insulating film remaining on the semiconductor substrate.

In this case, the first etching step is characterized in that the interlayer insulating film is etched so that the thickness of the interlayer insulating film is 200 ~ 300Å.

The present invention improves the problem that the lower portion of the contact hole is not opened while preventing the self-aligned contact from failing due to the excessive etching to open the lower portion of the contact hole, thereby providing an effect of preventing the contact resistance from increasing.

According to an embodiment of the present invention, a buffer oxide film is formed over an entire surface including a conductive layer pattern formed on a semiconductor substrate, the buffer oxide film is etched to expose a semiconductor substrate, an interlayer insulating film is formed over the entire substrate, and the interlayer insulating film is etched. It includes the technical idea of forming a contact hole.

That is, since the contact hole is not formed by etching the interlayer insulating film after forming the interlayer insulating film as in the related art, the difference in the etch rate generated by etching the interlayer insulating film does not occur, thereby improving the problem that the lower part of the contact hole is not opened.

In order to explain this in detail, the following describes the technical idea of the present invention with the landing plug contact hole as an embodiment.

However, the technical spirit of the present invention because it is described as an embodiment

Modifications can be made within a range including the above.

2A to 2H are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a hard mask pattern (not shown) formed on the semiconductor substrate 100 having the active region 102 defined as the device isolation layer 104 is used as an etch mask in the active region 102. After the trench is formed, the gate oxide layer 106, the polysilicon layer 108 for the gate electrode 108, and the hard mask layer 110 are sequentially formed on the entire surface, and then patterned to form the gate pattern 112.

Next, as shown in FIG. 2B, a nitride film 114 for a gate spacer and an oxide film (not shown) for a gate spacer are deposited on the semiconductor substrate 100 including the gate pattern 112. At this time, since the gate spacer oxide film is a structure necessary for forming the ferrite channel, it is preferable to remove the gate spacer oxide film from the cell portion. Thus, the gate spacer oxide film of the cell portion is removed using a mask that opens only the cell portion. Subsequently, a nitride film 116 for cell spacers is deposited.

Next, as shown in FIG. 2C, the buffer oxide film 118 is formed over the entirety. In this case, the buffer oxide layer 118 is not formed with the same thickness because the step coverage is not good, and is thicker on the gate hard mask 110 as shown.

As shown in FIG. 2D, an etch back process is performed on the buffer oxide layer 118 to form trenches in the active region 102. In this case, a trench is formed by etching the cell spacer nitride film 116, the gate spacer nitride film 114, the gate oxide film 106, and the active region 102 of the semiconductor substrate through an etch back process. It becomes 400 microseconds or less.

As described above, since the trench is formed in the active region 102 before the landing plug region is formed, the problem that the lower region of the landing plug is not opened can be basically solved. In addition, since the interlayer insulating layer for defining the landing plug region is not formed after the formation of the gate spacer as in the related art, an etching target of 3000 μs or more required for etching the interlayer insulating layer may not be applied to form the landing plug region. In this process, a difference in etching rate may be caused in a specific region, thereby preventing the landing plug lower region from being uniformly etched. In addition, it is possible to prevent the loss of the cell spacer nitride film 116 and the gate spacer nitride film 114, which may occur due to the excessive etching of the interlayer insulating film for opening the landing plug lower region. As such, since the etching is performed to the etching target lower than the conventional etching target, even if the difference in the etching rate is almost incomplete, the etching can be uniformly performed in all areas, thereby reducing the process time.

At this time, the buffer oxide film 118 is almost removed during the etch back process, and even though some of the buffer oxide film 118 remains, the buffer oxide film 118 remains only on the upper side of the gate pattern 112, which is removed during the planarization etching of the interlayer insulating film 120 in a subsequent process. do. Even though the buffer oxide film 118 remains, it acts like a spacer of the gate pattern and thus has no effect on subsequent processes. For convenience, the buffer oxide film 118 is not shown as being all removed.

Next, as shown in FIG. 2E, after forming the interlayer insulating layer 120 on the entire surface, the planarization etching process is performed to expose the gate hard mask layer 110.

Next, as shown in FIG. 2F, the hard mask layer 122 is formed over the entire surface.

Next, as shown in FIG. 2G, the hard mask layer 122 is etched using a photoresist pattern (not shown) defining a landing plug region on the hard mask layer 122 to form a hard mask pattern. The interlayer insulating layer 120 is etched using the hard mask pattern as an etch mask to form a landing plug region. At this time, the interlayer insulating film 120 is left to have a thickness of 200 mW to 300 mW from the bottom of the trench rather than being etched all the way to the bottom of the landing plug. The reason why the interlayer insulating film 120 is left in the predetermined thickness is to prevent excessive etching of the semiconductor device by controlling over-etching during etching to form the landing plug region.

Next, as shown in FIG. 2H, the interlayer insulating layer 120 remaining under the landing plug is removed to expose the active region 102 of the semiconductor substrate 100. In this case, the interlayer insulating layer 120 may be removed by wet etching or dry etching, and the interlayer insulating layer 120 may be removed by using an etching selectivity with the nitride layer 116 for the cell spacer in the active region 102. do. Since the thickness of the interlayer insulating layer 120 remaining in the active region 102 is 300 Å or less, the etching amount is not large, so that the sidewalls of the gate pattern are not lost, thereby reducing the reliability of the semiconductor device.

Therefore, as described above, the lower portion of the landing plug may be improved by first forming the lower portion of the landing plug and then forming an interlayer insulating layer on the upper portion of the landing plug and etching the same. In addition, as the active region of the semiconductor substrate is uniformly etched, the variation of the landing plug resistance is not large, thereby improving reliability of the semiconductor device.

 1A to 1F are cross-sectional views showing a method of forming a semiconductor device according to the prior art.

2A to 2H are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

Claims (11)

Forming a buffer layer over the entirety including the gate on the semiconductor substrate; Etching the buffer layer to expose the semiconductor substrate; Forming an interlayer insulating film on the semiconductor substrate; And Etching the interlayer insulating layer to form a contact hole; Etching the buffer layer And forming a trench by etching the buffer layer and the semiconductor substrate. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Forming the buffer layer And forming an insulating film for spacers over the entire area including the gate. Claim 3 was abandoned when the setup registration fee was paid. 3. The method of claim 2, And the insulating film for spacers is a nitride film. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, Etching the buffer layer A method of forming a semiconductor device, characterized in that carried out by an etch back process. delete Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The trench is a method of forming a semiconductor device, characterized in that formed in a depth of 100 ~ 400Å. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, Forming the interlayer insulating film And planarizing etching the interlayer insulating layer to expose the gate. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, Forming the interlayer insulating film Forming a hard mask layer on the entire surface of the semiconductor device forming method characterized in that it further comprises. Claim 9 was abandoned upon payment of a set-up fee. Forming the contact hole Etching the hard mask layer by using the photoresist pattern formed on the hard mask layer as an etching mask to form a hard mask layer pattern; And And etching the interlayer dielectric layer using the hard mask layer pattern as an etch mask. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, Forming the contact hole A first etching step of etching the interlayer insulating layer to a predetermined thickness; And And a second etching step of removing the interlayer insulating film remaining on the semiconductor substrate. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10, The first etching step is And etching the interlayer insulating film so that the thickness of the interlayer insulating film is 200 kPa to 300 kPa.

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