KR20010061262A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR20010061262A KR20010061262A KR1019990063753A KR19990063753A KR20010061262A KR 20010061262 A KR20010061262 A KR 20010061262A KR 1019990063753 A KR1019990063753 A KR 1019990063753A KR 19990063753 A KR19990063753 A KR 19990063753A KR 20010061262 A KR20010061262 A KR 20010061262A
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- oxide layer
- mask
- conductive layer
- gate electrode
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title claims description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- 229920005591 polysilicon Polymers 0.000 abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 8
- 229910021342 tungsten silicide Inorganic materials 0.000 description 8
- 238000002955 isolation Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 게이트전극이 집적화됨에 따른 셀영역의 오픈불량을 개선시킨 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which an open defect of a cell region is improved as a gate electrode is integrated.
일반적으로 반도체 소자가 고집적화될수록 게이트패턴은 저항을 감소시키기 위해 높게 형성하는데, 게이트패턴이 높고 밀집되게 형성되므로써 게이트패턴 사이의 공간이 좁은 지역에서는 측벽산화막이 비정상적으로 증착되어 측벽식각시 활성영역이 오픈되지 않는다.In general, as semiconductor devices become more integrated, gate patterns are formed higher in order to reduce resistance. As the gate patterns are formed higher and densely, the sidewall oxide film is abnormally deposited in a narrow area between the gate patterns, so that active regions are opened during sidewall etching. It doesn't work.
이 후 플러그형성시 플러그패턴과 활성영역 사이에 산화막 잔존물이 존재하여 셀오픈불량(Cell not open)이 발생한다.Thereafter, when the plug is formed, an oxide residue is present between the plug pattern and the active region, thereby causing cell not open.
도 1a에 도시된 바와 같이, 소자격리막(12)이 형성된 반도체 기판(11) 상에 게이트산화막(13)을 형성하고, 상기 게이트산화막(13) 상에 도핑폴리실리콘(Doped polysilicon), 텅스텐실리사이드(WSi), 마스크산화막(Mask oxide)을 순차적으로 증착한다.As shown in FIG. 1A, a gate oxide layer 13 is formed on a semiconductor substrate 11 on which the device isolation layer 12 is formed, and doped polysilicon and tungsten silicide are formed on the gate oxide layer 13. WSi) and a mask oxide film are deposited sequentially.
이어 상기 마스크산화막상에 감광막을 도포하고 노광 및 현상으로 패터닝한 다음, 패터닝된 감광막을 식각장벽으로 하여 마스크산화막을 건식식각한다. 이어 상기 감광막패턴을 제거한 다음, 마스크산화막을 식각장벽으로 하여 텅스텐실리사이드와 도핑폴리실리콘을 건식식각하여 마스크산화막패턴(16), 텅스텐실리사이드패턴(15), 도핑폴리실리콘패턴(14)을 포함하는 게이트패턴을 형성한다.Subsequently, a photoresist film is coated on the mask oxide film, patterned by exposure and development, and then the mask oxide film is dry-etched using the patterned photoresist as an etch barrier. Subsequently, after removing the photoresist pattern, a gate including a mask oxide layer pattern 16, a tungsten silicide pattern 15, and a doped polysilicon pattern 14 by dry etching the tungsten silicide and the doped polysilicon using the mask oxide layer as an etch barrier. Form a pattern.
이어 상기 결과물 상부에 측벽용산화막(17)을 증착한다. 이 때 게이트패턴이 높고 패턴사이 공간이 작아 측벽용산화막(17) 증착 후의 홈부분은 반도체기판(11)의 활성영역 상부에서는 공간이 넓으나 게이트패턴 상단부는 공간이 좁다.Subsequently, an oxide film 17 for sidewalls is deposited on the resultant. At this time, the gate pattern is high and the space between the patterns is small so that the groove portion after the sidewall oxide film 17 is deposited has a large space above the active region of the semiconductor substrate 11, but has a small space at the upper end of the gate pattern.
도 1b에 도시된 바와 같이, 상기 측벽용산화막(12)을 전면식각하여 게이트패턴 측벽에 접하는 측벽스페이서(18)를 형성한 다음, 상기 결과물 전면에 플러그물질을 형성한다. 이어 상기 플러그물질을 패터닝하여 상기 게이트패턴 사이를 매립하는 플러그패턴(19)을 형성한다.As shown in FIG. 1B, the sidewall oxide layer 12 is entirely etched to form a sidewall spacer 18 contacting the gate pattern sidewall, and then a plug material is formed on the entire surface of the resultant. Subsequently, the plug material is patterned to form a plug pattern 19 filling the gap between the gate patterns.
이 때 상기 측벽용산화막(17)이 비정상적으로 증착된 상태에서 전면식각이 이루어지므로 게이트패턴 사이의 활성영역 상부의 측벽용산화막(17)이 제거되지 않고 남아있게 된다(20).In this case, since the entire surface is etched in a state in which the sidewall oxide film 17 is abnormally deposited, the sidewall oxide film 17 on the upper portion of the active region between the gate patterns is left without being removed (20).
따라서 이러한 잔존하는 산화막으로 인해 플러그패턴(19) 하측의 활성영역이 오픈되지 않는 문제점이 발생한다.Therefore, a problem arises in that the active region under the plug pattern 19 is not opened due to the remaining oxide film.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로서, 고집적 게이트패턴 사이의 셀오픈불량을 방지하는데 적합한 반도체 소자의 제조 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a semiconductor device suitable for preventing cell open defects between highly integrated gate patterns.
도 1a 내지 도 1b는 종래기술에 따른 반도체 소자의 제조 방법을 나타낸 도면,1A to 1B illustrate a method of manufacturing a semiconductor device according to the prior art;
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 도면.2A to 2D illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21 : 반도체 기판 22 : 소자격리막21 semiconductor substrate 22 device isolation film
23 : 게이트산화막 24a : 도핑폴리실리콘패턴23 gate oxide film 24a doped polysilicon pattern
25a : 텅스텐실리사이드패턴 26a : 마스크산화막패턴25a: tungsten silicide pattern 26a: mask oxide film pattern
29 : 측벽스페이서 30 : 플러그패턴29 side wall spacer 30 plug pattern
상기의 목적을 달성하기 위한 본 발명은 소정공정이 실시된 반도체 기판 상부에 제1도전층, 마스크절연막을 순차적으로 형성하는 단계, 마스크를 이용하여 상기 마스크절연막을 선택적으로 식각하여 마스크절연막패턴을 형성하는 단계, 상기 마스크절연막패턴을 식각배리어로 하여 상기 제1도전층을 식각하여 제1도전층패턴을 형성하는 단계, 상기 마스크절연막을 일정 폭 습식식각하는 단계, 상기 결과물 전면에 측벽용절연막을 형성하는 단계, 상기 측벽용절연막을 전면식각하여 상기 제1도전층패턴 및 상기 마스크절연막패턴의 측벽에 접하는 스페이서를 형성하는 단계, 상기 결과물 전면에 제2도전층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The present invention for achieving the above object is a step of sequentially forming a first conductive layer, a mask insulating film on a semiconductor substrate subjected to a predetermined process, by selectively etching the mask insulating film using a mask to form a mask insulating film pattern Forming a first conductive layer pattern by etching the first conductive layer by using the mask insulating layer pattern as an etching barrier, wet etching the mask insulating layer by a predetermined width, and forming an insulating layer for sidewalls over the entire surface of the resultant layer. And forming a spacer contacting sidewalls of the first conductive layer pattern and the mask insulating layer pattern by etching the entire surface of the sidewall insulating layer, and forming a second conductive layer on the entire surface of the resultant layer. It is done.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 나타낸 도면이다.2A to 2D are views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 2a에 도시된 바와 같이, 소자격리막(22)이 형성된 반도체 기판(21) 상부에 게이트산화막(23)을 형성한 후, 상기 게이트산화막(22) 상에 도핑폴리실리콘 (24), 텅스텐실리사이드(25), 마스크산화막(26)을 순차적으로 형성한 다음, 상기 마스크산화막(26) 상부에 감광막을 도포하고 노광 및 현상으로 패터닝하여 게이트감광막패턴(27)을 형성한다. 여기서 상기 텅스텐실리사이드(25) 상에 캡핑폴리실리콘(Capping polysilicon)을 증착한 후 마스크산화막을 형성할 수 있고, 도핑폴리실리콘 상에 마스크산화막을 바로 형성할 수 도 있다.As shown in FIG. 2A, after the gate oxide layer 23 is formed on the semiconductor substrate 21 on which the device isolation layer 22 is formed, the doped polysilicon 24 and tungsten silicide are formed on the gate oxide layer 22. 25), the mask oxide film 26 is sequentially formed, and then the photoresist film is applied on the mask oxide film 26 and patterned by exposure and development to form the gate photoresist pattern 27. Here, a mask oxide film may be formed after depositing capping polysilicon on the tungsten silicide 25, and a mask oxide film may be directly formed on the doped polysilicon.
도 2b에 도시된 바와 같이, 상기 게이트감광막패턴(27)을 식각장벽으로 하여 마스크산화막(26)을 건식식각하여 마스크산화막패턴(26a)을 형성한 다음, 상기 게이트감광막패턴(27)을 제거한다.As shown in FIG. 2B, the mask oxide layer 26 is dry-etched using the gate photoresist pattern 27 as an etch barrier to form a mask oxide layer pattern 26a, and then the gate photoresist pattern 27 is removed. .
이어 상기 마스크산화막패턴(26a)을 식각장벽으로 텅스텐실리사이드(25), 도핑폴리실리콘(24), 게이트산화막(23)을 순차적으로 건식식각하여 텅스텐실리사이드패턴(25a), 도핑폴리실리콘패턴(24a)을 포함하는 게이트전극패턴을 형성한다.Subsequently, the tungsten silicide pattern 25a and the doped polysilicon pattern 24a are sequentially dry-etched by using the mask oxide layer pattern 26a as an etch barrier. To form a gate electrode pattern comprising a.
도 2c에 도시된 바와 같이, 습식식각을 실시하여 상기 마스크산화막패턴 (26a)의 양측 일정폭을 제거한다. 이어 상기 결과물 전면에 측벽용산화막(28)을 증착한다.As shown in FIG. 2C, a predetermined width of both sides of the mask oxide layer pattern 26a is removed by wet etching. Subsequently, an oxide film 28 for sidewalls is deposited on the entire surface.
도 2d에 도시된 바와 같이, 상기 측벽용산화막(28)을 전면식각하여 상기 마스크산화막패턴(26c), 텅스텐실리사이드패턴(25a) 및 도핑폴리실리콘패턴(24a)을 포함하는 게이트전극패턴의 측벽에 측벽스페이서(29)를 형성한 다음, 플러그용 폴리실리콘을 증착한다.As shown in FIG. 2D, the sidewall oxide layer 28 is etched to the sidewalls of the gate electrode pattern including the mask oxide layer pattern 26c, the tungsten silicide pattern 25a, and the doped polysilicon pattern 24a. After forming the sidewall spacers 29, polysilicon for plug is deposited.
이어 상기 폴리실리콘 상부에 감광막을 도포하고 노광 및 현상 공정으로 패터닝한 다음, 패터닝된 감광막(도시 생략)을 마스크로 하여 상기 폴리실리콘을 선택적으로 제거하여 상기 게이트전극패턴 사이를 매립하는 플러그패턴(30)을 형성한다.Subsequently, a plug pattern 30 is coated on the polysilicon and patterned by an exposure and development process, and then the polysilicon is selectively removed using a patterned photoresist (not shown) as a mask to fill the gaps between the gate electrode patterns. ).
이와 같이 본 발명에서는 마스크산화막의 일정폭을 측벽스페이서 형성전에 제거하므로써 게이트전극패턴이 밀집되어 있는 지역의 패턴사이 상단부 공간이 넓어지게 되고 측벽산화막 증착이 용이하게 실시되어 스페이서 형성시 활성영역 상부에 존재하는 측벽용산화막이 완전히 제거된다.Thus, in the present invention, by removing a certain width of the mask oxide film before forming the sidewall spacers, the upper space between the patterns of the regions where the gate electrode patterns are densified becomes wider and the sidewall oxide film is easily deposited to be present on the active region when forming the spacer The side wall oxide film is completely removed.
도면에 도시되지 않았지만, 상술한 공정을 플러그없이 비트라인 또는 캐패시터 형성 공정에 적용할 수 있다.Although not shown in the drawings, the above-described process may be applied to a bit line or a capacitor forming process without a plug.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 게이트패턴의 측벽에 형성되는 측벽용산화막의 잔막을 제거하므로써 게이트패턴 사이의 상단부 공간을 넓힐 수 있어 셀영역의 오픈을 용이하게 할 수 있는 효과가 있다.The present invention described above can increase the space between the upper end portions of the gate patterns by removing the residual film of the sidewall oxide film formed on the sidewalls of the gate pattern, thereby facilitating opening of the cell region.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990063753A KR20010061262A (en) | 1999-12-28 | 1999-12-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990063753A KR20010061262A (en) | 1999-12-28 | 1999-12-28 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010061262A true KR20010061262A (en) | 2001-07-07 |
Family
ID=19631075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990063753A KR20010061262A (en) | 1999-12-28 | 1999-12-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010061262A (en) |
-
1999
- 1999-12-28 KR KR1019990063753A patent/KR20010061262A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100258578B1 (en) | A method of forming contacts of semiconductor memory device | |
| KR20000042460A (en) | Method for forming bit line contact of semiconductor device | |
| KR100252044B1 (en) | Method for forming contact hole in semiconductor device | |
| KR20010061262A (en) | Method for manufacturing semiconductor device | |
| KR100753031B1 (en) | Method of forming contact hole in semiconductor device | |
| KR20010058679A (en) | Method for fabricating a semiconductor memory device having self-aligned contact | |
| KR100277905B1 (en) | Manufacturing Method of Semiconductor Memory Device | |
| KR100274355B1 (en) | Method of forming a word line in a flash memory device | |
| KR100431708B1 (en) | Method of manufacturing semiconductor device with double spacer for preventing damage of contact hole | |
| KR100529379B1 (en) | Method for manufacturing capacitor in secmiconductor device | |
| KR100218735B1 (en) | Forming method for contact hole of semiconductor device | |
| KR100546122B1 (en) | Capacitor Formation Method of Semiconductor Device | |
| KR100721186B1 (en) | Method for manufacturing semiconductor device | |
| KR100217920B1 (en) | Fabricating method for bit line in semiconductor device | |
| KR19990043724A (en) | Manufacturing method of semiconductor device | |
| KR100258368B1 (en) | Manufacturing method of contact of semiconductor device | |
| KR20000050330A (en) | Method for forming contact of semiconductor device | |
| KR100365748B1 (en) | A method for forming contact of semiconductor device | |
| KR100321759B1 (en) | Method for fabricating semiconductor device | |
| KR100379511B1 (en) | Method for Forming contact of Semiconductor Device | |
| KR20010063078A (en) | Method for manufacturing of capacitor | |
| KR20000003618A (en) | Fine contact hole forming method of semiconductor device | |
| KR20040003524A (en) | Damascene bit line compatible to SAC and method for forming the same | |
| KR20010068951A (en) | Method of forming memory contact hole | |
| KR19980045145A (en) | Contact hole formation method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |