KR20000003618A - Fine contact hole forming method of semiconductor device - Google Patents
Fine contact hole forming method of semiconductor device Download PDFInfo
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- KR20000003618A KR20000003618A KR1019980024878A KR19980024878A KR20000003618A KR 20000003618 A KR20000003618 A KR 20000003618A KR 1019980024878 A KR1019980024878 A KR 1019980024878A KR 19980024878 A KR19980024878 A KR 19980024878A KR 20000003618 A KR20000003618 A KR 20000003618A
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- forming
- gate electrode
- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 abstract description 3
- 238000001704 evaporation Methods 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 230000007423 decrease Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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Abstract
Description
본 발명은 반도체 소자의 미세 콘택홀 형성방법에 관한 것으로, 특히 반도체 소자의 콘택홀 형성시 사용되는 마스크 산화막을 산화막과 다결정실리콘으로 이루어지는 이중구조로 형성하여 셀프 얼라인 콘택(Self Aligned Contact : 이하 SAC 라 함) 식각시 공정 여유도를 확보하여 전극 상부의 손상을 줄일 수 있고, 공정 여유도 확보에 따른 반도체 소자 제조공정 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 미세 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine contact hole in a semiconductor device. In particular, a mask oxide film used for forming a contact hole in a semiconductor device is formed in a dual structure consisting of an oxide film and polycrystalline silicon, thereby forming a self-aligned contact. The present invention relates to a method for forming a fine contact hole of a semiconductor device capable of securing a process margin during etching to reduce damage to an upper part of the electrode, and improving a semiconductor device manufacturing process yield and reliability by securing a process margin.
일반적으로 1G DRAM 급 이상 고집적 반도체 소자의 콘택홀을 형성할 시, 질화막에 대한 고 선택비를 이용한 셀프 얼라인 콘택(Self Aligned Contact : 이하 SAC 라 함) 공정이 주로 사용된다.In general, when forming contact holes of 1G DRAM or higher integrated semiconductor devices, a self-aligned contact (SAC) process using a high selectivity to a nitride film is mainly used.
반도체 소자가 점점 고 집적화됨에 따라 콘택 크기는 점차 줄어들고 마스크 오정렬(mis-align)과 같은 공정 여유도는 콘택 크기 감소만큼 줄어들지 않기 때문에 실제 콘택이 오픈되는 크기는 계속 줄어들고 있다.As semiconductor devices become increasingly integrated, the size of open contacts continues to shrink as contact sizes decrease gradually and process margins such as mask mis-alignment do not decrease as contact size decreases.
또한 현재 사용되고 있는 상기 SAC 공정은 산화막 식각 시 질화막을 식각 멈춤막으로 사용하는 공정이 주류를 이루고 있으며, 소자가 고집적화됨에 따라 실제 콘택이 오픈되는 지역을 확보하기 위해 식각 멈춤막으로 사용하는 질화막의 두께는 점차 줄어들어야 한다.In addition, the SAC process currently being used is the process of using the nitride film as an etch stop film during the etching of the oxide, the thickness of the nitride film used as an etch stop film to secure the area where the actual contact is open as the device is highly integrated Should gradually decrease.
따라서 질화막 베리어 색(Barrier SAC) 공정에서 요구되는 산화막과 질화막과의 선택비는 증가되어야 하나 종래의 공정 능력상 선택비는 한계가 있으며, 또한 콘택이 오픈되는 크기는 계속 줄어들고 있기 때문에 공정 능력 및 재현성 확보가 더욱 어려워지는 문제점이 있다.Therefore, the selection ratio between oxide film and nitride film required in nitride barrier color (Barrier SAC) process should be increased, but the selection ratio is limited due to the conventional process capability. There is a problem that is more difficult to secure.
따라서 본 발명은 반도체 소자의 콘택홀 형성 시 전극위에 증착되어 전극과 같이 패턴이 형성되는 마스크 산화막의 구조를 산화막과 다결정 실리콘의 이중 구조로 형성함으로서 배리어 질화막이 손상되더라도 산화막의 선택비가 충분히 확보되어 있는 마스크 다결정 실리콘을 이용하여 식각 멈춤막으로 사용함으로서 전극의 손상 및 전극간 쇼트를 방지하여 공정 여유도를 증가시켜 미세 콘택홀을 용이하게 형성할 수 있는 반도체 소자의 미세 콘택홀 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention forms a structure of a mask oxide film, which is deposited on an electrode and forms a pattern like an electrode, when the contact hole of a semiconductor device is formed. By using a mask polycrystalline silicon as an etch stop film, it provides a method for forming a fine contact hole of a semiconductor device that can easily form a fine contact hole by increasing the process margin by preventing electrode damage and short circuit between electrodes. There is a purpose.
도 1 내지 도 8 은 본 발명의 방법에 따른 반도체 소자의 미세 콘택홀 형성 공정단계를 도시한 단면도1 to 8 are cross-sectional views showing the process steps for forming a fine contact hole in a semiconductor device according to the method of the present invention
도 5a 는 상기 도 5 의 평면도FIG. 5A is a plan view of FIG. 5.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
1 : 실리콘 기판 2 : 산화막1: silicon substrate 2: oxide film
3 : 게이트 전극용 다결정실리콘 4 : 게이트 전극용 텅스텐 실리사이드3: polysilicon for gate electrode 4: tungsten silicide for gate electrode
5 : 하드마스크용 산화막 6 : 하드마스크용 다결정실리콘5: oxide film for hard mask 6: polycrystalline silicon for hard mask
7 : 식각 멈춤용 질화막 8 : 절연 산화막7: nitride film for etching stop 8: insulating oxide film
9 : 콘택 마스크용 감광막 10 : 콘택홀9 photosensitive film for contact mask 10 contact hole
11 : 콘택 플러그용 다걸정실리콘 12 : 질화막 스페이서11 multi-silicon silicon for contact plug 12 nitride film spacer
13 : 콘택 플러그13: contact plug
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 미세 콘택홀 형성방법은,Method for forming a fine contact hole of the semiconductor device of the present invention for achieving the above object,
반도체 기판상에 게이트 전극 형성용 도전물질을 증착하는 단계와,Depositing a conductive material for forming a gate electrode on the semiconductor substrate;
상기 게이트 전극용 도전물질의 상부에 하드마스크용 산화막 및 다결정 실리콘을 차례로 증착한 후, 패터닝하여 게이트 전극을 형성하는 단계와,Depositing a hard mask oxide film and polycrystalline silicon in order on the conductive material for the gate electrode, and then patterning the gate electrode to form a gate electrode;
전체구조 상부에 산화막 및 식각 멈춤용 질화막을 차례로 증착하는 단계와,Sequentially depositing an oxide film and an etch stop nitride film on the entire structure;
상기 식각 멈춤용 질화막을 식각하여 게이트 전극과 상기 게이트 전극 상부의 하드 마스크용 산화막 및 다결정실리콘으로 이루어진 패턴의 양측벽에 질화막 스페이서를 형성하는 단계와,Etching the etch stop nitride film to form nitride spacers on both sidewalls of a pattern comprising a gate electrode, a hard mask oxide film and polycrystalline silicon on the gate electrode;
전체구조 상부에 소정두께의 절연 산화막을 증착하는 단계와,Depositing an insulating oxide film having a predetermined thickness on the entire structure;
상기 절연 산화막을 전면 식각하여 상기 하드마스크용 다결정실리콘의 상부가 오픈되도록 하는 단계와,Etching the entire surface of the insulating oxide layer to open an upper portion of the polysilicon for the hard mask;
상기 구조 상부에 콘택 마스크용 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern for a contact mask on the structure;
상기 콘택 마스크용 감광막 패턴을 이용하여 하부의 노출된 절연 산화막을 식각하여 콘택홀을 형성하되, 상기 게이트 전극 상부의 식각 멈춤용 다결정 실리콘과 게이트 전극 측벽 질화막을 식각 멈춤막으로 하여 콘택홀을 형성하는 단계와,Forming a contact hole by etching a lower exposed insulating oxide layer using the contact mask photoresist pattern, and forming a contact hole by using an etch stop polycrystalline silicon on the gate electrode and a gate electrode sidewall nitride layer as an etch stop layer Steps,
상기 콘택홀 내에 콘택 플러그를 형성하는 단계를 포함하는 구성으로 된다.And forming a contact plug in the contact hole.
이하 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대해 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 8 은 본 발명의 방법에 따른 반도체 소자의 미세 콘택홀 형성공정단계를 도시한 단면도이다.1 to 8 are cross-sectional views illustrating a process of forming a fine contact hole in a semiconductor device according to the method of the present invention.
도 1을 참조하면, 반도체 기판(1)상에 게이트 전극(3,4)를 형성한다.Referring to FIG. 1, gate electrodes 3 and 4 are formed on a semiconductor substrate 1.
이때 상기 게이트 전극(3,4)을 형성하는 물질은 그 하부로부터 상부로 각각 다결정실리콘(3)과 텅스텐 실리사이드(4)이다.In this case, the materials forming the gate electrodes 3 and 4 are polycrystalline silicon 3 and tungsten silicide 4 from bottom to top, respectively.
그리고 상기 게이트 전극(3,4) 상부에 하드마스크(Hardmask)의 용도로 산화막(5)과 다결정 실리콘(6)을 사용한 후, 기존의 공정과 같이 적정 두께의 산화막(2)과 식각 멈춤용 질화막(7)을 차례로 증착한다.After the oxide film 5 and the polycrystalline silicon 6 are used as a hard mask on the gate electrodes 3 and 4, the oxide film 2 and the nitride film for etching stoppage, as in the conventional process, are used. (7) is sequentially deposited.
도 2를 참조하면, 상기 식각 멈춤용 질화막(7)을 식각하여 게이트 전극(3,4)과 상기 게이트 전극(3,4) 상부의 산화막(5) 및 다결정실리콘(6)으로 이루어진 패턴의 양측벽에 질화막 스페이서(12)를 형성한다.Referring to FIG. 2, both sides of the pattern including the gate electrodes 3 and 4, the oxide film 5 and the polysilicon 6 on the gate electrodes 3 and 4 are etched by etching the etch stop nitride film 7. The nitride film spacer 12 is formed in the wall.
다음 전체구조 상부에 소정두께의 절연 산화막(8)을 증착한다.Next, an insulating oxide film 8 having a predetermined thickness is deposited on the entire structure.
도 3 을 참조하면, 화학-기계적 연마(Chemical Mechanical Polishing : 이하 CMP 라 함) 혹은 식각 공정을 이용하여 상기 하드마스크용 다결정실리콘(6)의 상부가 오픈되도록 한다.Referring to FIG. 3, the upper part of the polysilicon 6 for hard mask is opened by using a chemical mechanical polishing (CMP) or an etching process.
도 4를 참조하면, 전체구조 상부에 감광막 도포한 후 리소그라피 공정으로 콘택 마스크용 감광막 패턴(9)을 형성한다.Referring to FIG. 4, after the photoresist film is applied on the entire structure, the photoresist pattern 9 for contact mask is formed by a lithography process.
도 5를 참조하면, 상기 콘택 마스크용 감광막 패턴(9)을 이용하여 하부의 노출된 절연 산화막(8)을 식각하여 콘택홀(10)을 형성한다.Referring to FIG. 5, a contact hole 10 is formed by etching a lower exposed insulating oxide layer 8 using the photoresist pattern 9 for contact mask.
이때, 상기 게이트 전극(3,4) 상부의 식각 멈춤용 다결정 실리콘(6)과 게이트 전극(3,4)의 측벽 질화막(12)을 식각 멈춤용 막으로 이용하여 콘택홀(10)을 형성한다.In this case, the contact hole 10 is formed by using the etch stop polycrystalline silicon 6 on the gate electrodes 3 and 4 and the sidewall nitride film 12 of the gate electrodes 3 and 4 as the etch stop film. .
이 때 상기 다결정 실리콘(6)은 이후 공정인 콘택 플러그 실리콘 형성시(도 6, 도 7 의 공정) 제거되어 전극간 쇼트가 나는 것을 방지할 수 있다.At this time, the polycrystalline silicon 6 may be removed at the time of forming the contact plug silicon (the process of FIGS. 6 and 7), thereby preventing short circuit between electrodes.
한편, 도 5a 는 상기 도 5 의 평면도로서 콘택홀(10) 형성후의 평면상태를 도시하고 있다.FIG. 5A is a plan view of FIG. 5 showing a planar state after the contact hole 10 is formed.
상기 도면에 도시된 바와 같이, 상부 형상을 살펴보면 보면 실제 오픈된 콘택홀(10), 측벽 질화막(12), 하드마스크용 다결정 실리콘(6), 절연 산화막(8)의 배치 상태를 알수 있다.As shown in the figure, looking at the upper shape, it can be seen that the arrangement state of the contact hole 10, the sidewall nitride film 12, the polycrystalline silicon 6 for the hard mask, and the insulating oxide film 8 are actually opened.
도 6 을 참조하면, 전체구조 상부에 다결정 실리콘(13)을 소정두께로 증착한다.Referring to FIG. 6, polycrystalline silicon 13 is deposited on the entire structure to a predetermined thickness.
도 7 을 참조하면, CMP 혹은 식각 공정을 이용하여 상기 증착된 다결정 실리콘(13)을 적정두께로 식각하면 상기 도면에 나타난 바와 같이 콘택홀(10)내 비트라인 및 캐패시터 전극으로 사용할 다결정 실리콘 플러그(13)가 형성된다.Referring to FIG. 7, when the deposited polycrystalline silicon 13 is etched to an appropriate thickness using a CMP or an etching process, a polycrystalline silicon plug to be used as a bit line and a capacitor electrode in the contact hole 10 as shown in FIG. 13) is formed.
도 8을 참조하면, 전체구조 상부에 절연 산화막(8)을 증착하여 이후 공정을 진행한다.Referring to FIG. 8, an insulating oxide film 8 is deposited on the entire structure, and then the process is performed.
이상 상술한 바와 같이, 본 발명의 방법에 따라 반도체 소자의 콘택홀 형성 시 게이트 전극위에 증착되어 게이트 전극과 같이 패턴이 형성되는 마스크 산화막의 구조를 산화막과 다결정 실리콘의 이중 구조로 형성함으로써, 셀프 얼라인 콘택 식각시 공정 여유도를 확보하여 전극의 상부의 손상을 줄일 수 있고, 또한 공정 여유도 확보에 따라 공정상의 재현성을 있는 결과를 어더 미세 콘택홀 형성을 용이하게 할 수 있다As described above, according to the method of the present invention, the mask oxide film is deposited on the gate electrode when the contact hole of the semiconductor device is formed to form a pattern like the gate electrode, thereby forming a double structure of the oxide film and the polycrystalline silicon. The process margin can be reduced when the in-contact etching is performed to reduce the damage of the upper part of the electrode, and the process reproducibility can be easily achieved according to the process margin.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20160104450A (en) | 2015-02-26 | 2016-09-05 | 이만택 | Acupressure apparatus |
| KR20160104436A (en) | 2015-02-26 | 2016-09-05 | 주식회사 신진기계 | Inserting apparatus for Drying screen of Laver manufacturing machine |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160104450A (en) | 2015-02-26 | 2016-09-05 | 이만택 | Acupressure apparatus |
| KR20160104436A (en) | 2015-02-26 | 2016-09-05 | 주식회사 신진기계 | Inserting apparatus for Drying screen of Laver manufacturing machine |
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