KR20040057605A - method for manufacturing storage node contact in semiconductor device - Google Patents
method for manufacturing storage node contact in semiconductor device Download PDFInfo
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- KR20040057605A KR20040057605A KR1020020084371A KR20020084371A KR20040057605A KR 20040057605 A KR20040057605 A KR 20040057605A KR 1020020084371 A KR1020020084371 A KR 1020020084371A KR 20020084371 A KR20020084371 A KR 20020084371A KR 20040057605 A KR20040057605 A KR 20040057605A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 구체적으로는 고집적 반도체 소자의 스토리지노드 콘택 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a storage node contact of a highly integrated semiconductor device.
반도체 소자가 고집적화됨에 따라, 스토리지노드 콘택 크기는 점점 작아지고 있는 추세이다. 또한, 안정적인 반도체 소자의 동작특성을 확보하기 위해서는 셀 트랜지스터의 커런트 드라이브(current drive) 능력을 최대한 높여야 하며, 이를위해서는 스토리지노드 콘택 자체의 저항을 최대한 줄여야 한다. 상기 스토리지노드 콘택의 저항을 줄이는 방안으로는, 스토리지노드 플러그 간의 접촉면적을 증가시키는 방법이 있지만, 이러한 방법은 반도체 소자가 고집적화될수록 스토리지노드 콘택 자체의 크기는 점점 작아지고, 이에 따라 스토리지노드 플러그 간의 접촉 면적은 감소되므로 적당치 않다.As semiconductor devices are highly integrated, storage node contact sizes are becoming smaller. In addition, in order to secure stable operation characteristics of the semiconductor device, the current drive capability of the cell transistor should be increased as much as possible, and for this purpose, the resistance of the storage node contact itself should be reduced as much as possible. As a method of reducing the resistance of the storage node contact, there is a method of increasing the contact area between the storage node plugs. However, in this method, as the semiconductor device becomes more integrated, the size of the storage node contact itself becomes smaller, and thus, between the storage node plugs. The contact area is reduced and therefore not suitable.
또한, 스토리지노드 콘택 형성 시, 셀프어라인 방식을 이용하기 때문에 조금만 미스어라인되어도 하부의 도전 플러그와의 접촉 면적은 줄어들 수 밖에 없는 실정이다.In addition, since the self-aligning method is used when forming the storage node contact, even if a little misalignment, the contact area with the conductive plug below is inevitably reduced.
도 1a 내지 도 1 은 종래 기술에 따른 스토리지노드 콘택 형성 방법을 설명하기 위한 공정단면도이다.1A through 1 are cross-sectional views illustrating a method of forming a storage node contact according to the related art.
종래 기술에 따른 스토리지노드 콘택 형성 방법은, 도 1a에 도시된 바와 같이, 반도체기판(1) 상에 제 1절연막(2)을 형성한 다음, 상기 제 1절연막(2)을 식각하여 콘택(3)을 형성한다. 이때, 상기 기판(1)에는, 도면에는 도시되지 않았지만, 게이트 전극 및 소오스/드레인의 불순물영역을 포함한 트랜지스터가 제조되어 있다.In the storage node contact forming method according to the related art, as shown in FIG. 1A, a first insulating layer 2 is formed on a semiconductor substrate 1, and then the first insulating layer 2 is etched to form a contact 3. ). At this time, although not shown in the drawing, a transistor including a gate electrode and a source / drain impurity region is fabricated in the substrate 1.
이어, 상기 콘택(3)을 포함한 기판 전면에 다결정 실리콘막을 형성한 다음, 상기 다결정 실리콘막을 에치백하여 콘택(3)을 매립시키는 도전 플러그(4)를 형성한다. 그런 다음, 상기 제 1절연막(2)을 포함한 기판 상에 제 2절연막(5), 비트라인(6) 및 측벽 스페이서 형성용 실리콘 질화막(7)을 차례로 형성한다. 이 후, 상기 실리콘 질화막(7) 상에 제 3절연막(8)을 형성하고 평탄화시킨 다음, 감광막패턴(20)을 이용하여 상기 제 3절연막, 실리콘 질화막, 비트라인 및 제 2절연막을 셀프 어라인( self align) 방식으로 건식 식각하여 도전 플러그(4)를 노출시키는 스토리지노드 콘택(SC1)을 형성한다.Subsequently, a polycrystalline silicon film is formed on the entire surface of the substrate including the contact 3, and then the conductive plug 4 for filling the contact 3 is formed by etching back the polycrystalline silicon film. Next, a second insulating film 5, a bit line 6, and a silicon nitride film 7 for forming sidewall spacers are sequentially formed on the substrate including the first insulating film 2. Thereafter, a third insulating film 8 is formed and planarized on the silicon nitride film 7, and then the third insulating film, the silicon nitride film, the bit line, and the second insulating film are self-aligned using the photosensitive film pattern 20. Dry etching is performed in a self align manner to form a storage node contact SC1 exposing the conductive plug 4.
이어, 도 1b에 도시된 바와 같이, 감광막 패턴을 제거한다.Subsequently, as shown in FIG. 1B, the photoresist pattern is removed.
그런 다음, 도 1c에 도시된 바와 같이, 상기 제 3절연막 및 제 2절연막의 일부를 습식 식각한다. 이때, 상기 습식 식각 공정에서 제 2절연막의 일부가 식각됨으로서, 스토리지노드 콘택(SC1) 크기가 증가된다.Then, as shown in FIG. 1C, portions of the third and second insulating layers are wet etched. In this case, a portion of the second insulating layer is etched in the wet etching process, thereby increasing the size of the storage node contact SC1.
도 2a 내지 도 2b는 종래 기술에 따른 문제점을 설명하기 위한 공정단면도이다.2A to 2B are process cross-sectional views for explaining the problem according to the prior art.
종래의 기술에서는 감광막 패턴이 비트라인에 대해 정확히 어라인되지 않아 미스어라인된 경우, 도 2a에 도시된 바와 같이, 스토리지노드 콘택이 도전 플러그와 접촉되는 접촉 면적이 작아지게 된다.In the related art, when the photoresist pattern is misaligned due to misalignment with respect to the bit line, as shown in FIG. 2A, the contact area where the storage node contact is in contact with the conductive plug is reduced.
따라서, 도 2b에 도시된 바와 같이, 상기 스토리지노드 콘택의 바닥면 면적을 확보하기 위해 제 3절연막 및 제 2절연막을 과도하게 습식 식각 공정을 진행하게 된다. 그러나, 상기 과도 습식 식각 공정을 통해 스토리지노드 콘택의 바닥면 면적은 어느 정도 확보되는 반면에, 상기 스토리지노드 콘택의 상부도 함께 식각됨으로서, 이웃한 스토리지노드 콘택 간의 분리막인 제 3절연막의 간격이 매우 작아져 스토리지노드 콘택 간의 전기적 쇼트(short)를 유발시키는 문제점이 있었다.Therefore, as shown in FIG. 2B, the third insulating layer and the second insulating layer are excessively wet-etched to secure the bottom area of the storage node contact. However, while the bottom surface area of the storage node contact is secured to some extent through the transient wet etching process, the upper portion of the storage node contact is also etched, so that a gap between the third insulating layer, which is a separator between neighboring storage node contacts, is very large. There has been a problem in that the electrical short between the storage node contacts is reduced.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 스토리지노드 콘택의 바닥면 면적을 확보하면서 동시에 이웃한 스토리지노드 콘택 간의 분리막인 제 3절연막이 과도 식각되는 것을 방지할 수 있는 반도체 소자의 스토리지노드 콘택 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems. The present invention provides a semiconductor device capable of securing the bottom surface area of a storage node contact and at the same time preventing over-etching of the third insulating layer, which is a separator between neighboring storage node contacts. It is an object of the present invention to provide a method for forming a storage node contact.
도 1a 내지 도 1b는 종래 기술에 따른 스토리지노드 콘택 형성 방법을 설명하기 위한 공정단면도.1A to 1B are cross-sectional views illustrating a method of forming a storage node contact according to the related art.
도 2a 내지 도 2b는 종래 기술에 따른 문제점을 설명하기 위한 공정단면도.Figure 2a to 2b is a cross-sectional view for explaining the problem according to the prior art.
도 3a 내지 도 3c는 본 발명의 제 1실시예에 따른 반도체 소자의 스토리지노드 콘택 형성 방법을 설명하기 위한 공정단면도.3A to 3C are cross-sectional views illustrating a method of forming a storage node contact in a semiconductor device according to a first embodiment of the present invention.
도 4a 내지 도 4c는 본 발명의 제 2실시예에 따른 반도체 소자의 스토리지노드 콘택 형성 방법을 설명하기 위한 공정단면도.4A through 4C are cross-sectional views illustrating a method of forming a storage node contact in a semiconductor device according to a second exemplary embodiment of the present invention.
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 스토리지노드 콘택 형성 방법은 비트라인 및 상기 비트라인을 덮는 절연 스페이서를 각각 구비된 반도체기판을 제공하는 단계와, 기판 전면에 절연막 및 베리어막을 차례로 형성하는 단계와, 베리어막 위에 스토리지노드 콘택영역을 노출시키는 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 하고 베리어막 및 절연막을 선택 식각하여 기판의 일부를 노출시키는 스토리지노드 콘택을 형성하는 단계와, 감광막 패턴을 제거하는 단계와, 잔류된 베리어막을 마스크로 하고 상기 절연막을 습식 식각하여 스토리지노드 콘택의 바닥면 면적을 확보하는 단계를 포함한 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a storage node contact of a semiconductor device, the method including: providing a semiconductor substrate having bit lines and insulating spacers covering the bit lines, and sequentially forming an insulating film and a barrier film on the entire surface of the substrate; Forming a photoresist pattern exposing the storage node contact region on the barrier layer; forming a storage node contact exposing a portion of the substrate by selectively etching the barrier layer and the insulating layer using the photoresist pattern as a mask; And removing the photoresist pattern, and wet etching the insulating layer using the remaining barrier layer as a mask to secure a bottom surface area of the storage node contact.
상기 절연막은 BPSG, HDP, TEOS 및 USG막 중 어느 하나를 이용하며, 1000∼10000Å 두께로 형성한다.The insulating film is any one of a BPSG, HDP, TEOS, and USG film, and is formed to a thickness of 1000 to 10000 GPa.
상기 베리어막은 실리콘 질화막을 이용하며, 상기 실리콘 질화막은 PECVD 및 LPCVD 중 어느 하나의 공정에 의해 형성한다. 또한, 상기 실리콘 질화막은 100∼2000Å 두께로 형성한다.The barrier film uses a silicon nitride film, and the silicon nitride film is formed by one of PECVD and LPCVD. In addition, the silicon nitride film is formed to a thickness of 100 ~ 2000Å.
상기 습식 식각 공정은 BOE 및 HF 중 어느 하나를 이용한다.The wet etching process uses any one of BOE and HF.
본 발명에 따른 반도체 소자의 스토리지노드 콘택 형성 방법은 비트라인 및 비트라인을 덮는 절연 스페이서를 각각 구비된 반도체기판을 제공하는 단계와, 기판에 절연막을 형성하는 단계와, 절연막 위에 스토리지노드 콘택영역을 덮는 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 하고 상기 절연막을 식각하여 콘택을 형성하는 단계와, 감광막 패턴을 제거하는 단계와, 콘택을 매립시키는 베리어막을 형성하는 단계와, 베리어막을 마스크로 하고 상기 절연막을 습식 식각하여 기판의 일부분을 노출시키는 스토리지노드 콘택을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of forming a storage node contact in a semiconductor device according to the present invention includes providing a semiconductor substrate having a bit line and an insulating spacer covering the bit line, forming an insulating film on the substrate, and forming a storage node contact region on the insulating film. Forming a covering photoresist pattern, forming a contact by etching the insulating film using the photoresist pattern as a mask, removing the photoresist pattern, forming a barrier film to fill the contact, and using the barrier film as a mask And wet etching the insulating layer to form a storage node contact exposing a portion of the substrate.
상기 절연막은 BPSG, HDP, TEOS 및 USG막 중 어느 하나를 이용하며, 1000∼10000Å 두께로 형성한다.The insulating film is any one of a BPSG, HDP, TEOS, and USG film, and is formed to a thickness of 1000 to 10000 GPa.
상기 베리어막은 PECVD 및 LPCVD 중 어느 하나의 공정에 의해 형성된 실리콘 질화막을 이용하며, 1000∼5000Å 두께로 형성한다.The barrier film is formed using a silicon nitride film formed by one of PECVD and LPCVD, and is formed to a thickness of 1000 to 5000 mm 3.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3c는 본 발명의 제 1실시예에 따른 반도체 소자의 스토리지노드 콘택 형성 방법을 설명하기 위한 공정단면도이다.3A to 3C are cross-sectional views illustrating a method of forming a storage node contact in a semiconductor device according to a first embodiment of the present invention.
본 발명의 제 1실시예에 따른 반도체 소자의 스토리지노드 콘택 형성 방법은, 도 3a에 도시된 바와 같이, 먼저 반도체기판(100) 상에 제 1절연막(102)을 형성한 다음, 상기 제 1절연막(102)을 식각하여 불순물영역(미도시)을 노출시키는 콘택(103)을 형성한다. 이때, 상기 반도체기판(100)에는, 도면에는 도시되지 않았지만, 게이트 전극 및 소오스/드레인의 불순물영역이 구비된 트랜지스터가 제조되어 있다. 이어, 상기 콘택(103)을 포함한 기판 전면에 다결정 실리콘막(미도시)을 형성한 후, 상기 다결정 실리콘막을 에치백 또는 화학적 기계적 연마하여 콘택(103)을 매립시키는 도전플러그(104)를 형성한다.In the method of forming a storage node contact of a semiconductor device according to the first embodiment of the present invention, as shown in FIG. 3A, first, a first insulating layer 102 is formed on a semiconductor substrate 100, and then the first insulating layer is formed. The 102 is etched to form a contact 103 exposing an impurity region (not shown). In this case, although not shown in the figure, a transistor is provided in the semiconductor substrate 100 provided with impurity regions of a gate electrode and a source / drain. Subsequently, a polycrystalline silicon film (not shown) is formed on the entire surface of the substrate including the contact 103, and then the conductive plug 104 is formed by etching back or chemical mechanical polishing the polycrystalline silicon film to fill the contact 103. .
그런 다음, 상기 도전 플러그(104)를 포함한 기판 전면에 제 2절연막(105), 비트라인(106) 및 절연 스페이서(107)를 차례로 형성한다.Thereafter, the second insulating film 105, the bit line 106, and the insulating spacer 107 are sequentially formed on the entire surface of the substrate including the conductive plug 104.
이 후, 상기 구조 전면에 제 3절연막(108)을 증착하고 나서, 상기 절연 스페이서(107) 표면이 노출되는 시점까지 상기 제3절연막을 에치백 또는 화학적 기계적 연마하여 평탄화시킨다. 이때, 상기 제 3절연막(108)은 BPSG(BoroPhosphorSilicate Glass), HDP(High Density Plasma), TEOS(TetraEthylOrtho Silicate) 및 USG(Undoped Silicon Glass)막 중 어느 하나를 이용하며, 1000∼10000Å 두께로 형성한다.Thereafter, after the third insulating film 108 is deposited on the entire surface of the structure, the third insulating film is etched back or chemical mechanically polished and planarized until the surface of the insulating spacer 107 is exposed. In this case, the third insulating layer 108 may be formed of any one of BoroPhosphorSilicate Glass (BPSG), High Density Plasma (HDP), TetraEthylOrtho Silicate (TEOS), and Undoped Silicon Glass (USG). .
이어, 상기 제 3절연막(108) 위에 실리콘 질화막(109)을 형성한다. 이때, 상기 실리콘 질화막(109)은 PECVD(Plasma Enhanced Chemical Vapor Deposition) 또는 LPCVD(Low Pressure Chemical Vapor Deposition) 공정을 이용하며, 100∼2000Å 두께로 형성한다. 또한, 상기 실리콘 질화막(109)은 이 후의 제 2및 제 3절연막의 습식 식각 공정에서 식각 베리어막의 역할을 한다.Subsequently, a silicon nitride film 109 is formed on the third insulating film 108. In this case, the silicon nitride film 109 is formed using a plasma enhanced chemical vapor deposition (PECVD) or a low pressure chemical vapor deposition (LPCVD) process, and is formed to a thickness of 100 to 2000 kPa. In addition, the silicon nitride layer 109 serves as an etching barrier layer in a subsequent wet etching process of the second and third insulating layers.
그런 다음, 도 3b에 도시된 바와 같이, 상기 실리콘 질화막(109) 위에 스토리지노드 콘택영역(미도시)을 정의하는 감광막 패턴(120)을 형성한 다음, 상기 감광막 패턴(120)을 마스크로 하고 상기 기판이 노출되는 시점까지 상기 막들을 셀프 어라인 방식으로 건식 식각하여 스토리지노드 콘택(SC2)을 형성한다. 이때, 상기 건식 식각 공정에서, 감광막 패턴(120)이 비트라인(106)에 대해 정확히 어라인되지않아 미스어라인이 발생된 경우, 스토리지노드 콘택(SC2)이 도전 플러그(104)와 접촉되는 접촉 면적이 작아지게 된다.3B, a photoresist pattern 120 defining a storage node contact region (not shown) is formed on the silicon nitride layer 109, and then the photoresist pattern 120 is used as a mask. The films are dry-etched in a self-aligned manner until the substrate is exposed to form a storage node contact SC2. In this dry etching process, when the photoresist pattern 120 is not aligned with respect to the bit line 106 and a misalignment occurs, the storage node contact SC2 contacts with the conductive plug 104. The area becomes small.
따라서, 상기 스토리지노드 콘택(SC2)의 바닥면 면적을 확보하기 위해, 먼저, 상기 감광막 패턴을 제거하고 나서, 도 3c에 도시된 바와 같이, 잔류된 실리콘 질화막(109a)을 식각 베리어로 하고 상기 제 3 및 제 2절연막을 습식 식각한다. 이때, 상기 습식 식각 공정에서, 습식액으로 BOE(Buffer Oxide Etchant) 또는 HF용액을 이용한다. 또한, 상기 식각 베리어인 실리콘 질화막(109a)은 제 3절연막이 과도 습식 식각되더라도 이웃한 스토리지노드 콘택(SC2) 간의 전기적 쇼트를 방지하는 역할을 한다.Therefore, in order to secure the bottom area of the storage node contact SC2, first, the photoresist pattern is removed, and as shown in FIG. 3C, the remaining silicon nitride layer 109a is used as an etch barrier and the first photoresist layer is removed. The third and second insulating films are wet etched. At this time, in the wet etching process, BOE (Buffer Oxide Etchant) or HF solution is used as the wet solution. In addition, the silicon nitride layer 109a which is the etching barrier serves to prevent electrical short between the neighboring storage node contacts SC2 even when the third insulating layer is excessively wet etched.
도 4a 내지 도 4c는 본 발명의 제 2실시예에 따른 반도체 소자의 스토리지노드 콘택 형성 방법을 설명하기 위한 공정단면도이다.4A through 4C are cross-sectional views illustrating a method of forming a storage node contact in a semiconductor device according to a second exemplary embodiment of the present invention.
본 발명의 제 2실시예에 따른 반도체 소자의 스토리지노드 콘택 형성 방법은, 도 4a에 도시된 바와 같이, 반도체기판(200) 상에 제 2절연막(205), 비트라인(206) 및 상기 비트라인(206)을 덮는 절연 스페이서(207) 형성 공정까지는 본 발명의 제 1실시예와 동일하게 진행된다. 도 4a에서, 미설명된 도면부호 202는 제 1절연막을, 도면부호 203은 제 1콘택을, 도면부호 204는 도전 플러그를 각각 나타낸 것이다.In the method of forming a storage node contact of a semiconductor device according to the second embodiment of the present invention, as shown in FIG. 4A, the second insulating layer 205, the bit line 206, and the bit line are formed on the semiconductor substrate 200. The process of forming the insulating spacer 207 covering the 206 proceeds in the same manner as in the first embodiment of the present invention. In FIG. 4A, reference numeral 202 denotes a first insulating film, reference numeral 203 denotes a first contact, and reference numeral 204 denotes a conductive plug.
이어, 상기 결과의 기판 전면에 제 3절연막(208)을 증착하고 평탄화시킨 다음, 제 1실시예와는 반대로, 스토리지노드 콘택영역을 덮는 감광막 패턴(210)을 형성한다. 이때, 제 3절연막(208)은 BPSG, HDP, TEOS 및 USG막 중 어느 하나를 이용하며, 1000∼10000Å 두께로 형성한다. 또한, 제 3절연막(208)의 평탄화 공정은 상기 절연 스페이서(207) 위로 500∼5000Å 두께 잔류되는 시점까지 상기 제 3절연막에 에치백 또는 화학적 기계적 연마 공정을 진행한다. 한편, 상기 감광막 패턴(210)은 네거티브(negative) 타입을 이용한다.Subsequently, a third insulating layer 208 is deposited and planarized on the entire surface of the resultant substrate, and then, on the contrary to the first embodiment, a photoresist pattern 210 covering the storage node contact region is formed. At this time, the third insulating film 208 uses any one of BPSG, HDP, TEOS, and USG films, and is formed to have a thickness of 1000 to 10000 kHz. In addition, in the planarization process of the third insulating layer 208, an etchback or chemical mechanical polishing process is performed on the third insulating layer until the thickness of 500 to 5000 Å remains on the insulating spacer 207. On the other hand, the photoresist pattern 210 uses a negative type.
그런 다음, 감광막 패턴(210)을 마스크로 하고 상기 절연 스페이서(207) 표면이 노출되는 시점까지 상기 제 3절연막(208)을 건식 식각하여 제 2콘택(209)를 형성한다. 이때, 제 2콘택(209)은 상기 건식 식각 공정에서 감광막 패턴(220)이 비트라인(206)에 대해 정확히 어라인되지 않아 미스어라인이 발생된 경우, 스토리지노드 콘택(SC3)이 도전 플러그(204)와 접촉되는 접촉 면적이 작아지게 된다.Thereafter, the second insulating layer 208 is dry-etched to form a second contact 209 until the photoresist layer pattern 210 is used as a mask and the surface of the insulating spacer 207 is exposed. In this case, when the photoresist pattern 220 is not correctly aligned with respect to the bit line 206 in the dry etching process, a misalignment occurs, the storage node contact SC3 is connected to the conductive plug. The contact area in contact with 204 becomes small.
따라서, 상기 스토리지노드 콘택(SC2)의 바닥면 면적을 확보하기 위해, 도 4b에 도시된 바와 같이, 상기 감광막 패턴을 제거하고 나서, 상기 제 2콘택(209)을 포함한 제 3절연막 상에 실리콘 질화막(미도시)을 증착하고 에치백 또는 화학적 기계적 연마하여 평탄화한다. 이때, 상기 실리콘 질화막(210)은 PECVD 또는 LPCVD 공정을 이용하며, 1000∼5000Å 두께로 형성한다.Therefore, in order to secure the bottom area of the storage node contact SC2, as shown in FIG. 4B, after removing the photoresist pattern, the silicon nitride layer is formed on the third insulating layer including the second contact 209. Deposit (not shown) and planarize by etch back or chemical mechanical polishing. In this case, the silicon nitride film 210 is formed by using a PECVD or LPCVD process, the thickness of 1000 ~ 5000∼.
그런 다음, 100∼2000Å 두께 잔류되는 시점까지 상기 실리콘 질화막을 에치백 또는 화학적 기계적 연마하여 제 2콘택(209)을 매립시키는 베리어막(210)을 형성한다.Thereafter, the silicon nitride film is etched back or chemically mechanically polished until the remaining thickness of 100 to 2000 mm 3 is formed to form the barrier film 210 to fill the second contact 209.
이 후, 도 4c에 도시된 바와 같이, 상기 베리어막(210)을 마스크로 하고 상기 제 3절연막(208) 및 제 2절연막(205)을 습식 식각하여 도전 플러그(204)를 노출시키는 스토리지노드 콘택(SC2)을 형성한다. 이때, 상기 습식 식각 공정에서, 습식액으로 BOE 또는 HF용액을 이용한다. 한편, 상기 베리어막(210)은 제 3절연막(208)이 과도 습식 식각되더라도 이웃한 스토리지노드 콘택(SC3) 간의 전기적 쇼트를 방지하는 역할을 한다.Thereafter, as shown in FIG. 4C, the storage node contact exposes the conductive plug 204 by wet etching the barrier layer 210 and wet etching the third and second insulating layers 208 and 205. (SC2) is formed. At this time, in the wet etching process, BOE or HF solution is used as the wet solution. Meanwhile, the barrier layer 210 may prevent electrical short between adjacent storage node contacts SC3 even when the third insulating layer 208 is excessively wet etched.
이상에서와 같이, 본 발명은 베리어막을 이용하여 절연막을 습식 식각하여 스토리지노드 콘택을 식각함으로써, 감광막 패턴이 비트라인에 대해 정확히 어라인되지 않아 미스어라인이 발생된 경우에도 스토리지노드 콘택의 바닥면 접촉면적을 확보할 수 있다. 또한, 절연막이 과도 습식 식각되더라도 이웃한 스토리지노드 콘택 간의 전기적 쇼트 발생을 방지할 수 있다.As described above, the present invention wets an insulating layer using a barrier film to etch the storage node contact, so that even when the photoresist pattern is not accurately aligned with the bit line, a misalignment occurs, the bottom surface of the storage node contact. Contact area can be secured. In addition, even if the insulating film is excessively wet etched, electrical short between adjacent storage node contacts may be prevented.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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