KR20010081501A - Method for manufacturing a semiconductor device having transistor - Google Patents
Method for manufacturing a semiconductor device having transistor Download PDFInfo
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- KR20010081501A KR20010081501A KR1020000007120A KR20000007120A KR20010081501A KR 20010081501 A KR20010081501 A KR 20010081501A KR 1020000007120 A KR1020000007120 A KR 1020000007120A KR 20000007120 A KR20000007120 A KR 20000007120A KR 20010081501 A KR20010081501 A KR 20010081501A
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- spacer
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- semiconductor substrate
- gate pattern
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 12
- 125000006850 spacer group Chemical group 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 42
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 230000002093 peripheral effect Effects 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 8
- 239000011800 void material Substances 0.000 abstract description 2
- 239000003989 dielectric material Substances 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 트랜지스터를 갖는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a transistor.
반도체 소자의 디자인 룰(design rule)이 감소함에 따라 게이트 사이의 간격은 점점 감소하고, 이에 따라 게이트와 게이트 사이를 절연막으로 매립하는 것이 점점 어려워지고 있으며, 셀 어레이영역이나 주변회로 영역에 트랜지스터를 형성할 때 엘디디(Lightly Doped Drain; LDD)용 스페이서(spacer)를 형성하는 데 제약이 따른다.As the design rule of the semiconductor device decreases, the gap between the gates decreases gradually, thus making it difficult to fill the gaps between the gates and the gates with insulating films, and form transistors in the cell array region or the peripheral circuit region. In this case, there is a restriction in forming a spacer for a lightly doped drain (LDD).
도 1 내지 도 3은 종래의 반도체 소자의 제조방법을 설명하기 위한 단면도들이다.1 to 3 are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
먼저, 도 1을 참조하면, 셀 어레이영역 및 주변회로 영역을 포함하는 반도체기판(2)에 활성영역과 비활성영역을 한정하기 위한 소자분리막(4)을 형성한 다음, 상기 반도체기판 상에 게이트절연막(도시되지 않음)을 형성한다. 이 게이트절연막 위에, 예를 들어 도우프된 폴리실리콘막(6), 텅스텐 실리사이드(8) 및 마스크용 질화막(10)을 차례로 증착한 후 이들을 차례로 이방성식각하여 게이트 패턴을 형성한다. 다음에, 게이트 패턴이 형성된 결과물 상에 절연막을 증착한 다음 이방성 식각하여 상기 게이트 패턴의 측벽에 LDD를 형성하기 위한 스페이서(12)를 형성한다.First, referring to FIG. 1, an isolation layer 4 for defining an active region and an inactive region is formed in a semiconductor substrate 2 including a cell array region and a peripheral circuit region. Then, a gate insulating layer is formed on the semiconductor substrate. (Not shown). For example, a doped polysilicon film 6, a tungsten silicide 8, and a nitride film 10 for a mask are deposited on the gate insulating film in sequence, and then anisotropically etched to form a gate pattern. Next, an insulating film is deposited on the resultant product on which the gate pattern is formed, and then anisotropically etched to form a spacer 12 for forming an LDD on the sidewall of the gate pattern.
참조부호 "t1" 및 "t3"은 스페이서의 두께를, "t2"는 게이트 패턴 사이의 간격을, 그리고 "t4"는 게이트 패턴의 높이를 각각 나타낸다.Reference numerals "t1" and "t3" denote the thickness of the spacer, "t2" denotes the spacing between the gate patterns, and "t4" denotes the height of the gate pattern, respectively.
도 2를 참조하면, 스페이서가 형성된 결과물의 전면에 산화막을 증착하여 상기 게이트 패턴들 사이를 매립하는 층간절연막(14)을 형성한다.Referring to FIG. 2, an oxide layer is deposited on the entire surface of the resultant product on which spacers are formed to form an interlayer insulating layer 14 that fills the gate patterns.
이 때, 반도체 소자가 고집적화되어 디자인 룰이 0.1㎛ 정도가 되면, 워드라인의 저항과 관련하여 게이트 패턴의 높이(도 1의 t4)는 감소하지 않고 게이트 사이의 거리(도 1의 2t1+t2)만 감소하게 되므로, 상기 층간절연막 증착시 게이트 패턴들 사이에 보이드(A)가 생기기 쉽다.At this time, when the semiconductor device is highly integrated and the design rule is about 0.1 µm, the distance between the gates (2t1 + t2 in FIG. 1) without decreasing the height of the gate pattern (t4 in FIG. 1) in relation to the resistance of the word line. Since only a decrease is performed, voids A are likely to occur between gate patterns during the deposition of the interlayer insulating film.
도 3을 참조하면, 상기 층간절연막을 패터닝하여 반도체기판(2)의 활성영역을 노출시키는 콘택홀을 형성한다. 다음에, 결과물 상에 도우프된 폴리실리콘과 같은 도전물질을 증착한 다음 패터닝하여 상기 반도체기판(2)과 접속된 패드층(16)을 형성한다. 상기 패드층(16)을 형성하기 위한 도전물질 증착시 게이트 패턴 사이에 형성되었던 보이드(도 2의 A)에도 도전물질이 증착되어 패드층(16) 사이에 브리지(bridge)(B)가 발생하여 소자의 신뢰성을 악화시킬 수 있다.Referring to FIG. 3, the interlayer insulating layer is patterned to form a contact hole exposing an active region of the semiconductor substrate 2. Next, a conductive material such as doped polysilicon is deposited on the resultant and then patterned to form a pad layer 16 connected to the semiconductor substrate 2. The conductive material is also deposited on the voids (A of FIG. 2) formed between the gate patterns during the deposition of the conductive material for forming the pad layer 16, thereby generating a bridge B between the pad layers 16. The reliability of the device can be deteriorated.
상기한 바와 같이, 종래의 방법에 의하면, 게이트 패턴들 사이를 매립하는 층간절연막 증착시 보이드의 발생을 최대한 억제하기 위하여 게이트의 측벽에 형성하는 스페이서의 폭을 감소시켜야 한다. 그러나, 주변회로 영역에 형성되는 트랜지스터의 LDD 길이는 스페이서의 폭에 의해 결정되므로, 스페이서의 폭을 감소시키면 LDD의 길이도 감소하게 되어 펀치쓰루(punchthrough) 등의 문제가 발생하기 쉽다.As described above, according to the conventional method, the width of the spacers formed on the sidewalls of the gate should be reduced in order to suppress the generation of voids during the deposition of the interlayer insulating film filling the gate patterns. However, since the length of the LDD of the transistor formed in the peripheral circuit region is determined by the width of the spacer, reducing the width of the spacer also reduces the length of the LDD, which is likely to cause problems such as punchthrough.
따라서, 본 발명이 이루고자 하는 기술적 과제는, 셀 어레이영역에 형성되는 게이트 스페이서의 폭과 상관없이 주변회로 영역에 형성되는 트랜지스터의 LDD 길이를 조절할 수 있으며, 게이트 사이를 매립하기 위한 층간절연막 증착시 보이드가 발생되지 않도록 하는 반도체 소자의 제조방법을 제공하는 데 있다.Therefore, the technical problem to be achieved by the present invention is to adjust the LDD length of the transistor formed in the peripheral circuit region irrespective of the width of the gate spacer formed in the cell array region, and to void during deposition of an interlayer insulating film to fill the gates. It is to provide a method for manufacturing a semiconductor device so that does not occur.
도 1 내지 도 3은 종래의 반도체 소자의 제조방법을 설명하기 위한 단면도들이다.1 to 3 are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
도 4 내지 도 10은 본 발명에 의한 반도체 소자의 제조방법을 설명하기 위한 단면도들이다.4 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
2, 22.....반도체기판 4, 24.....소자분리막2, 22 ..... semiconductor substrate 4, 24 ..... element separator
6, 26.....폴리실리콘막 8, 28.....텅스텐 실리사이드막6, 26 ... polysilicon film 8, 28 ... tungsten silicide film
10, 30.....마스크용 질화막 12,34',40'.....스페이서(층)10, 30 ..... mask nitride mask 12,34 ', 40' ..... spacer (layer)
14,38,42...층간절연막 16, 44.....패드층(플러그)14,38,42 Interlayer insulating film 16, 44 ... Pad layer (plug)
32.........식각 방지막32 ......... Anti-etching film
상기 과제를 이루기 위하여 본 발명에 의한 반도체 소자의 제조방법은, 셀어레이영역 및 주변회로 영역의 반도체기판 상에 게이트 패턴을 형성하는 단계와, 반도체기판에 소오스/드레인용 불순물을 주입하는 단계와, 결과물 상에 식각 방지막을 형성하는 단계와, 주변회로 영역의 게이트 패턴의 측벽에 제1 스페이서를 형성하는 단계와, 반도체기판에 LDD용 불순물을 주입한 후 제1 스페이서를 제거하는 단계와, 게이트 패턴들 사이를 매립하되, 게이트 패턴의 상부를 노출시키도록 제1 층간절연막을 형성하는 단계와, 게이트 패턴의 노출된 측벽에 제2 스페이서를 형성하는 단계와, 게이트 패턴들 사이를 완전히 매립하는 제2 층간절연막을 형성하는 단계, 및 제1 및 제2 층간절연막을 관통하여 반도체기판의 활성영역과 접속된 도전층을 형성하는 단계를 구비한다.In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes forming a gate pattern on a semiconductor substrate in a cell array region and a peripheral circuit region, injecting source / drain impurities into the semiconductor substrate, Forming an etch stop layer on the resultant, forming a first spacer on a sidewall of a gate pattern of a peripheral circuit region, injecting an LDD impurity into a semiconductor substrate, and then removing the first spacer; Forming a first interlayer dielectric layer so as to expose the upper portion of the gate pattern; forming a second spacer on exposed sidewalls of the gate pattern; and filling a second gap between the gate patterns. Forming an interlayer insulating film, and forming a conductive layer connected to the active region of the semiconductor substrate through the first and second interlayer insulating films. The rain.
본 발명에 있어서, 상기 식각 방지막은 실리콘질화막(SiN), 실리콘 카바이드(SiC) 또는 실리콘산화질화막(SiON)으로 형성하고, 상기 제1 및 제2 스페이서는 실리콘산화막(SiO2)으로 형성한다. 그리고, 상기 제1 스페이서를 제거하는 단계에서, 상기 식각 방지막에 대한 식각 선택비가 5:1 이상인 조건으로 진행하는 것이 바람직하다.In the present invention, the etch stop layer is formed of silicon nitride (SiN), silicon carbide (SiC) or silicon oxynitride (SiON), and the first and second spacers are formed of silicon oxide (SiO 2 ). In addition, in the removing of the first spacer, the etching selectivity to the etch stop layer may be performed under a condition of 5: 1 or more.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 4 내지 도 10은 본 발명에 의한 반도체 소자의 제조방법을 설명하기 위한 단면도들이다.4 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 4를 참조하면, 셀 어레이영역 및 주변회로 영역을 포함하는 반도체기판(22)에 활성영역과 비활성영역을 한정하기 위한 소자분리막(24)을 형성한 다음, 상기 반도체기판 상에 게이트절연막(도시되지 않음)을 형성한다. 이 게이트절연막 위에, 예를 들어 도우프된 폴리실리콘막(26), 텅스텐 실리사이드(28) 및 마스크용 질화막(30)을 차례로 증착한 후 이들을 이방성 식각하여 게이트 패턴을 형성한다. 다음, 상기 게이트 패턴을 마스크로 하여 상기 반도체기판에 소오스/드레인을 형성하기 위한 저농도의 불순물 이온을 주입한다.Referring to FIG. 4, an isolation layer 24 for defining active and inactive regions is formed on a semiconductor substrate 22 including a cell array region and a peripheral circuit region, and then a gate insulating layer (not shown) is formed on the semiconductor substrate. Not formed). For example, a doped polysilicon film 26, a tungsten silicide 28, and a mask nitride film 30 are sequentially deposited on the gate insulating film, and then anisotropically etched to form a gate pattern. Next, a low concentration of impurity ions for forming a source / drain is implanted into the semiconductor substrate using the gate pattern as a mask.
도 5를 참조하면, 도 4의 결과물 상에 실리콘질화막(SiN), 탄화실리콘(SiC)막 또는 실리콘산화질화막(SiON) 등과 같이, 게이트 스페이서를 식각하기 위한 식각공정에서 선택적으로 제거되지 않는 물질을 증착하여 식각방지막(32)을 형성한다. 이 식각방지막(32)은 후속 콘택홀 형성공정시 노출되는 필드영역의 산화막이 식각되는 것을 방지하고, LDD용 스페이서 제거시 필드산화막의 식각을 방지하는 역할을 한다. 다음에, 상기 식각방지막(32) 위에 산화막을 증착하여 LDD용 스페이서층(34)을 형성한다. 이 스페이서층(34)은 후속 공정에서 주변회로 영역의 LDD를 형성한 다음에 제거되는 것으로, 형성하고자 하는 LDD의 폭을 고려하여 그 두께를 결정한다.Referring to FIG. 5, a material that is not selectively removed in an etching process for etching a gate spacer, such as a silicon nitride film (SiN), a silicon carbide (SiC) film, or a silicon oxynitride film (SiON), may be formed on the resultant of FIG. 4. Deposition is performed to form an etch stop layer 32. The etch stop layer 32 prevents the oxide layer of the field region exposed during the subsequent contact hole forming process from being etched and prevents the field oxide layer from being etched when the LDD spacer is removed. Next, an oxide film is deposited on the etch stop layer 32 to form the LDD spacer layer 34. The spacer layer 34 is removed after the LDD of the peripheral circuit region is formed in a subsequent process, and the thickness thereof is determined in consideration of the width of the LDD to be formed.
도 6을 참조하면, LDD용 스페이서층(34)이 형성된 결과물 상에, 주변회로 영역을 노출시키는 포토레지스트 패턴(36)을 형성한 다음, 주변회로 영역의 상기 LDD용 스페이서층(34)을 식각하여 주변회로 영역의 게이트 패턴의 측벽에 LDD용 스페이서(34')를 형성한다. 상기 스페이서(34') 형성을 위한 식각공정은 하부에 형성된 식각 방지막(32)에 대해 식각 선택비가 5:1 정도로 높은 조건으로 진행하며, 식각 방지막(32)이 노출되면 식각을 종료한다. 다음에, 상기 반도체기판에 소오스/드레인용 불순물이온을 고농도로 주입한다.Referring to FIG. 6, a photoresist pattern 36 exposing a peripheral circuit region is formed on a resultant product on which the LDD spacer layer 34 is formed, and then the LDD spacer layer 34 of the peripheral circuit region is etched. Thus, the LDD spacer 34 'is formed on the sidewall of the gate pattern of the peripheral circuit region. In the etching process for forming the spacer 34 ′, the etching selectivity of the spacer 34 ′ is lowered to about 5: 1, and the etching is terminated when the etching prevention layer 32 is exposed. Next, source / drain impurity ions are injected into the semiconductor substrate at a high concentration.
도 7을 참조하면, 상기 포토레지스트 패턴을 제거한 다음, LDD용 스페이서층(34) 및 스페이서(34')를 제거한다. 그 결과물의 전면에 산화막을 증착하여 제1 층간절연막(38)을 형성하는데, LDD용 스페이서가 제거된 상태이기 때문에 게이트 패턴들 사이의 어스펙트 비(aspect ratio)가 감소되므로 제1 층간절연막(38)으로 게이트 패턴들 사이를 보이드 없이 용이하게 매립할 수가 있다. 상기 제1 층간절연막(38)은 고밀도 플라즈마(HDP; High Density Plasma)를 이용한 산화막 또는 도우프되지 않은 산화막(USG; Undoped Silica Glass)으로 형성할 수 있다.Referring to FIG. 7, the photoresist pattern is removed, and then the LDD spacer layer 34 and the spacer 34 ′ are removed. The first interlayer insulating film 38 is formed by depositing an oxide film on the entire surface of the resultant. Since the LDD spacer is removed, the aspect ratio between the gate patterns is reduced, so that the first interlayer insulating film 38 is formed. ), The gate patterns can be easily buried without voids. The first interlayer insulating layer 38 may be formed of an oxide film using a high density plasma (HDP) or an undoped silica glass (USG).
도 8을 참조하면, 소정의 습식 또는 건식식각 공정으로 상기 제1 층간절연막(38)의 상부를 일정 두께 식각하여 리세스(recess)시킨 다음, 그 결과물 상에 스페이서용 절연막(40)을 형성한다. 상기 스페이서용 절연막(40)은 산화막과의 식각선택비가 커서 후속 SAC 식각시 잘 식각되지 않는 물질, 예를 들어 실리콘질화막(SiN)으로 형성하는 것이 바람직하다.Referring to FIG. 8, the upper portion of the first interlayer insulating layer 38 is etched and recessed by a predetermined wet or dry etching process to form a spacer insulating film 40 on the resultant. . The spacer insulating layer 40 is preferably formed of a material that is not easily etched during subsequent SAC etching, for example, silicon nitride layer (SiN) due to a large etching selectivity with respect to the oxide layer.
도 9를 참조하면, 상기 스페이서용 절연막(도 8의 40)을 이방성 식각하여 게이트 패턴의 상부 측벽에 스페이서(40')를 형성한다. 이 스페이서(40')의 폭이 게이트 스페이서의 폭이 된다. 이어서, 절연막을 증착하여 스페이서(40')가 형성된 결과물을 덮는 제2 층간절연막(42)을 형성한다. 이 때에도 게이트 패턴의 하부는 제1 층간절연막(38)으로 매립되어 있어 어스펙트 비가 낮기 때문에 보이드의 발생 없이 게이트 패턴들 사이를 매립할 수 있다.Referring to FIG. 9, the spacer insulating layer 40 (FIG. 8) is anisotropically etched to form a spacer 40 ′ on an upper sidewall of the gate pattern. The width of this spacer 40 'becomes the width of the gate spacer. Subsequently, an insulating film is deposited to form a second interlayer insulating film 42 covering the resultant formed spacer 40 '. In this case, since the lower portion of the gate pattern is buried in the first interlayer insulating layer 38, the aspect ratio is low, so that the gate patterns may be buried without generating voids.
도 10을 참조하면, 통상의 사진공정으로 포토레지스트 패턴(도시되지 않음)을 형성한 다음, 이 포토레지스트 패턴을 마스크로 하여 제2 층간절연막(42) 및 제1 층간절연막(38)을 식각하여 반도체기판(22)의 활성영역을 노출시키는 콘택홀을 형성한다. 이 때, 층간절연막(42, 38)을 구성하는 산화막에 대해 스페이서(40')를 구성하는 질화막의 식각 선택비가 크기 때문에 상기 스페이서(40')에 자기정합적으로 콘택홀을 형성할 수 있다.Referring to FIG. 10, a photoresist pattern (not shown) is formed by a normal photolithography process, and then the second interlayer insulating film 42 and the first interlayer insulating film 38 are etched using the photoresist pattern as a mask. A contact hole for exposing the active region of the semiconductor substrate 22 is formed. At this time, since the etch selectivity of the nitride film constituting the spacer 40 'with respect to the oxide films constituting the interlayer insulating films 42 and 38 is large, a contact hole may be formed in the spacer 40' in a self-aligned manner.
다음, 결과물 상에 도전물질을 증착하고 이를 이방성 식각하여, 반도체기판(22)의 활성영역과 상부 도전층을 접속시키는 플러그(44)를 형성한다. 또는, 상기 반도체기판의 활성영역과 접속된 스토리지 전극(도시되지 않음)을 형성할 수도 있다.Next, a conductive material is deposited on the resultant and anisotropically etched to form a plug 44 connecting the active region of the semiconductor substrate 22 and the upper conductive layer. Alternatively, a storage electrode (not shown) connected to the active region of the semiconductor substrate may be formed.
이상 본 발명을 상세히 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고 본 발명의 기술적 사상내에서 당업자에 의해 많은 변형 및 개량이 가능하다.Although the present invention has been described in detail above, the present invention is not limited to the above embodiments, and many modifications and improvements can be made by those skilled in the art within the technical idea of the present invention.
상술한 본 발명에 의한 반도체 소자의 제조방법에 의하면, 셀 어레이영역에 형성되는 게이트 스페이서의 폭과 상관없이 주변회로 영역에 형성되는 트랜지스터의 LDD 길이를 조절할 수 있으며, 게이트들 사이를 매립하기 위한 층간절연막 증착시 보이드가 발생되지 않도록 할 수 있으므로, 소자의 신뢰성을 향상시킬 수가 있다.According to the method of manufacturing a semiconductor device according to the present invention described above, regardless of the width of the gate spacer formed in the cell array region, the LDD length of the transistor formed in the peripheral circuit region may be adjusted, and the interlayer for filling the gates may be interposed. Since voids can be prevented from occurring during the deposition of the insulating film, the reliability of the device can be improved.
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| KR100675947B1 (en) * | 2006-09-28 | 2007-01-30 | 씨제이 푸드 시스템 주식회사 | A heating structure for a heating cabinet |
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| KR100675947B1 (en) * | 2006-09-28 | 2007-01-30 | 씨제이 푸드 시스템 주식회사 | A heating structure for a heating cabinet |
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