CN113497143A - Semiconductor structure and method for forming semiconductor structure - Google Patents

Semiconductor structure and method for forming semiconductor structure Download PDF

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Publication number
CN113497143A
CN113497143A CN202010252058.0A CN202010252058A CN113497143A CN 113497143 A CN113497143 A CN 113497143A CN 202010252058 A CN202010252058 A CN 202010252058A CN 113497143 A CN113497143 A CN 113497143A
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layer
forming
initial
gate
semiconductor structure
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Chinese (zh)
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章毅
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method for forming the same, comprising: the substrate comprises a dense area, the dense area comprises a plurality of first areas and second areas, and the second areas are positioned between the adjacent first areas; a plurality of gate structures located on the first region of the substrate; the grid structure is positioned in the dielectric layer; a first opening located on a second region of the substrate, the first opening extending from the dielectric layer to the substrate; and the diffusion-proof layer is positioned on the top of the first opening and seals the first opening into a closed cavity. The performance of the semiconductor structure is improved.

Description

Semiconductor structure and method for forming semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, the semiconductor industry has progressed to nanotechnology process nodes due to demands for high device density, high performance, and low cost, and the fabrication of semiconductor devices is limited by various physical limitations.
As CMOS device dimensions continue to shrink, challenges from manufacturing and design aspects have prompted the development of three-dimensional designs such as fin field effect transistors (finfets). Compared with the existing planar transistor, the FinFET is an advanced semiconductor device for process nodes of 20nm and below, can effectively control the short channel effect which is difficult to overcome due to the fact that the device is scaled down, can also effectively improve the density of a transistor array formed on a substrate, and meanwhile, a grid electrode in the FinFET is arranged around a fin (a fin-shaped channel), so that static electricity can be controlled from three surfaces, and the performance in the aspect of static electricity control is more outstanding.
In order to further increase the density of devices in the FinFET process, many Single Diffusion Break (SDB) may be designed to form more narrower shallow trench isolations, so as to save the area of the gate array.
However, the process and performance of the conventional method for forming shallow trench isolation by cutting off the single diffusion region still need to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a dense area, the dense area comprises a plurality of first areas and second areas, and the second areas are positioned between the adjacent first areas; a plurality of gate structures located on the first region of the substrate; the grid structure is positioned in the dielectric layer; a first opening located on a second region of the substrate, the first opening extending from the dielectric layer to the substrate; and the diffusion-proof layer is positioned on the top of the first opening and seals the first opening into a closed cavity.
Optionally, the substrate includes a base and a fin structure located on the base; the gate structure crosses the fin structure; a bottom plane of the first opening is lower than or flush with a bottom plane of the fin structure.
Optionally, the diffusion barrier layer is further located on the surface of the transition layer.
Optionally, the substrate further comprises a sparse region.
Optionally, the device distribution density of the sparse region is less than the device distribution density of the dense region.
Optionally, the aspect ratio range of the first opening is: 4 to 10.
Optionally, the method further includes: and the barrier layer is positioned on the top surface of the first region gate structure.
Optionally, the material of the barrier layer is different from that of the dielectric layer.
Optionally, the material of the barrier layer comprises a dielectric material, and the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, silicon oxycarbide and silicon oxycarbide.
Optionally, the material of the diffusion-preventing layer is different from that of the dielectric layer; the material of the diffusion preventing layer is different from that of the transition layer.
Optionally, the material of the diffusion preventing layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, and silicon oxycarbide.
Optionally, the material of the transition layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, and silicon oxycarbide.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a dense area, the dense area comprises a plurality of first areas and second areas, and the second areas are positioned between the adjacent first areas; forming a plurality of initial gate structures on the first region and the second region; forming a dielectric layer on the substrate, wherein the initial grid structure is positioned in the dielectric layer, and the dielectric layer is exposed out of the surface of the initial grid structure; removing the initial grid structure on the second area, and forming a first opening on the second area of the substrate, wherein the first opening extends from the dielectric layer to the substrate; forming a transition layer on the bottom surface and the side wall surface of the first opening; and after the transition layer is formed, forming an anti-diffusion layer which is positioned at the top of the first opening and seals the first opening into a closed cavity.
Optionally, the substrate includes a base and a fin structure located on the base; the initial gate structure spans the fin structure; a bottom plane of the first opening is lower than or flush with a bottom plane of the fin structure.
Optionally, the diffusion barrier layer is further located on the surface of the transition layer.
Optionally, the substrate further comprises a sparse region; the device distribution density of the sparse region is less than that of the dense region.
Optionally, the initial gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the dielectric constant of the material of the gate dielectric layer is less than or equal to 3.9, and the material of the gate dielectric layer comprises silicon oxide; the material of the gate layer comprises polysilicon.
Optionally, the initial gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the dielectric constant of the material of the gate dielectric layer is greater than 3.9, and the material of the gate dielectric layer comprises hafnium oxide or aluminum oxide; the material of the gate layer comprises a metal comprising tungsten.
Optionally, the forming method of the initial gate structure includes: forming a dummy gate structure on a substrate; forming a dielectric layer on a substrate, wherein the dummy gate structure is positioned in the dielectric layer; removing the pseudo gate structure, and forming a gate opening in the dielectric layer; and forming the initial gate structure in the gate opening.
Optionally, the forming method of the dielectric layer includes: forming a dielectric material layer on a substrate; and flattening the dielectric material layer until the top surface of the pseudo gate structure is exposed to form the dielectric layer, wherein the surface of the dielectric layer is provided with a first groove.
Optionally, the method for forming the first opening includes: forming a mask structure on the surface of the substrate, wherein the mask structure exposes the surface of the initial grid structure on the second region; and etching the initial grid structure and the substrate by taking the mask structure as a mask, and forming a first opening on the second region of the substrate.
Optionally, before forming the mask structure, the method further includes: etching back the initial grid structure, forming a grid structure on the first area and the second area, and forming a second opening in the dielectric layer at the top of the grid structure; forming an initial barrier layer in the second opening and on the surface of the dielectric layer, wherein a second groove is formed on the surface of the initial barrier layer on the dielectric layer; the mask structure exposes the surface of the initial barrier layer on the second region.
Optionally, before forming a mask structure on the surface of the initial barrier layer, the method further includes: forming a sacrificial layer on the surface of the initial barrier layer; the sacrificial layer is located in the second groove, and the mask structure is located on the surfaces of the sacrificial layer and the initial barrier layer.
Optionally, the method for forming the sacrificial layer includes: forming a sacrificial material layer on the surface of the initial barrier layer; and flattening the sacrificial material layer until the surface of the initial barrier layer is exposed, and forming a sacrificial layer in the second groove.
Optionally, the material of the sacrificial layer is different from the material of the initial barrier layer.
Optionally, the material of the initial barrier layer is different from the material of the dielectric layer.
Optionally, the material of the initial barrier layer comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, and combinations thereof.
Optionally, the material of the initial barrier layer is different from the material of the transition layer.
Optionally, the material of the transition layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, and silicon oxycarbide.
Optionally, the mask structure comprises a hard mask structure; a liner layer on the hard mask structure; and the photoresist layer is positioned on the liner layer and exposes the surface of the liner layer on the second area.
Optionally, the hard mask structure includes a first hard mask layer and a second hard mask layer on the first hard mask layer.
Optionally, the method for forming the diffusion barrier includes: forming a diffusion-proof material layer in the first opening and on the surface of the initial barrier layer; flattening the anti-diffusion material layer to form an initial anti-diffusion layer in the first opening; and flattening the initial barrier material layer and the initial anti-diffusion layer until the surface of the dielectric layer is exposed, forming a barrier layer on the top of the gate structure, and forming an anti-diffusion layer in the first opening.
Optionally, the process of forming the diffusion-preventing material layer includes a chemical vapor deposition process.
Optionally, before planarizing the diffusion-preventing material layer, the method further includes: and forming a covering layer on the diffusion-proof material layer.
Optionally, the process for planarizing the initial barrier material layer and the initial anti-diffusion layer includes a Hydra etching process or a gas cluster ion beam treatment process.
Optionally, the aspect ratio range of the first opening is: 4 to 10.
Optionally, the material of the diffusion preventing layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, and silicon oxycarbide.
Optionally, after forming the diffusion barrier layer, removing the initial barrier layer, and forming a gate plug on top of the gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the semiconductor structure of the technical scheme of the invention, the anti-diffusion layer is positioned at the top of the first opening and seals the first opening into a closed cavity. The closed cavity can play a good role in isolating ions in the substrate and the medium layer, so that the electrical properties of the device structures at two sides of the anti-diffusion layer can not interfere with each other; meanwhile, the anti-diffusion layer with the closed cavity has a smaller dielectric constant, so that the parasitic capacitance of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved.
Furthermore, the anti-diffusion layer is also positioned on the surface of the transition layer, and the transition layer can further improve the blocking effect of the anti-diffusion layer; meanwhile, the transition layer can stabilize the stress between the dielectric layer and the diffusion-preventing layer, and the defect of the semiconductor structure caused by unbalanced stress is avoided, so that the performance of the semiconductor structure is influenced.
In the forming method of the semiconductor structure in the technical scheme of the invention, the initial grid structure on the second area is removed, the first opening is formed on the second area of the substrate, and then the anti-diffusion layer is formed in the first opening, is positioned at the top of the first opening and seals the first opening into the closed cavity. The closed cavity can play a good role in isolating ions in the substrate and the medium layer, so that the electrical properties of the device structures on two sides of the anti-diffusion layer can not interfere with each other, and the electrical property stability of the formed semiconductor structure is improved; meanwhile, the anti-diffusion layer with the closed cavity has a smaller dielectric constant, so that the parasitic capacitance of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved.
Furthermore, the surface of the side wall of the first opening is provided with a transition layer, the anti-diffusion layer is also positioned on the surface of the transition layer, and the transition layer can further improve the blocking effect of the anti-diffusion layer; meanwhile, the transition layer can stabilize the stress between the dielectric layer and the diffusion-preventing layer, and the defect of the semiconductor structure caused by unbalanced stress is avoided, so that the performance of the semiconductor structure is influenced.
Furthermore, the barrier layer and the anti-diffusion layer can be formed simultaneously, so that the process flow is simplified, and the working efficiency is improved.
Further, a sacrificial layer is formed on the surface of the initial barrier layer, and a mask structure is formed on the sacrificial layer, so that the sacrificial layer can fill and level the surface of the initial barrier layer, the flatness of a plane on which the mask structure is formed is high, and the position accuracy of a pattern formed by the mask structure is high.
Further, the process of planarizing the diffusion-preventing material layer and the initial barrier material layer includes: the method comprises the following steps of performing a Hydra etching process or a gas cluster ion beam treatment process, wherein the etching rate of the Hydra etching process on silicon oxide and silicon nitride is basically equal, and the etching rate of the gas cluster ion beam treatment process on the silicon oxide and the silicon nitride is basically equal, so that the etching rate of the Hydra etching process or the gas cluster ion beam treatment process on the initial barrier layer and the initial dielectric layer is basically equal, the thickness of the barrier layer formed in a dense area and a sparse area is uniform, the barrier layer is removed subsequently, and when a grid plug electrically connected with a grid structure is formed, the grid plug is in good contact with the grid structure, and the uniformity of the device structure performance of the dense area and the sparse area is good.
Drawings
FIGS. 1-3 are cross-sectional views illustrating a semiconductor structure forming process according to an embodiment;
fig. 4 to 14 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background art, the process and performance of the conventional method for forming shallow trench isolation by cutting off the single diffusion region still need to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 to 3 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment.
Referring to fig. 1, a substrate 100 is provided; the substrate 100 has a fin 101 thereon; the substrate 100 is provided with a plurality of dummy gate structures 103, and the dummy gate structures 103 cross over the fin portion 101; the substrate 100 is provided with a dielectric layer 102, and the dummy gate structure 103 is located in the dielectric layer 102.
Referring to fig. 2, a mask structure (not shown) is formed on the substrate 100, wherein the mask structure exposes a portion of the top surface of the dummy gate structure 103; removing a part of the dummy gate structure 103 and the fin portion 101 by using the mask structure as a mask, and forming an opening (not shown) in the dielectric layer 102; an anti-diffusion structure 104 is formed within the opening.
Referring to fig. 3, the dummy gate structure 103 is removed to form a gate structure 105.
In the formation process of the semiconductor structure, the diffusion preventing structure 104 is used for blocking ion diffusion in the fin portion 101, so that when different devices are formed on two sides of the diffusion preventing structure 104, the diffusion preventing structure 104 can play a role in electrical isolation.
However, the depth-to-width ratio of the opening formed by removing part of the dummy gate structure 103 and the fin 101 is large, so that when the anti-diffusion structure 104 is formed in the opening by a deposition process, the formed anti-diffusion structure 104 is loose and has holes. When the dummy gate structure 103 is subsequently removed to form the gate structure 105, the gate structure 105 is made of a metal, and the metal material fills the hole of the diffusion preventing structure 104, so that the diffusion preventing capability of the diffusion preventing structure 104 is weakened, and the semiconductor structure has a risk of short circuit, which affects the performance of the formed semiconductor structure.
In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, wherein a diffusion preventing structure having a sealed cavity is formed, and the sealed cavity can perform a good blocking function on ions in a substrate and in a dielectric layer, so that electrical properties of device structures on two sides of the diffusion preventing structure can not interfere with each other, thereby improving electrical property stability of the formed semiconductor structure; meanwhile, the diffusion-preventing structure with the closed cavity has a smaller dielectric constant, so that the parasitic capacitance of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 14 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 4, a substrate is provided, the substrate includes a dense area, the dense area includes a plurality of first areas I and second areas II, and the second areas II are located between adjacent first areas I.
In this embodiment, the substrate further includes a sparse region a; the device distribution density of the sparse area A is smaller than that of the dense area.
The substrate includes a base 200 and a fin structure 201 on the base 200.
The substrate 200 is made of semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, or silicon on insulator; the fin structure 201 may be made of a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or silicon on insulator.
In the present embodiment, the material of the substrate 200 includes silicon; the material of the fin structure 201 includes silicon.
In other embodiments, the substrate comprises a planar substrate.
Referring to fig. 5, a plurality of initial gate structures 203 are formed on the substrate, wherein the initial gate structures 203 cross over the fin structure 201.
The initial gate structure 203 includes a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.
In this embodiment, the dielectric constant of the gate dielectric layer material is greater than 3.9, and the gate dielectric layer material includes hafnium oxide or aluminum oxide; the material of the gate layer comprises a metal comprising tungsten.
In another embodiment, the dielectric constant of the gate dielectric layer material is less than or equal to 3.9, and the material of the gate dielectric layer comprises silicon oxide; the material of the gate layer comprises polysilicon.
The method for forming the initial gate structure 203 comprises the following steps: forming a dummy gate structure (not shown) on the substrate; forming a dielectric layer 202 on the substrate, wherein the dummy gate structure is located in the dielectric layer 202; removing the dummy gate structure and forming a gate opening (not shown) in the dielectric layer 202; and forming the initial gate structure 203 in the gate opening, wherein the dielectric layer 202 exposes the surface of the initial gate structure 203.
The forming method of the dielectric layer 202 comprises the following steps: forming a layer of dielectric material (not shown) on a substrate; and flattening the dielectric material layer until the top surface of the dummy gate structure is exposed to form the dielectric layer 202, wherein the surface of the dielectric layer 202 is provided with a first groove 204.
In this embodiment, the planarization process is a chemical mechanical polishing process, and the etching rate of the chemical mechanical polishing process to the dielectric material layer is relatively high, so that when the top surface of the dummy gate structure is completely exposed, the first groove 204 is formed on the surface of the dielectric layer 202.
The material of the dielectric layer 202 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, and silicon oxycarbide.
In this embodiment, the material of the dielectric layer 202 includes silicon oxide.
Referring to fig. 6, the initial gate structure is etched back, a gate structure 205 is formed on the dense region and the sparse region, and a second opening (not shown) is formed in the dielectric layer 202 on top of the gate structure 205.
With continued reference to fig. 6, an initial barrier layer 207 is formed in the second opening and on the surface of the dielectric layer 202, and a second recess 206 is formed on the surface of the initial barrier layer 207 on the dielectric layer 202.
The material of the initial barrier layer 207 is different from the material of the dielectric layer 202.
The material of the initial barrier layer 207 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbo nitride oxide, and silicon oxycarbide.
In this embodiment, the material of the initial barrier layer 207 comprises silicon nitride.
The material of the initial blocking layer 207 is different from that of the dielectric layer 202, so that the blocking layer formed subsequently has a larger etching selection ratio with the dielectric layer 202, a conductive plug is formed at the top of the gate structure 205 subsequently, and when the blocking layer at the top of the gate structure 205 is removed, the process for removing the blocking layer has less damage to the dielectric layer 202, so that the position of the conductive plug can be formed at the top of the gate structure 205 in a self-alignment manner.
The process of forming the initial barrier layer 207 includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the initial barrier layer 207 includes a chemical vapor deposition process. Since the dielectric layer 202 has the first recess 204, the surface of the initial barrier layer 207 formed on the dielectric layer 202 by using the chemical vapor deposition process also has the second recess 206.
Referring to fig. 7, a sacrificial layer 208 is formed on the surface of the initial barrier layer, and the sacrificial layer 208 is located in the second recess 206.
And forming a sacrificial layer 208 on the surface of the initial barrier layer 207, so that when a mask structure is formed on the sacrificial layer 208 in the following step, the sacrificial layer 208 can fill and level the surface of the initial barrier layer 207, the flatness of the plane on which the mask structure is formed is high, the position accuracy of a pattern formed by the mask structure is high, the gate structure and the fin structure on the second region II can be accurately removed to form a first opening, and an anti-diffusion layer is formed in the first opening.
The method for forming the sacrificial layer 208 comprises the following steps: forming a sacrificial material layer (not shown) on the surface of the initial barrier layer 207; the sacrificial material layer is planarized until the surface of the initial barrier layer 207 is exposed, forming a sacrificial layer 208 within the second recess 206.
The material of the sacrificial layer 208 is different from the material of the initial barrier layer 207.
The material of the sacrificial layer 208 comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbo nitride, and silicon oxycarbide in combination.
In the present embodiment, the material of the sacrificial layer 208 includes silicon oxide.
The material of the sacrificial layer 208 is different from the material of the initial barrier layer 207, so that when the sacrificial material layer is planarized, the planarization process can stop at the surface of the initial barrier layer 207, so that the sacrificial layer 208 can be formed in the second recess 206.
The process of forming the sacrificial material layer includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the sacrificial material layer includes a chemical vapor deposition process.
Referring to fig. 8, a mask structure is formed on the surface of the sacrificial layer 208 and the surface of the initial barrier layer 207, and the mask structure exposes the surface of the gate structure 205 on the second region II.
The mask structure comprises a hard mask structure; a pad layer 211 on the hardmask structure; a photoresist layer 212 on the pad layer 211, the photoresist layer 212 exposing the surface of the pad layer 211 on the second region.
The hard mask structure includes a first hard mask layer 209 and a second hard mask layer 210 on the first hard mask layer 209. The first hard mask layer 209 is a different material than the second hard mask layer 210.
The material of the first hard mask layer 209 comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon carbide; the material of the second hard mask layer 210 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbide.
In this embodiment, the material of the first hard mask layer 209 includes silicon nitride; the material of the second hard mask layer 210 includes silicon oxide.
The material of the first hard mask layer 209 is different from the material of the second hard mask layer 210, so that the pattern transfer for forming the first opening is stable, and the position of the first opening formed subsequently is accurate.
The material of the pad layer 211 includes an organic material or an inorganic material. In this embodiment, the material of the liner layer 211 includes an organic material, and the organic material includes amorphous carbon.
Referring to fig. 9, the gate structure 205 and the fin structure 201 are etched using the mask structure as a mask, and a first opening 213 is formed in the second region II of the substrate, where a bottom plane of the first opening 213 is lower than or equal to a bottom plane of the fin structure 201.
The bottom of the first opening 213 is lower than or flush with the bottom plane of the fin structure 201, so that when an anti-diffusion layer is formed in the first opening 213 subsequently, the anti-diffusion layer can obstruct ion diffusion in the fin structure 201, and when different devices are formed on two sides of the anti-diffusion layer, the anti-diffusion layer can play a good role in electrical isolation, so that the electrical properties of the device structures on two sides of the anti-diffusion layer can not interfere with each other, and the electrical property stability of the formed semiconductor structure is improved.
In this embodiment, the aspect ratio range of the first opening 213 is: 4 to 10.
The depth-to-width ratio range of the first opening 213 is 4-10, so that when the anti-diffusion layer is formed in the first opening 213 in the following process, the anti-diffusion layer on the surface of the side wall of the top of the first opening can seal the first opening 213 into a sealed cavity, and the anti-diffusion layer with the sealed cavity can have a good partition effect.
In the process of etching the gate structure 205 and the fin structure 201 on the second region II to form the first opening 213 by using the mask structure as a mask, the etching process also etches the mask structure, the mask layer 208 and a part of the initial barrier layer 207 at the same time.
Referring to fig. 10, an initial transition layer 214 is formed on the surface of the initial barrier layer 207 and the bottom surface and sidewall surface of the first opening 213.
The initial transition layer 214 provides a material layer for a subsequently formed transition layer, and the material of the initial transition layer 214 is different from the material of the subsequently formed diffusion-proof material layer.
The material of the initial transition layer 214 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbo nitride oxide, and silicon oxycarbide. The process of forming the initial transition layer 214 includes a chemical vapor deposition process or an atomic layer deposition process.
In the present embodiment, the material of the initial transition layer 214 includes silicon oxide. The process of forming the initial transition layer 214 includes an atomic layer deposition process that is capable of forming the initial transition layer 214 with a dense structure and a thin thickness.
The material of the initial transition layer 214 is different from that of the anti-diffusion material layer formed subsequently, so that the initial transition layer 214 can be used as a stop layer of the planarization process when the anti-diffusion material layer is planarized subsequently, a flat plane can be obtained after the planarization process, and the plane of the barrier layer and the plane of the dielectric layer can be kept flush when the transition layer and the barrier layer are formed by the initial transition layer and the initial barrier layer after the planarization subsequently.
Next, a diffusion preventing layer is formed in the first opening 213, and the diffusion preventing layer is located on the top of the first opening and closes the first opening into a closed cavity.
In this embodiment, the diffusion barrier layer is also located on the surface of the transition layer. The transition layer can further improve the barrier effect of the diffusion-proof layer; meanwhile, the transition layer can stabilize the stress between the dielectric layer and the diffusion-preventing layer, and the defect of the semiconductor structure caused by unbalanced stress is avoided, so that the performance of the semiconductor structure is influenced.
Referring to fig. 11, a diffusion-preventing material layer 215 is formed in the first opening 213 and on the surface of the initial barrier layer 207.
The diffusion preventing material layer 215 provides a material layer for a subsequent formation of a diffusion preventing layer.
The material of the diffusion-preventing material layer 215 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, and silicon oxycarbide. In the present embodiment, the material of the diffusion preventing material layer 215 includes silicon nitride.
In the present embodiment, the process of forming the diffusion preventing material layer 215 includes a chemical vapor deposition process. The deposition rate of the chemical vapor deposition process is fast, so that the diffusion-proof material layer 215 is preferentially formed on the surface of the top side wall of the first opening 213, and the diffusion-proof material layer seals the first opening 213 to form a closed cavity, so that the closed cavity has a good isolation effect.
With continued reference to fig. 11, a cap layer 216 is formed on the diffusion-preventing material layer 215.
The capping layer 216 is used to increase the surface flatness of the anti-diffusion material layer 218, and when the anti-diffusion material layer 215 is planarized subsequently, the surface flatness of the anti-diffusion material layer 215 is high, so that the stop position of the planarization process can be precisely controlled to stop on the surface of the initial transition layer 214, a plane with good flatness can be obtained, and the dimensional uniformity of a gate plug formed subsequently is facilitated.
The material of the capping layer 216 comprises a dielectric material comprising one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, silicon oxycarbide nitride, and silicon oxycarbide. The process of forming the capping layer 216 includes a chemical vapor deposition process or an atomic layer deposition process.
In the present embodiment, the material of the capping layer 216 includes silicon nitride; the process of forming the capping layer 216 includes a chemical vapor deposition process.
In other embodiments, the cover layer can be not formed.
Referring to fig. 12, the anti-diffusion material layer 215 and the capping layer 216 are planarized until the surface of the initial transition layer 214 is exposed, and an initial anti-diffusion layer 217 is formed on top of the first opening 213.
In the present embodiment, the process of planarizing the diffusion preventing material layer 215 and the capping layer 216 includes a chemical mechanical polishing process.
Referring to fig. 13, the initial anti-transition layer 214 and the initial barrier layer 207 are planarized until the surface of the dielectric layer 202 is exposed, a transition layer 220 is formed on the inner wall surface of the first opening 213, an anti-diffusion layer 218 is formed on the surface of the transition layer 220, the anti-diffusion layer 218 is located on the top of the first opening 213 and seals the first opening 213 into a sealed cavity, and a barrier layer 219 is formed on the top surface of the gate structure 205.
The surface of the sidewall of the first opening 213 has a transition layer 220, and the transition layer 220 can further improve the barrier effect of the diffusion barrier 218; meanwhile, the transition layer 220 can stabilize the stress between the dielectric layer 220 and the diffusion barrier 218, and avoid the condition that the performance of the semiconductor structure is affected due to the defect of the semiconductor structure caused by unbalanced stress.
The process of planarizing the initial anti-transition layer 214 and the initial barrier layer 207 includes: hydra etching process or Gas cluster Ion Beam Processing (GCIB for short).
The etching rate of the Hydra etching process to the silicon oxide material and the silicon nitride material is basically equal, so that after the initial transition layer 214 on the initial barrier layer 207 is removed, the etching rate of the Hydra etching process to the initial barrier layer 207 and the dielectric layer 202 is basically equal, the thicknesses of the barrier layers 219 formed in the dense region and the sparse region a are uniform, the barrier layers 219 are subsequently removed, when a gate plug electrically connected with the gate structure 205 is formed, the contact between the gate plug and the gate structure 205 is good, and the performance uniformity of the device structures in the dense region and the sparse region a is good.
The etching rate of the gas cluster ion beam processing technology to the silicon oxide material and the silicon nitride material is basically equal, so that after the initial transition layer 214 on the initial barrier layer 207 is removed, the etching rate of the gas cluster ion beam processing technology to the initial barrier layer 207 and the dielectric layer 202 is basically equal, the thicknesses of the barrier layers 219 formed in the dense region and the sparse region a are uniform, further, when the barrier layers 219 are subsequently removed to form a gate plug electrically connected with the gate structure 205, the contact between the gate plug and the gate structure 205 is good, and the uniformity of the device structure performance of the dense region and the sparse region a is good.
The etching gas of the Hydra etching process comprises the following steps: c4F8And CH3And F, mixed gas.
The etching gas of the gas cluster ion beam treatment process comprises: a mixed gas of argon and fluorocarbon gas.
To this end, the diffusion preventing layer 218 is formed, the diffusion preventing layer 218 is located on the surface of the transition layer 220, and the diffusion preventing layer 218 is located on the top of the first opening 213 and closes the first opening 213 into a closed cavity. The closed cavity can play a good role in blocking ions in the fin structure 201 and the dielectric layer 202, so that the electrical properties of the device structures on the two sides of the diffusion-proof layer 218 can not interfere with each other, and the electrical property stability of the formed semiconductor structure is improved; meanwhile, the diffusion barrier 218 having a closed cavity has a smaller dielectric constant, thereby reducing the parasitic capacitance of the semiconductor structure and improving the performance of the semiconductor structure.
In this embodiment, the barrier layer 219 can be formed simultaneously with the diffusion barrier layer 218, so as to simplify the process flow and improve the working efficiency.
Referring to fig. 14, after forming the anti-diffusion layer 218, the blocking layer 219 is removed, and a gate plug 221 is formed on top of the gate structure 205.
The material of the gate plug 221 includes a metal including one or a combination of copper, tungsten, aluminum, and titanium nitride.
Due to the fact that the materials of the barrier layer 219 and the dielectric layer 202 are different, when the barrier layer 219 is removed, the damage of the process for removing the barrier layer 219 to the dielectric layer 202 is small, and when the gate plug 221 is formed at the top of the gate structure 205, the gate plug 221 can be formed at the top of the gate structure 205 in a self-aligned manner, so that the position accuracy of the gate plug 221 is good, and the electrical connection effect with the gate structure 205 is good.
Since the etching rate of the initial barrier layer 207 and the dielectric layer 202 is substantially equal by the Hydra etching process or the gas cluster ion beam treatment process, the thickness of the barrier layer 219 formed in the dense region and the sparse region a is uniform, so that the barrier layer 219 is removed, when the gate plug 221 electrically connected with the gate structure 205 is formed, the contact between the gate plug 221 and the gate structure 205 is good, and the uniformity of the device structure performance of the dense region and the sparse region a is good.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to fig. 13, including:
the substrate comprises a dense area, the dense area comprises a plurality of first areas I and second areas II, and the second areas II are positioned between the adjacent first areas I;
a plurality of gate structures 205 located on the first region I of the substrate;
a dielectric layer 202 located on the substrate, wherein the gate structure 205 is located in the dielectric layer 202;
a first opening (not labeled) located on the second region II of the substrate, the first opening extending from the dielectric layer 202 to the substrate;
a transition layer 220 on the bottom surface and sidewall surface of the first opening;
an anti-diffusion layer 218 located on top of and enclosing the first opening into a closed cavity.
In the present embodiment, the substrate includes a base 200 and a fin structure 201 on the base 200; the gate structure 205 spans the fin structure 201; the bottom plane of the first opening is lower than or flush with the bottom plane of the fin structure 201.
In this embodiment, the diffusion barrier 218 is also located on the surface of the transition layer 220.
In this embodiment, the substrate further comprises a sparse region a.
In this embodiment, the device distribution density of the sparse region a is less than that of the dense region.
In this embodiment, the aspect ratio range of the first opening is: 4 to 10.
In this embodiment, the method further includes: a barrier layer 219 located on the top surface of the first region iggate structure 205.
In this embodiment, the material of the barrier layer 219 is different from that of the dielectric layer.
In this embodiment, the material of the barrier layer 219 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, and silicon oxycarbide.
In this embodiment, the material of the diffusion barrier layer 218 is different from the material of the dielectric layer 202; the material of the diffusion barrier layer 218 is different from the material of the transition layer 220.
In this embodiment, the material of the diffusion barrier layer 218 is different from the material of the dielectric layer; the material of the diffusion preventing layer is different from that of the transition layer.
In the present embodiment, the material of the transition layer 220 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, and combinations thereof.
The diffusion barrier 218 is positioned on top of the first opening and closes the first opening into a closed chamber. The closed cavity can play a good role in blocking ions in the fin structure 201 and the dielectric layer 202, so that the electrical properties of the device structures on the two sides of the diffusion-proof layer 218 can not interfere with each other; meanwhile, the diffusion barrier 218 having a closed cavity has a smaller dielectric constant, thereby reducing the parasitic capacitance of the semiconductor structure and improving the performance of the semiconductor structure.
Further, the diffusion-proof layer 218 is also positioned on the surface of the transition layer 220, and the transition layer 220 can further improve the blocking effect of the diffusion-proof layer 218; meanwhile, the transition layer 220 can stabilize the stress between the dielectric layer 202 and the diffusion barrier 218, and avoid the situation that the performance of the semiconductor structure is affected due to the defect of the semiconductor structure caused by unbalanced stress.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (38)

1. A semiconductor structure, comprising:
the substrate comprises a dense area, the dense area comprises a plurality of first areas and second areas, and the second areas are positioned between the adjacent first areas;
a plurality of gate structures located on the first region of the substrate;
the grid structure is positioned in the dielectric layer;
a first opening located on a second region of the substrate, the first opening extending from the dielectric layer to the substrate;
a transition layer located on the bottom surface and the sidewall surface of the first opening;
and the diffusion-proof layer is positioned on the top of the first opening and seals the first opening into a closed cavity.
2. The semiconductor structure of claim 1, wherein the substrate comprises a base and a fin structure on the base; the gate structure crosses the fin structure; a bottom plane of the first opening is lower than or flush with a bottom plane of the fin structure.
3. The semiconductor structure of claim 1, wherein the anti-diffusion layer is further located at a surface of the transition layer.
4. The semiconductor structure of claim 1, wherein the substrate further comprises a sparse region.
5. The semiconductor structure of claim 4, in which a device distribution density of the sparse region is less than a device distribution density of the dense region.
6. The semiconductor structure of claim 1, wherein an aspect ratio range of the first opening is: 4 to 10.
7. The semiconductor structure of claim 1, further comprising: and the barrier layer is positioned on the top surface of the first region gate structure.
8. The semiconductor structure of claim 7, wherein a material of the barrier layer is different from a material of the dielectric layer.
9. The semiconductor structure of claim 8, wherein the material of the barrier layer comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbo-nitride, and silicon oxycarbide.
10. The semiconductor structure of claim 1, wherein a material of the diffusion preventing layer is different from a material of the dielectric layer; the material of the diffusion preventing layer is different from that of the transition layer.
11. The semiconductor structure of claim 10, wherein the material of the diffusion barrier layer comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and silicon oxycarbide.
12. The semiconductor structure of claim 10, wherein the material of the transition layer comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbo nitride oxide, and silicon oxycarbide.
13. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a dense area, the dense area comprises a plurality of first areas and second areas, and the second areas are positioned between the adjacent first areas;
forming a plurality of initial gate structures on the first region and the second region;
forming a dielectric layer on the substrate, wherein the initial grid structure is positioned in the dielectric layer, and the dielectric layer is exposed out of the surface of the initial grid structure;
removing the initial grid structure on the second area, and forming a first opening on the second area of the substrate, wherein the first opening extends from the dielectric layer to the substrate;
forming a transition layer on the bottom surface and the side wall surface of the first opening;
and after the transition layer is formed, forming an anti-diffusion layer which is positioned at the top of the first opening and seals the first opening into a closed cavity.
14. The method of claim 13, wherein the substrate comprises a base and a fin structure on the base; the initial gate structure spans the fin structure; a bottom plane of the first opening is lower than or flush with a bottom plane of the fin structure.
15. The method of forming a semiconductor structure of claim 13, wherein the anti-diffusion layer is further located on a surface of the transition layer.
16. The method of forming a semiconductor structure of claim 13, wherein the substrate further comprises a sparse region; the device distribution density of the sparse region is less than that of the dense region.
17. The method of forming a semiconductor structure of claim 13, wherein the initial gate structure comprises a gate dielectric layer and a gate layer overlying the gate dielectric layer; the dielectric constant of the material of the gate dielectric layer is less than or equal to 3.9, and the material of the gate dielectric layer comprises silicon oxide; the material of the gate layer comprises polysilicon.
18. The method of forming a semiconductor structure of claim 13, wherein the initial gate structure comprises a gate dielectric layer and a gate layer overlying the gate dielectric layer; the dielectric constant of the material of the gate dielectric layer is greater than 3.9, and the material of the gate dielectric layer comprises hafnium oxide or aluminum oxide; the material of the gate layer comprises a metal comprising tungsten.
19. The method of forming a semiconductor structure of claim 18, wherein the method of forming the initial gate structure comprises: forming a dummy gate structure on a substrate; forming a dielectric layer on a substrate, wherein the dummy gate structure is positioned in the dielectric layer; removing the pseudo gate structure, and forming a gate opening in the dielectric layer; and forming the initial gate structure in the gate opening.
20. The method of forming a semiconductor structure of claim 19, wherein the method of forming the dielectric layer comprises: forming a dielectric material layer on a substrate; and flattening the dielectric material layer until the top surface of the pseudo gate structure is exposed to form the dielectric layer, wherein the surface of the dielectric layer is provided with a first groove.
21. The method of forming a semiconductor structure of claim 13, wherein the method of forming the first opening comprises: forming a mask structure on the surface of the substrate, wherein the mask structure exposes the surface of the initial grid structure on the second region; and etching the initial grid structure and the substrate by taking the mask structure as a mask, and forming a first opening on the second region of the substrate.
22. The method of forming a semiconductor structure of claim 21, further comprising, prior to forming the mask structure: etching back the initial grid structure, forming a grid structure on the first area and the second area, and forming a second opening in the dielectric layer at the top of the grid structure; forming an initial barrier layer in the second opening and on the surface of the dielectric layer, wherein a second groove is formed on the surface of the initial barrier layer on the dielectric layer; the mask structure exposes the surface of the initial barrier layer on the second region.
23. The method of forming a semiconductor structure of claim 22, further comprising, prior to forming a masking structure on the surface of the initial barrier layer: forming a sacrificial layer on the surface of the initial barrier layer; the sacrificial layer is located in the second groove, and the mask structure is located on the surfaces of the sacrificial layer and the initial barrier layer.
24. The method of forming a semiconductor structure of claim 23, wherein the method of forming the sacrificial layer comprises: forming a sacrificial material layer on the surface of the initial barrier layer; and flattening the sacrificial material layer until the surface of the initial barrier layer is exposed, and forming a sacrificial layer in the second groove.
25. The method of forming a semiconductor structure of claim 23, wherein a material of the sacrificial layer is different from a material of the initial barrier layer.
26. The method of forming a semiconductor structure of claim 22, wherein a material of the initial barrier layer is different from a material of the dielectric layer.
27. The method of forming a semiconductor structure of claim 26, wherein the material of the initial barrier layer comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbo nitride, and silicon oxycarbide.
28. The method of forming a semiconductor structure of claim 22, wherein a material of the initial barrier layer is different from a material of the transition layer.
29. The method of forming a semiconductor structure of claim 28, wherein the material of the transition layer comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbo nitride, and silicon oxycarbide.
30. The method of forming a semiconductor structure of claim 21, wherein the mask structure comprises a hard mask structure; a liner layer on the hard mask structure; and the photoresist layer is positioned on the liner layer and exposes the surface of the liner layer on the second area.
31. The method of forming a semiconductor structure of claim 30, wherein the hard mask structure comprises a first hard mask layer and a second hard mask layer on the first hard mask layer.
32. The method of forming a semiconductor structure according to claim 22, wherein the method of forming the diffusion barrier layer comprises: forming a diffusion-proof material layer in the first opening and on the surface of the initial barrier layer; flattening the anti-diffusion material layer to form an initial anti-diffusion layer in the first opening; and flattening the initial barrier material layer and the initial anti-diffusion layer until the surface of the dielectric layer is exposed, forming a barrier layer on the top of the gate structure, and forming an anti-diffusion layer in the first opening.
33. The method of claim 32, wherein the step of forming the layer of diffusion barrier material comprises a chemical vapor deposition process.
34. The method of forming a semiconductor structure of claim 32, wherein prior to planarizing the layer of diffusion-resistant material, further comprising: and forming a covering layer on the diffusion-proof material layer.
35. The method of claim 32, wherein the process of planarizing the initial barrier material layer and the initial anti-diffusion layer comprises a Hydra etch process or a gas cluster ion beam process.
36. The method of forming a semiconductor structure of claim 13, wherein an aspect ratio of the first opening ranges from: 4 to 10.
37. The method of claim 13, wherein the material of the diffusion barrier layer comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbo nitride, and silicon oxycarbide in combination.
38. The method of forming a semiconductor structure of claim 22, wherein after forming an anti-diffusion layer, removing said initial barrier layer and forming a gate plug on top of said gate structure.
CN202010252058.0A 2020-04-01 2020-04-01 Semiconductor structure and method for forming semiconductor structure Pending CN113497143A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102969239A (en) * 2011-09-01 2013-03-13 中国科学院微电子研究所 Process and special device for improving isolating oxide chemical mechanical planarization (CMP) uniformity
CN104253082A (en) * 2013-06-26 2014-12-31 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US20160225762A1 (en) * 2015-01-30 2016-08-04 Globalfoundries Inc. Single diffusion break with improved isolation and process window and reduced cost
CN109659274A (en) * 2017-10-10 2019-04-19 格芯公司 Form the method and generated structure of conductive contact structure to semiconductor device
CN109873035A (en) * 2017-12-04 2019-06-11 联华电子股份有限公司 Semiconductor element and preparation method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102969239A (en) * 2011-09-01 2013-03-13 中国科学院微电子研究所 Process and special device for improving isolating oxide chemical mechanical planarization (CMP) uniformity
CN104253082A (en) * 2013-06-26 2014-12-31 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US20160225762A1 (en) * 2015-01-30 2016-08-04 Globalfoundries Inc. Single diffusion break with improved isolation and process window and reduced cost
CN109659274A (en) * 2017-10-10 2019-04-19 格芯公司 Form the method and generated structure of conductive contact structure to semiconductor device
CN109873035A (en) * 2017-12-04 2019-06-11 联华电子股份有限公司 Semiconductor element and preparation method thereof

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