CN105140174A - TSV side wall flattening method - Google Patents
TSV side wall flattening method Download PDFInfo
- Publication number
- CN105140174A CN105140174A CN201510349172.4A CN201510349172A CN105140174A CN 105140174 A CN105140174 A CN 105140174A CN 201510349172 A CN201510349172 A CN 201510349172A CN 105140174 A CN105140174 A CN 105140174A
- Authority
- CN
- China
- Prior art keywords
- hole
- tsv
- silica membrane
- side wall
- flattening method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a TSV (through-silicon-via) side wall flattening method comprising the following steps: providing a semiconductor substrate, and etching the semiconductor substrate to obtain a via hole in the semiconductor substrate; depositing a silicon dioxide thin film on the side wall of the via hole through a CVD process; partially etching the silicon dioxide thin film through a wet etching process; using xenon fluoride gas to etch a projecting part not covered with the silicon dioxide thin film; and finally, removing the remaining silicon dioxide thin film on the side wall of the via hole. By flattening the side wall of a TSV, scalloping is greatly improved, a TSV structure with a smooth side wall can be obtained, the difficulty in subsequent TSV filling, such as uniform and continuous deposition of a dielectric layer, a barrier layer and a seed layer, is reduced, and eventually, the possibility of TSV device failure is reduced.
Description
Technical field
The invention belongs to semiconductor manufacturing and encapsulation technology field, relate to a kind of flattening method of TSV through hole sidewall.
Background technology
Along with the integrated level of integrated circuit improves constantly, the develop rapidly that semiconductor technology also continues.Along with integrated circuit technique enters 32 nanometers even after 22 nanometer technology platforms, the sharply rising of the aspect such as system complexity, equipment investment cost, for this reason, utilize Modern Electronic Packaging Technology to realize highdensity 3D (three-dimensional) integrated, become the system-level integrated important technology approach of microelectronic circuit (comprising MEMS).
In numerous 3D encapsulation technologies, silicon through hole (Through-Silicon-Via, TSV) technology becomes the focus of research now.At present, the process technology of through-silicon via structure mainly comprises laser beam drilling, wet anisotropic etching, reactive ion etching technology and Bosch (ripple is assorted) etching technics etc.Wherein Bosch etching technics has high etch rate, extraordinary pattern controlling, and has high Selection radio to mask, therefore receives the extensive concern of people, becomes the mainstream technology of silicon through hole processing in current 3D encapsulation technology.
The formation method of existing TSV through hole comprises the following steps: provide the Semiconductor substrate being formed with hard mask graph, and described hard mask graph is corresponding with through hole; With described hard mask graph for mask, etch semiconductor substrates forms through hole.
Because Semiconductor substrate all has suitable thickness usually, the technique forming through hole is that plasma etching industrial is generally the assorted lithographic technique of ripple (Boschprocess), the assorted etching of ripple can form the quite high vertical through hole of depth-to-width ratio, but, please refer to Fig. 1, Fig. 1 is the TSV through hole schematic diagram with scallop pattern; Comprise Semiconductor substrate 1 and TSV through hole 2, TSV through hole 2 sidewall formed is rough, rough and uneven in surface, likeness in form wave, be also referred to as scallop pattern (scallopingorroughness), the range difference namely between the most protrusion place of TSV through hole 2 sidewall and most recess can reach 100nm.
Hocket with passivation because Bosch technique etches in the TSV through hole course of processing, therefore scallop pattern is produced at TSV through hole sidewall upper side wall, this side wall construction affects the uniform deposition of subsequent dielectric layers, barrier layer, Seed Layer, and then affects copper plating fill process and device performance.In addition, scallop pattern to cause on TSV through hole sidewall stress, electric field uneven distribution in the course of work, thus affects device reliability, accelerates component failure.
Therefore, those skilled in the art need the flattening method providing a kind of TSV through hole sidewall badly, improve the scallop pattern of TSV through hole sidewall, thus improve electric property and the yield of device.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of flattening method of TSV through hole sidewall, improves the scallop pattern of TSV through hole sidewall, thus improves electric property and the yield of device.
In order to solve the problems of the technologies described above, the invention provides a kind of flattening method of TSV through hole sidewall, comprising the following steps:
Step S01, provide Semiconductor substrate, and described Semiconductor substrate is etched, to obtain through hole in described Semiconductor substrate; Wherein, the sidewall of described through hole has protuberance and depressed part;
Step S02, employing CVD technique are at the sidewall deposition silicon dioxide film of described through hole;
Step S03, employing wet-etching technology carry out partial etching to described silica membrane; Wherein, the protuberance of described through-hole side wall is exposed in liquid, the depressed part reserve part silica membrane of described through-hole side wall;
Step S04, the protuberance not covering silica membrane to be etched;
Step S05, remove remaining silica membrane on described through-hole side wall.
Preferably, in step S04, pass into xenon fluoride gas and etch the protuberance not covering silica membrane, the etch thicknesses of described protuberance is
Preferably, described xenon fluoride gas flow is 5 ~ 15sccm, and gas pressure is 0.5 ~ 1Torr.
Preferably, in step S02, the thickness of described silica membrane is
Preferably, in step S03, the etch rate of described silica membrane is not more than
the etch thicknesses of described silica membrane is
etch period is not less than 5min.
Preferably, in step S03, the etching liquid in described wet-etching technology is DHF, BOE and APM one wherein; Wherein, the H in DHF
2o:HF volume ratio is greater than 200:1, the NH in BOE
4the volume ratio of F:HF is greater than 10:1, NH in APM
4oH:H
2o
2: H
2the volume ratio of O controls between 1:1:20 ~ 1:4:5, and fluid temperature is not higher than 80 degree.
Preferably, in step S05, wet-etching technology is adopted to remove remaining silica membrane on described through-hole side wall.
Preferably, in step S05, the etch rate of described silica membrane is not more than
the etch thicknesses of described silica membrane is greater than
Preferably, the etching liquid in described wet-etching technology is DHF, BOE and APM one wherein; Wherein, the H in DHF
2o:HF volume ratio is greater than 150:1, the NH in BOE
4the volume ratio of F:HF is greater than 8:1, NH in APM
4oH:H
2o
2: H
2the volume ratio of O controls between 1:1:15 ~ 1:4:5, and fluid temperature is not higher than 80 degree.
Preferably, described step S01 comprises:
Step S01a, provide the Semiconductor substrate being formed with hard mask graph, described hard mask graph is corresponding with through hole;
Step S01b, with described hard mask graph for mask, etch semiconductor substrates formed through hole.
Compared with existing scheme, the flattening method of TSV through hole sidewall provided by the invention, by carrying out planarization to the sidewall of TSV through hole, substantially improve scallop pattern, and the TSV structure with smooth side wall can be obtained, reduce the difficulty of filling TSV through hole, the uniformly continous deposition of such as dielectric layer, barrier layer, Seed Layer, finally reduces the possibility of TSV component failure.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the TSV through hole in prior art with scallop pattern;
Fig. 2 is the schematic flow sheet of the flattening method of TSV through hole sidewall of the present invention;
Fig. 3 to Fig. 7 is the cross-sectional view of the flattening method preferred embodiment of TSV through hole sidewall of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.Those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Above-mentioned and other technical characteristic and beneficial effect, by conjunction with the embodiments and the flattening method of accompanying drawing 2 to 7 to TSV through hole sidewall of the present invention be described in detail.Fig. 2 is the schematic flow sheet of the flattening method of TSV through hole sidewall of the present invention; Fig. 3 to Fig. 7 is the cross-sectional view of the flattening method preferred embodiment of TSV through hole sidewall of the present invention.
As shown in Figure 2, the invention provides a kind of flattening method of TSV through hole sidewall, comprise the following steps:
Step S01, provide Semiconductor substrate, and etch Semiconductor substrate, to obtain through hole in Semiconductor substrate, the sidewall 3 of through hole has protuberance and depressed part (as shown in Figure 3).
Concrete, the method forming through hole on a semiconductor substrate comprises: step S01a, provide the Semiconductor substrate being formed with hard mask graph, and hard mask graph is corresponding with through hole; Step S01b, with hard mask graph for mask, etch semiconductor substrates formed through hole.Wherein, mask layer can be photoresist or hard mask, after obtaining through hole on a semiconductor substrate, removes the mask layer in Semiconductor substrate, and can clean Semiconductor substrate.
Wherein, the degree of depth of through hole is less than the thickness of Semiconductor substrate, in the specific implementation, realizes the preparation of required TSV through hole by carrying out the mode such as thinning to Semiconductor substrate.Obtaining through hole is on a semiconductor substrate the technological means that this area is commonly used, and does not repeat them here.
Step S02, employing CVD technique are at sidewall 3 deposition silicon dioxide film 4 (as shown in Figure 4) of through hole.
Concrete, adopt CVD technique at the sidewall deposition silicon dioxide film of through hole, owing to adopting CVD technique, its step coverage is better, can carry out deposit along figure pattern preferably, the scallop consistent appearance of the film namely formed and through-hole side wall, the thickness of silica membrane is preferably
Step S03, employing wet-etching technology etch silica membrane 4.Wherein, the protuberance of the through-hole side wall 3 after etching is exposed in liquid, and namely the protuberance of through-hole side wall 3 does not cover silica membrane, and the depressed part reserve part silica membrane 4 (as shown in Figure 5) of through-hole side wall 3.
Concrete, adopt wet-etching technology to be not more than the etch rate that silica membrane 4 etches
the etch thicknesses of silica membrane 4 is preferably
etch period is not less than 5min.
In the present embodiment, the etching liquid in wet-etching technology is preferably DHF, BOE and APM one wherein; Wherein, the H in DHF
2o:HF volume ratio is greater than 200:1, the NH in BOE
4the volume ratio of F:HF is greater than 10:1, NH in APM
4oH:H
2o
2: H
2the volume ratio of O controls between 1:1:20 ~ 1:4:5, and fluid temperature is not higher than 80 degree.
Step S04, the protuberance not covering silica membrane to be etched (as shown in Figure 6).
Concrete, preferably pass into xenon fluoride gas and etch the protuberance not covering silica membrane, the etch thicknesses of protuberance is
xenon fluoride gas flow is 5 ~ 15sccm, and gas pressure is 0.5 ~ 1Torr.As shown in Figure 6, protuberance planarization gradually after over etching of through-hole side wall, but through-hole side wall still remains silica membrane 4.
Remaining silica membrane 4 (as shown in Figure 7) on step S05, removal through-hole side wall 3.
Concrete, adopt wet-etching technology to remove remaining silica membrane 4 on through-hole side wall 3, the etch rate of residue silica membrane 4 is not more than
the etch thicknesses of residue silica membrane 4 is greater than
In the present embodiment, the etching liquid in wet-etching technology is preferably DHF, BOE and APM one wherein; Wherein, the H in DHF
2o:HF volume ratio is greater than 150:1, the NH in BOE
4the volume ratio of F:HF is greater than 8:1, NH in APM
4oH:H
2o
2: the volume ratio of H2O controls between 1:1:15 ~ 1:4:5, and fluid temperature is not higher than 80 degree.
After the smoothness that the sidewall of through hole reaches required, can sidewall oxide, barrier layer, Seed Layer and metallic conductor be set in through hole, sidewall oxide covers the sidewall of through hole, barrier layer is positioned at Seed Layer and sidewall oxidation interlayer, metallic conductor is filled in through hole, and Seed Layer is wrapped in the outer ring of metallic conductor.Subsequent technique is the common practise of those skilled in the art, does not repeat them here.
In sum, the flattening method of TSV through hole sidewall provided by the invention, by carrying out planarization to the sidewall of TSV through hole, substantially improve scallop pattern, and can obtain that there is smooth side wall structure, reduce the difficulty of filling TSV through hole, the uniformly continous deposition of such as dielectric layer, barrier layer, Seed Layer, finally reduces the possibility of TSV component failure.
Above-mentioned explanation illustrate and describes some preferred embodiments of the present invention, but as previously mentioned, be to be understood that the present invention is not limited to the form disclosed by this paper, should not regard the eliminating to other embodiments as, and can be used for other combinations various, amendment and environment, and can in invention contemplated scope described herein, changed by the technology of above-mentioned instruction or association area or knowledge.And the change that those skilled in the art carry out and change do not depart from the spirit and scope of the present invention, then all should in the protection range of claims of the present invention.
Claims (10)
1. a flattening method for TSV through hole sidewall, is characterized in that, comprises the following steps:
Step S01, provide Semiconductor substrate, and described Semiconductor substrate is etched, to obtain through hole in described Semiconductor substrate; Wherein, the sidewall of described through hole has protuberance and depressed part;
Step S02, employing CVD technique are at the sidewall deposition silicon dioxide film of described through hole;
Step S03, employing wet-etching technology carry out partial etching to described silica membrane; Wherein, the protuberance of described through-hole side wall is made to be exposed in liquid, the depressed part reserve part silica membrane of described through-hole side wall;
Step S04, the protuberance not covering silica membrane to be etched;
Step S05, remove remaining silica membrane on described through-hole side wall.
2. the flattening method of TSV through hole sidewall according to claim 1, is characterized in that, in step S04, pass into xenon fluoride gas and etch the protuberance not covering silica membrane, the etch thicknesses of described protuberance is
3. the flattening method of TSV through hole sidewall according to claim 2, is characterized in that, described xenon fluoride gas flow is 5 ~ 15sccm, and gas pressure is 0.5 ~ 1Torr.
4. the flattening method of TSV through hole sidewall according to claim 1, is characterized in that, in step S02, the thickness of described silica membrane is
5. the flattening method of TSV through hole sidewall according to claim 1, is characterized in that, in step S03, the etch rate of described silica membrane is not more than
the etch thicknesses of described silica membrane is
etch period is not less than 5min.
6. the flattening method of TSV through hole sidewall according to claim 1, is characterized in that, in step S03, the etching liquid in described wet-etching technology is DHF, BOE and APM one wherein; Wherein, the H in DHF
2o:HF volume ratio is greater than 200:1, the NH in BOE
4the volume ratio of F:HF is greater than 10:1, NH in APM
4oH:H
2o
2: H
2the volume ratio of O controls between 1:1:20 ~ 1:4:5, and fluid temperature is not higher than 80 degree.
7. the flattening method of TSV through hole sidewall according to claim 1, is characterized in that, in step S05, adopts wet-etching technology to remove remaining silica membrane on described through-hole side wall.
8. the flattening method of TSV through hole sidewall according to claim 7, is characterized in that, in step S05, the etch rate of described silica membrane is not more than
the etch thicknesses of described silica membrane is greater than
9. the flattening method of TSV through hole sidewall according to claim 7, is characterized in that, the etching liquid in described wet-etching technology is DHF, BOE and APM one wherein; Wherein, the H in DHF
2o:HF volume ratio is greater than 150:1, the NH in BOE
4the volume ratio of F:HF is greater than 8:1, NH in APM
4oH:H
2o
2: H
2the volume ratio of O controls between 1:1:15 ~ 1:4:5, and fluid temperature is not higher than 80 degree.
10. the flattening method of TSV through hole sidewall according to claim 1, is characterized in that, described step S01 specifically comprises:
Step S01a, provide the Semiconductor substrate being formed with hard mask graph, described hard mask graph is corresponding with through hole;
Step S01b, with described hard mask graph for mask, etch semiconductor substrates formed through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510349172.4A CN105140174A (en) | 2015-06-19 | 2015-06-19 | TSV side wall flattening method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510349172.4A CN105140174A (en) | 2015-06-19 | 2015-06-19 | TSV side wall flattening method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105140174A true CN105140174A (en) | 2015-12-09 |
Family
ID=54725472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510349172.4A Pending CN105140174A (en) | 2015-06-19 | 2015-06-19 | TSV side wall flattening method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105140174A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023284121A1 (en) * | 2021-07-12 | 2023-01-19 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| WO2023000656A1 (en) * | 2021-07-19 | 2023-01-26 | 长鑫存储技术有限公司 | Method for fabricating semiconductor structure and semiconductor structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030211752A1 (en) * | 2002-05-01 | 2003-11-13 | Michael Rattner | Method of smoothing a trench sidewall after a deep trench silicon etch process |
| CN1553495A (en) * | 2003-06-06 | 2004-12-08 | 南亚科技股份有限公司 | Plug forming method |
| US20120199984A1 (en) * | 2010-09-15 | 2012-08-09 | Elpida Memory, Inc. | Semiconductor device, method for manufacturing the same, and data processing device |
-
2015
- 2015-06-19 CN CN201510349172.4A patent/CN105140174A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030211752A1 (en) * | 2002-05-01 | 2003-11-13 | Michael Rattner | Method of smoothing a trench sidewall after a deep trench silicon etch process |
| CN1553495A (en) * | 2003-06-06 | 2004-12-08 | 南亚科技股份有限公司 | Plug forming method |
| US20120199984A1 (en) * | 2010-09-15 | 2012-08-09 | Elpida Memory, Inc. | Semiconductor device, method for manufacturing the same, and data processing device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023284121A1 (en) * | 2021-07-12 | 2023-01-19 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| WO2023000656A1 (en) * | 2021-07-19 | 2023-01-26 | 长鑫存储技术有限公司 | Method for fabricating semiconductor structure and semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100768363B1 (en) | Production method for semiconductor integrated circuit device and semiconductor integrated circuit device | |
| US7807583B2 (en) | High aspect ratio via etch | |
| US9099400B2 (en) | Semiconductor device manufacturing methods | |
| US9607883B2 (en) | Trench formation using rounded hard mask | |
| CN103390581A (en) | Through-silicon-via etching method | |
| US9330964B2 (en) | Semiconductor structures and fabrication methods for improving undercut between porous film and hardmask film | |
| CN111689460B (en) | Manufacturing method of TSV ground interconnection hole structure under silicon cavity in microsystem module | |
| US8530327B2 (en) | Nitride shallow trench isolation (STI) structures and methods for forming the same | |
| CN104617035A (en) | Forming method of semiconductor device | |
| CN111968953A (en) | Through silicon via structure and preparation method thereof | |
| CN102412193A (en) | Through silicon via (TSV) filling method | |
| CN103871956A (en) | Silicon deep via etching method | |
| KR20150067748A (en) | Bi-layer hard mask for robust metalization profile | |
| CN105140174A (en) | TSV side wall flattening method | |
| CN107706145B (en) | Isolation trench film filling structure, semiconductor memory device and preparation method | |
| US11450562B2 (en) | Method of bottom-up metallization in a recessed feature | |
| CN106548977B (en) | Manufacturing method of air gap structure | |
| TWI462224B (en) | Integrated circuits and methods for processing integrated circuits with embedded features | |
| EP2819162B1 (en) | Method for producing contact areas on a semiconductor substrate | |
| CN103681235A (en) | Solution method for effectively filling deep trench | |
| CN109427650B (en) | Semiconductor structure and forming method thereof | |
| CN102956543B (en) | Manufacturing method for through silicon via | |
| WO2009090520A1 (en) | High aspect ratio holes or trenches | |
| CN101562147A (en) | Method for removing residual defects | |
| CN109326558B (en) | Groove filling structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151209 |
|
| RJ01 | Rejection of invention patent application after publication |