WO2009090520A1

WO2009090520A1 - High aspect ratio holes or trenches

Info

Publication number: WO2009090520A1
Application number: PCT/IB2008/055579
Authority: WO
Inventors: François NEUILLY; Philippe Meunier-Beillard
Original assignee: Nxp B.V.
Priority date: 2008-01-16
Filing date: 2008-12-30
Publication date: 2009-07-23
Also published as: EP2232533A1

Abstract

The present invention relates to a method to increase throughput when manufacturing high Aspect Ratio (AR) holes or trenches, and high AR holes or trenches obtained by said method. In semiconductor devices holes or trenches are etched, using dry or wet etching techniques, typically dry etching is preferred. According to the present invention, the initial aspect ratio of the trenches is increased by depostion of the layer of the same material as the substate on the walls and the bottom of the trenches. In order to get high- integrated devices use of a third dimension, e.g. of a silicon wafer is necessary to follow the ITRS roadmap. Therein, for instance a deep silicon etch is required and further high aspect structures are designed. Many products with high aspect holes are in production or development like deep trench capacities, Trench MOSFET, DRAM capacities, through wafer via interconnects, etc.

Description

HIGH ASPECT RATIO HOLES OR TRENCHES

FIELD OF THE INVENTION

The present invention relates to a method to increase throughput when manufacturing high Aspect Ratio (AR) holes or trenches, and high AR holes or trenches obtained by said method.

BACKGROUND OF THE INVENTION

In semiconductor devices holes or trenches are etched, using dry or wet etching techniques, typically dry etching is preferred.

In order to get high- integrated devices use of a third dimension, e.g. of a silicon wafer, is necessary to follow the ITRS roadmap. Therein, for instance a deep silicon etch is required and further high aspect structures are designed. Many products with high aspect holes are in production or development like deep trench capacities, Trench MOSFET, DRAM capacities, through wafer via interconnects, etc.

With deeper and higher aspect-ratio structures, such devices have improved characteristics. The deep silicon etch process steps become therefore more and more important.

The race for high aspect ratio holes (or trenches) has an impact in terms of cost. It is noted that deep silicon etch is becoming a major cost contributor in the process price. Throughput of those processes can be drastically decreased with the downsizing of structures to etch. This is due to the fact that the etch rate is aspect ratio dependent. The higher the aspect ratio is, the slower the etch rate is. Fig. 1 is an example of etch rate as function of hole diameter, clearly indicating that holes with smaller diameters, i.e. higher aspect ratios, take relatively much longer to be formed. Thus, as a disadvantage, process time and costs increase. Furthermore, as the etching tool is a typically a single wafer tool, a longer process time will dramatically decrease the throughput and increase the process time of a complete batch (25 wafers), and thus add to costs considerably.

Various documents describe formation of holes or trenches with relatively high aspect ratios. Document US2005/0266655 Al (Dl) discloses deposition of a thin layer of silicon within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the amorphous silicon from outside of the trench, oxide is selectively deposited over the amorphous silicon to fill the trench from the bottom up without voids, thereby creating a shallow trench isolation (STI) structure. Deposition of the amorphous silicon or other silicon containing layers allows the selective oxide deposition step to be integrated with a thermally grown oxide trench liner. It is noted that in the above disclosure the use of a Si liner implicitly reduces the aspect ratio of the hole, but not to the extent of the present invention. Further, no reference is made to the composition of the liner, apart from being amorphous silicon. Thus, the document does not appear to disclose the material of the present substrate used.

Document US2004/0180510 Al (D2) discloses methods of producing trench structures having substantially void- free filler materials therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.

Document US2005/0153507 Al (D3) discloses a fabrication method for a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact. After forming and sinking an electrically conductive filling, an insulation collar and, if appropriate, a buried contact that is connected on all sides, the following are effected: providing at least one liner layer in the trench; filling the trench with a filling made of an auxiliary material, which filling is encapsulated by the at least one liner layer in the trench; providing a mask on the filling for defining the structure of the buried contact, the mask having no projections into the trench; removing a part of the filling using the mask; removing an underlying part of the at least one liner layer for uncovering a corresponding part of the insulation collar.

Thus, D2 and D3 seem to disclose the use of silicon liners, which is of the same material as the substrate, but not of the same crystal or poly-crystalline structure. Further, these liners only temporarily reduces the aspect ratio, as they are removed during further processing. As seems standard practice in such cases, the liner is removed during the process of forming holes, and therefore the silicon liner does not directly reduce the final aspect ratio. In fact, it remains largely the same, as the liner does not or at the most to a small extend appear in the final trench. Document US2006/0264054 Al (D4) discloses a method for etching a trench in a semiconductor substrate. More specifically, the present invention relates to a method for etching deep trenches such as those having aspect ratios of 30 and higher. According to embodiments of the invention, a method for etching a trench in a semiconductor substrate includes a first etch cycle wherein the trench is etched to a first depth. Thereafter, a protective liner is deposited on at least the upper part of the trench's sidewalls. The protective liner includes inorganic material. During at least one second etch cycle, the trench is etched to its final depth.

It seems that D4 discloses the use of a Si liner, which would implicitly reduce the final aspect ratio. However, the substrate is made from another material, which serves as a protective layer, such as SiGe. It is not made of the same material as the substrate, such as Si.

It is noted that many documents may be found which use Si nitride/oxide liners which would implicitly reduce the aspect ratio of the holes in which they are formed. However, the liners are not of identical composition to the substrate although they might be Si based or be based on the same material as being used for the substrates. It is noted that the use of liner to reduce the aspect ratio, must, however, be of a different material than that of the substrate to get a selective etch of silicon and not the spacer.

Etching of wafers as well as certain techniques of deposition of layers, such as techniques as CVD, epitaxy, etc. are very costly, because in certain cases only one wafer can be produced at the same time. So reduction of process time would benefit the costs of processing. Typically the person skilled in the art would not consider adding process steps to an existing process, as the total process time and costs would increase, which is in general considered as a disadvantage. The objective of the present invention is to remove disadvantages of the prior art, especially those relating to costs and process time. On the other hand, existing advantages, such as high aspect ratios of holes, should be maintained.

SUMMARY OF THE INVENTION The overall idea of the present invention is to increase the aspect ratio in general, by applying a layer in a hole. This is especially economically interesting for a high aspect ratio.

The aspect ratio of a two-dimensional shape is the ratio of its longer dimension to its shorter dimension. It also applies to two characteristic dimensions of a three- dimensional shape, especially for the longest and shortest 'axes' or for symmetrical objects (e.g. rods or holes) that are described by just two measures (e.g. length and diameter or width). In such cases, the aspect ratio may evaluate to a value less than one (e.g. consider very short and very long rods). As etch rate is size dependent, instead of etching a very small hole or trench that would require a very long processing, a larger hole or trench is etched, which is then filled with material to get the same aspect ratio, but with a shorter process time. This is due to an etch process time that is smaller because of the higher size structure and deposition techniques that are less expensive in terms of time and cost because of batch processing. The extra process costs are much lower than the large costs induced by a very long dry etch process.

DETAILED DESCRIPTION OF THE INVENTION

In a first aspect the present invention relates to a method of forming one or more holes in a substrate, comprising the steps of: providing a substrate having a composition, forming a mask, etching one or more holes in the substrate, which one or more holes have an initial aspect ratio, a depth and a width, which depth and width may vary from hole to hole, and applying a layer, which layer has the same composition as the substrate, preferably having the same crystal structure as the substrate, thereby forming holes which have a final aspect ratio, which final aspect ratio is smaller than the initial aspect ratio, which layer is substantially not removed. The present invention is equally well applicable to the formation of trenches, or squares, or donut shaped forms, or oblong structures, or combinations thereof. Thus within the present invention the term "hole" also means a trench, or any other structure having an aspect ratio. The present method increases the aspect ratio of said structure.

The substrate can be any substrate, such as silicon, silicon oxide, silicon- germanium, etc, but preferably is silicon.

In order to form holes a standard lithographic step is used, wherein a resist is used to protect part of the substrate that is not intended to be etched, and to have another part of the substrate available wherein one or more holes are etched.

Thereafter an etch step is applied to actually form one or more holes. In a preferred embodiment the etch step is a dry etch step, such as BOSH or RIE, preferably by RIE. The RIE process is used to obtain an anisotropic etch. A continuous Si etching process is composed only of an etching process. Therefore etching chemistry is often based on e.g. SF₆ZHBr or SF₆ZO₂. In such an etch step it is more difficult to obtain a very high aspect ratio via, as sidewall passivation control is considered more difficult.

Another process known to obtain a very high aspect ratio via is the so-called BOSCH process. This BOSCH process is in fact a RIE etch, with cycles of etching and passivation. As the energy of the ion used is mostly perpendicular to the substrate, the sidewall passivation is not removed, and as a consequence the BOSCH process is improving the anisotropy. The BOSCH Si etching process comprises the steps of:

Si Etch Pulse: Si is etched isotropically by F radicals generated in a plasma of a fluorinated gas such as SF₆.

Passivation Pulse: A layer of passivation polymer is deposited by dissociating a fluorocarbon precursor gas such as C₄Fs in a plasma. - Depassivation Pulse: The passivation polymer at the bottom of the etched features is preferentially removed mainly by ion bombardment.

The cycle of Etch-Passivation-Depassivation is repeated till the desired etch depth is obtained.

Typically, other parameters for Si etching process are, for the Bosh process and a continuous process:

Pressures are typically in the order of tens of mTorr;

RF power (for plasma density): Thoussands of Watts;

RF bias (for ion energy): hundreds of Watts;

Temperature: from cryogenic to room temperature; and - Gas flow: several seem (standard cubic centimer per minute).

Other techniques other than dry etch may be used as well, such as wet etch using KOH, or TMAH. However, a wet etch process is an isotropic etching process. Further there are contamination issues. Therefore, in general dry etch is preferred.

Thereby one or more holes are formed, which have a certain depth and a certain width, and thus an initial aspect ratio. It is also envisaged that depth and width may vary from hole to hole, thus at this stage the substrate may comprise various holes, which holes may each have a specific aspect ratio, width, and depth, respectively, varying from hole to hole, in a controlled and objected manner. Thereafter a layer is applied. Said layer has the same composition as the substrate.

In a preferred embodiment the layer has the same crystal structure as the substrate, e.g. in case of silicon the layer is an epitaxial grown layer. As the layer is applied, specifically the width of the holes is reduced. It is noted that also the depth is reduced, but this effect is relatively small. Further, the layer is typically also applied on the substrate. As a consequence especially the width of the one or more holes is reduced, by approximately two times the thickness of the layer applied. Thus, the aspect ratio is increased. However, as can for instance be seen in Fig. 3, the hole is only partly filled, i.e. is still open. If the initial width was Wl, and the depth was d, and the thickness of the applied layer is h, the final width is W2 = Wl - 2h, the initial aspect ratio was d/Wl, and the final aspect ratio is approximately d/(Wl-2h) or d/W2. As W2 < Wl, the final aspect ratio is larger than the initial aspect ratio.

The layer applied does not function as a protective layer or barrier, for instance for an underlying layer or structure.

Further, as it is the aim of the present invention to increase the aspect ratio of holes by the present method, the layer applied is substantially not removed, i.e. it remains largely as it was after being applied. Of course further processing steps could have some influence on the layer thickness or integrity of the layer, due to process conditions and chemicals used in such steps, but this influence is very small and furthermore, it does not differ significantly from further process steps used in the prior art, as these further process steps largely have the same or similar objective, such as filling of contacts, vias or trenches.

In table one some experimental results are given, clearly illustrating the advantageous effect of the present invention. In a preferred embodiment the holes have an initial aspect ratio, which is a high aspect ratio, preferably larger than 4:1, more preferably larger than 8:1, even more preferably larger than 12:1, most preferably larger than 16:1, such as 20:1. As can be seen from the experiments below, and can be deducted from Fig. 1, the total process time for the present method, comprising etch and epitaxy, with respect to the prior art, for a specific or given aspect ratio, reduces most for high aspect ratios. Thus, the present invention is most favorable for holes with high aspect ratios.

In a preferred embodiment the initial aspect ratio is at least 1.3 times smaller than the final aspect ratio, preferably at least 1.5 times smaller, even more preferably at least 1.7 times smaller, even more preferably at least 2.0 times smaller, most preferably at least 3.0 times smaller, such as 4.0 times smaller. As with respect to high aspect ratios, the effect of the present method is most favorable when the diameter of the holes is reduced most, i.e. wherein the final aspect ratio is much larger than the initial aspect ratio.

In a preferred embodiment the substrate is silicon or an oxide, such as silicon oxide. The holes formed may be holes for capacities, through wafer vias, trenches, such as STI, contacts and vias filled with a conductor for connecting metal layers, and holes or structures that require a high aspect ratio in general.

In a preferred embodiment the layer is applied by epitaxy, LPCVD, MOCVD, plasma enhanced CVD, MBE (Molecular Beam Epitaxy), preferably epitaxy or LPCVD, most preferably epitaxy. In general, the layer should have a thickness such that the thickness h thereof is large enough, compared to the width of the hole, in order to obtain a final width W2 = Wl-2h after deposition, which is different from the initial width Wl. Preferably the layer has a thickness of more than 0.05 times the width of the initial hole, more preferably at a thickness of more than 0.1 times the width of the initial hole, even more preferably at a thickness of more than 0.2 times the width of the initial hole, such as more than 0.25 times the width of the initial hole. Clearly a thicker layer reduces the aspect ratio the most.

The substrate material, as well as that of the layer applied, could be a silicon like substrate, but could be also be germanium, which has very similar characteristics as silicon. Also glass substrates could be used, such as dielectric materials, such as SiO₂.

The material applied for the layer would in that case be SiO₂, which could be applied by deposition of SiO₂ PECVD, or TEOS LPCVD.

In a preferred embodiment the hole is for a deep trench capacity, a trench MOSFET, a DRAM capacity, a through wafer via interconnect, a via, a connect, or combinations thereof. It is noted that with a higher aspect ratio, the time for filling a hole is also shorter. This is for instance important for a subsequent metal filling, which filling typically is a single wafer process. In the latter case it is then easier to close the hole and avoid any problems for a remaining process to be performed, such as a spin coating deposition. Again, this phenomena is important for metal filling of holes, as metal thickness deposition is, most of the time, limited, for instance, to a few microns in case of a PVD process, to tens of microns for an electroplating process and an electroless process. For example, a via of 25 μm diameter can be filled by copper electroplating, wherein copper is just an example for a metal, with a high throughput and a better uniformity than filling a via of 50 μm diameter by copper electroplating, so it that sense it is easier. In a second aspect the present invention relates to one or more holes in a substrate, which holes have an initial aspect ratio relating to the one or more holes before applying a further layer as described above, further comprising a layer, which layer has the same composition as the substrate, thereby forming holes which have a final aspect ratio, which final aspect ratio is smaller than the initial aspect ratio.

In a third aspect the present invention relates to a semiconductor device, made by a method according to the invention.

In a fourth aspect the present invention relates to an IC comprising holes according to the invention. The present invention is further elucidated by the following Figures and examples, which are not intended to limit the scope of the invention. The person skilled in the art will understand that various embodiments may be combined.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows an etch rate of a standard process as function of hole diameter.

Fig. 2 shows a prior art hole formation.

Fig. 3 shows a hole formation according to the present invention. Fig. 4 shows a SEM photograph of hole according to the invention with EPI growth. Fig. 5 shows a SEM photograph of hole according to the invention with EPI growth.

DETAILED DESCRIPTION OF THE DRAWINGS

Fig. 1 shows an etch rate of a standard process as function of hole diameter. For a standard process, such as a RIE or BOSH process, the etch rate, expressed as μm /min, is given as a function of the hole diameter, expressed in μm. The Figure shows that for a small hole diameter the etch rate is also relatively small. Going from left to right, as the hole diameter increases, also the etch rate increases. It is noted that specifically for small hole diameters the etch rate is relatively small, which etch rate does not increase relatively that much at higher hole diameters. In other words, for relatively large diameter, a hole surface could be considered to be infinite, but for a small hole diameter, volatile species experience difficulties to get out of hole because of for instance collisions, and as a consequence the etchrate drops. This phenomenom is known as Aspect ratio Dependent Etch (ARDE). Fig. 2 shows a prior art hole formation. The hole is formed by applying a lithographic mask and etching a hole in a substrate.

Fig. 3 shows a hole formation according to the present invention. First a hole is etched, in a similar way as in Fig. 2. However, the hole diameter is much larger than in the case of Fig. 2. As a consequence the initial aspect ratio is much smaller. Than, the hole is partly filled by applying a layer. As the layer is applied, specifically the width of the holes is reduced. It is noted that also the depth is reduced, but this effect is relatively small. Further, the layer is typically also applied on the substrate. As a consequence especially the width of the one or more holes is reduced, by approximately two times the thickness of the layer applied. Thus, the aspect ratio is increased. If the initial width was Wl, and the depth was d, and the thickness of the applied layer is h, the final width is W2 = Wl - 2h, the initial aspect ratio was d/Wl, and the final aspect ratio is approximately d/(Wl-2h) or d/W2. As W2 < Wl, the final aspect ratio is larger than the initial aspect ratio.

When depositing layers batch tools may be used, in order to reduce process time and costs even further, such as LPCVD tools.

The study has been made with EPI tool, but LPCVD poly deposition could be also an alternative for narrowing a via diameter.

The invention specifically relates to deep silicon holes filled with silicon deposition, where batch processing for those deposition techniques exists. However, it is envisaged that the present could be extented to any high aspect ratio etch process. For example, contact holes for CMOS processing are done in oxide. A less constraint etch could than be done, whereafter the contact is then filled with a material. It is noted that an issue is the temperature budget. In back end processing, because of the metal layers, it is not possible to process to high temperature. However, if precautions are taken with respect to this concern, it is possible to extent the present invention to those materials.

Fig. 4 shows a SEM photograph of hole according to the invention which has been partly filled by applying EPI growth.

Fig. 5 shows a SEM photograph of another hole according to the invention with EPI growth, but the resulting layer is poly-crystalline or with a high defect density.

Table 1. Aspect ratio after etch or after etch and EPI.

The present invention reduces an initial diameter, being 50 μm in the example, to a final diameter of 25 μm (not given in the table). From the above table, it is shown that the 10:1 aspect ratio hole is obtained by combining dry etch and epitaxy in only 88% of the time of a comparable single dry etch process of the prior art. For the 14:1 aspect ratio hole only 83% of the time is needed. For larger aspect ratios the reduction is even more significant. Thus, for holes with relatively large aspect ratios, a reduction in process time of more than 10% is achieved, often more than 15%, and in many cases a reduction of more than 20% process time is achieved.

Claims

CLAIMS:

1. Method of forming one or more holes in a substrate, comprising the steps of: providing a substrate having a composition, forming a mask, etching one or more holes in the substrate, which one or more holes have an initial aspect ratio, a depth and a width, and applying a layer, which layer has the same composition as the substrate, thereby forming holes which have a final aspect ratio, which final aspect ratio is smaller than the initial aspect ratio, which layer is substantially not removed.

2. Method according to claim 1, wherein the etch step is a dry etch step, such as

BOSCH or RIE, preferably RIE.

3. Method according to claim 1 or 2, wherein the initial aspect ratio is a high aspect ratio, such as larger than 4:1, preferably larger than 6:1, such as larger than 8:1.

4. Method according to any of claims 1-3, wherein the initial aspect ratio is at least 1.3 times smaller than the final aspect ratio, preferably at least 1.5 times smaller, even more preferably at least 1.7 times smaller, even more preferably at least 2.0 times smaller, most preferably at least 3.0 times smaller.

5. Method according to any of claims 1-4, wherein the substrate is silicon or an oxide, such as silicon oxide.

6. Method according to any of claims 1-5, wherein the layer is applied by epitaxy, LPCVD, MOCVD, plasma enhanced CVD, MBE (Molecular Beam Epitaxy), preferably epitaxy or LPCVD, most preferably epitaxy, and preferably at a thickness of more than 0.05 times the width of the initial hole, more preferably at a thickness of more than 0.1 times the width of the initial hole, even more preferably at a thickness of more than 0.2 times the width of the initial hole, such as more than 0.25 times the width of the initial hole.

7. Method according to any of claims 1-6, wherein the hole is for a deep trench capacity, a trench MOSFET, a DRAM capacity, a through wafer via interconnect, a via, a connect, or combinations thereof.

8. One or more holes in a substrate, which holes have an initial aspect ratio relating to the hole without a layer, further comprising a layer, which layer has the same composition as the substrate, thereby forming holes which have a final aspect ratio, which final aspect ratio is smaller than the initial aspect ratio.

9. Hole obtainable by a method according to any of claims 1-7.

10. Semiconductor device, made by a method according to any of claims 1-7.

11. IC comprising holes according to claim 8 or 9.