CN103871956A - Silicon deep via etching method - Google Patents
Silicon deep via etching method Download PDFInfo
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- CN103871956A CN103871956A CN201210528536.1A CN201210528536A CN103871956A CN 103871956 A CN103871956 A CN 103871956A CN 201210528536 A CN201210528536 A CN 201210528536A CN 103871956 A CN103871956 A CN 103871956A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 88
- 239000010703 silicon Substances 0.000 title claims abstract description 88
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 86
- 238000005530 etching Methods 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 229910004014 SiF4 Inorganic materials 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 50
- 239000007789 gas Substances 0.000 description 13
- 229920000642 polymer Polymers 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 4
- 239000006227 byproduct Substances 0.000 description 3
- 125000004430 oxygen atom Chemical group O* 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002045 lasting effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003595 mist Substances 0.000 description 2
- 239000013047 polymeric layer Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 229920002313 fluoropolymer Polymers 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a silicon deep via etching method carried out in a plasma etching chamber. The method comprises the following steps: (a) a silicon substrate is provided, a first gas is supplied to the chamber, and a graphical photoresist layer is deposited on the silicon substrate, with an opening being formed; (b) an oxide layer is deposited on the bottom and a side wall of the opening and the photoresist layer; and (c) a second gas is supplied to the chamber and etches the silicon substrate to a predetermined depth, with the oxide layer and the photoresist layer as masks. The method can improve a side wall graphic of a silicon via and defects of a side wall recess.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of deep hole silicon etching method.
Background technology
In technical field of manufacturing semiconductors, in MEMS(Micro-Electro-Mechanical Systems, MEMS (micro electro mechanical system)) and the field such as 3D encapsulation technology, conventionally need to carry out deep via etching to materials such as silicon.For example, in body silicon etching technology, the degree of depth of dark silicon through hole (Through-Silicon-Via, TSV) reaches hundreds of micron, its depth-to-width ratio even much larger than 10, conventionally adopts deep reaction ion etching method to carry out etching body silicon and forms.
In prior art, the common Bosch technique of the deep reaction ion etching of TSV is carried out.As shown in Figure 1, wherein, substrate silicon is layer to be etched, does mask layer to form figure on it, and mask layer is generally SiO2 or Si3N4, mainly plays mask effect in etching process.Concrete deep reaction ion etching method comprises the following steps: (1) etch step, conventionally carry out plasma etching with the mist of Ar, SF6, (2) polymer deposition step, conventionally form fluorocarbon polymer layer with the mist of Ar and C4F8 at hole medial surface, its thickness is generally at nanoscale, sometimes be passivation layer also referred to as this polymeric layer, (3) etch step and polymer deposition step hocket, until dark silicon via etch completes, in etch step, due to the inner surface of hole, especially at hole medial surface deposited polymer, the polymer of the plasma bombardment bottom of vertical incidence, make the etching of vertical direction continue to carry out downwards, and so the reservation etching rate due to polymer of sidewall is very low, thereby ensure the anisotropy of whole hole etching process.
But prior art is carried out etching as only done mask with polymeric layer to silicon substrate, need to carry out in addition a sidewall protection processing procedure.Or prior art is protected the sidewall of deep hole silicon by reaction by-product, byproduct quality is softer, and owing to being processing procedure byproduct, its thinner thickness, is not enough to protective side wall.
Fig. 1 is the schematic diagram of the deep hole silicon etching of prior art.The photoresist layer 102 of deposition pattern on silicon substrate 100, then continues etch silicon substrate 100, to form opening 103 taking described photoresist layer as mask.But as shown in Figure 1, the deep hole silicon etching mechanism of prior art can form a darker depression (bowing) at the sidewall in hole, this depression is in processing procedure, not wish to occur.
In order to solve the above-mentioned defect of prior art, the present invention is proposed.
Summary of the invention
For the problems referred to above in background technology, the present invention proposes a kind of deep hole silicon etching method carrying out in plasma etch chamber chamber.
The invention provides a kind of deep hole silicon etching method carrying out in plasma etch chamber chamber, wherein, comprise the steps:
Step (a), provides a silicon substrate, and supply the first gas is to described chamber, and on described silicon substrate the photoresist layer of deposition pattern, form opening;
Step (b), deposited oxide layer on the bottom of described opening and sidewall and photoresist layer;
Step (c), supply the second gas is to described chamber, taking described oxide layer and described photoresist layer as silicon substrate described in mask continues etching is to desired depth.
Further, described the first gas comprises SiF4 and O2, or SiH4 and O2.
Further, described the second gas comprises CF4.
Further, the span of described step (b) time of implementation is 15s to 1min, and the span of the time of implementation of described step (c) is 1min to 10min.
Further, described step (b) and step (c) hocket.
Further, the span of described step (b) time of implementation is 10s to 30s, and the span of the time of implementation of described step (c) is 30s to 2min.
The span of the thickness of the oxide layer depositing on described sidewall further, is 90nm to 110nm.
Further, the span of the thickness of the oxide layer on described photoresist sidewall is 90nm to 110nm.
Further, described oxide layer comprises SiO2.
Further, the span of described chamber pressure is 100mt to 300mt.
Further, described desired depth is relevant with critical size bar.
Further, the span of described desired depth is 10micro to 300micro.
Deep hole silicon etching method provided by the invention, owing to adopting oxide layer to do mask, its quality is harder, and sidewall can adequately protect.And, because oxide layer is on the photoresist being first deposited on as mask, then etched away a part by rear etching, wherein can produce oxide layer particulate, in etching process, adhere to bottom and the sidewall of deep hole silicon opening, protect with oppose side wall.And the present invention can also improve the side walls collapse problem of silicon through hole.
Brief description of the drawings
Fig. 1 is the schematic diagram of the deep hole silicon etching of prior art;
Fig. 2 (a) ~ Fig. 2 (d) is the processing step flow chart of the deep hole silicon etching of a specific embodiment according to the present invention;
Fig. 3 (a) ~ Fig. 3 (e) is the processing step flow chart of the deep hole silicon etching of another specific embodiment according to the present invention;
Fig. 4 (a) ~ Fig. 4 (b) is the generalized section of the silicon through hole of prior art;
Fig. 5 is the generalized section of silicon through hole of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described.
The invention provides a kind of deep hole silicon etching method carrying out in plasma etch chamber chamber.Typically, above-mentioned deep hole silicon etching carries out processing procedure in plasma process chamber.
Particularly, first perform step S11, one silicon substrate 200 is provided, in described plasma process chamber, supply the first gas, and deposit photoresist 202 on described silicon substrate 200, and described photoresist 202 is carried out to a mask layer described photoresist 202 is carried out to etching, to obtain the patterned photoresist layer 202 as shown in Fig. 2 (a), to form opening.Wherein, described the first gas is used for etching photoresist 202 and forms opening 203.
Then perform step S21, as shown in Fig. 1 (b), deposited oxide layer 204 on the bottom of described opening 203 and sidewall and photoresist layer 202 respectively;
It should be noted that; the thickness of described oxide layer 204 is determined according to process requirements; it is relevant with factors such as the degree of depth of deep hole silicon, chamber pressure, radio-frequency power, etching speeds, and its thickness at least should be able to can not weather by its sidewall of sustainable protection after the deep hole silicon etching of desired depth completes.
Step S31, supply the second gas is to described chamber, taking described oxide layer 204 and described photoresist layer 202 for silicon substrate 200 described in mask continuation etching is to desired depth.
Alternatively, the present invention can deposit the silica 204 of q.s once on photoresist 202, also can repeatedly carry out the step S21 of cvd silicon oxide 204 and the step S31 of etch silicon substrate 200 many times, with the silica 204 that continues to reach required.
In lasting etching process, silicon substrate 200 reaches the desired depth as shown in Fig. 2 (d) gradually, simultaneously, oxide layer 204 is received the bombardment attenuation gradually of plasma, the oxygen atom that wherein unnecessary oxide layer produces drops in opening 203, adhere on the sidewall of opening 203 and react with silicon substrate 200 gradually, having generated silica.Silicon oxide film fits tightly the sidewall of opening 203, has served as the protective layer of the sidewall of opening 203.
It should be noted that, although in the etching process of deep hole silicon, due to the continuous etching to silicon substrate, the silicon oxide film layer generating also will inevitably be etched, but owing to having deposited the oxide layer of adequate thickness on photoresist 202, be accompanied by the etching of oxide layer, constantly have oxygen atom to drop in opening 203, continue to react with silicon substrate 200, therefore constantly form silicon oxide film.
Deep hole silicon etching method provided by the invention, does not need additionally to provide sidewall protection step, has therefore saved process time and cost.In addition, the silica protective layer that continues to form on deep hole sidewall silicon due to the present invention is not polymer, and it has certain thickness, is difficult for being corroded fast in oxidizing process.Even if it,, along with processing procedure carries out etchedly, also can supplement in good time, therefore can more effectively protect deep hole sidewall silicon figure, and can not produce the defects such as projection depression.
Fig. 3 (a) ~ Fig. 3 (e) is the processing step flow chart of the deep hole silicon etching of another specific embodiment according to the present invention, in the present embodiment, the present invention also retains certain thickness oxide layer at patterned photoresist sidewall, using the barrier layer as deep hole silicon etching, to solve the problem of deep hole sidewall silicon depression (bowing).
Particularly, first perform step S12, one silicon substrate 300 is provided, in described plasma process chamber, supply the first gas, and deposit photoresist 302 on described silicon substrate 300, and described photoresist 302 is carried out to a mask layer described photoresist 302 is carried out to etching, to obtain the patterned photoresist layer 302 as shown in Fig. 3 (a), to form opening.Wherein, described the first gas is used for etching photoresist 302 and forms opening 303.
Then perform step S22, as shown in Fig. 1 (b), deposited oxide layer 304 on the bottom of described opening 303 and sidewall and photoresist layer 302 respectively;
It should be noted that; the thickness of described oxide layer 304 is determined according to process requirements; it is relevant with factors such as the degree of depth of deep hole silicon, chamber pressure, radio-frequency power, etching speeds, and its thickness at least should be able to can not weather by its sidewall of sustainable protection after the deep hole silicon etching of desired depth completes.
Step S32, supply the second gas is to described chamber, taking described oxide layer 304 and described photoresist layer 302 for silicon substrate 200 described in mask continuation etching is to desired depth.
Alternatively, the present invention can deposit the silica 304 of q.s once on photoresist 302, also can repeatedly carry out the step S22 of cvd silicon oxide 304 and the step S32 of etch silicon substrate 200 many times, with the silica 304 that continues to reach required.
In lasting etching process, silicon substrate 300 reaches desired depth gradually, simultaneously, oxide layer 304 is received the bombardment attenuation gradually of plasma, the oxygen atom that wherein unnecessary oxide layer produces drops in opening 303, adhere on the sidewall of opening 303 and react with silicon substrate 200 gradually, having generated silica.Silicon oxide film fits tightly the sidewall of opening 303, has served as the protective layer of the sidewall of opening 203.
In addition, different from a upper embodiment, the present embodiment is larger at the thickness of the oxide layer 304 of photoresist 302 sidewall sections depositions.Thus, the oxide layer 304 adhering on photoresist 302 sidewall sections can be as the barrier layer of deep hole silicon etching, thus, as shown in Fig. 3 (c), excite the plasma of generation initial in etching by the second gas, also eat away the oxide layer 304 that is positioned at photoresist 302 sidewalls of close together.Therefore,, because this oxide layer 304 consumes the plasma that part should initially be born by deep hole sidewall silicon, therefore the sinking degree of deep hole sidewall silicon can improve.
Referring to accompanying drawing 3 (d) and 3 (e), along with the carrying out of processing procedure, the oxide layer 304 that is positioned at photoresist 302 sidewalls is more and more thinner, and the degree of depth of opening 303 is increasing.Finally, as shown in accompanying drawing 3 (e), opening 303 arrives desired depth, although the deep hole sidewall silicon of acquisition also has depression to a certain degree, compared to the existing larger improvement of prior art.
Further, described the first gas comprises SiF4 and O2, or SiH4 and O2.
Further, described the second gas comprises CF4.
Further, the span of described step (b) time of implementation is 15s to 1min, and the span of the time of implementation of described step (c) is 1min to 10min.
Further, described step (b) and step (c) hocket.Wherein, the span of described step (b) time of implementation is 10s to 30s, and the span of the time of implementation of described step (c) is 30s to 2min.
The span of the thickness of the oxide layer depositing on described sidewall further, is 90nm to 110nm.
Further, the span of the thickness of the oxide layer on described photoresist sidewall is 90nm to 110nm.
Further, described oxide layer comprises SiO2.
Further, the span of described chamber pressure is 100mt to 300mt.
Further, described desired depth is relevant with critical size bar.
Further, the span of described desired depth is 10micro to 300micro.
Fig. 4 (a) is according to the generalized section of the silicon through hole of the deep hole silicon etching mechanism acquisition of prior art; Fig. 4 (b) is that the employing polymer of prior art is as the generalized section of the silicon through hole of the side wall protective layer acquisition of deep hole silicon etching; as shown in Figure 4; wherein; the sidewall figure of above-mentioned silicon through hole is even not; present up big and down small shape, especially occurred great depression at through-silicon via sidewall initial part, this is the situation that processing procedure need to be avoided.Fig. 5 shows the generalized section of the silicon through hole obtaining according to deep hole silicon etching mechanism of the present invention, and the sidewall surfaces of this silicon through hole is uniform and smooth, does not occur significantly depression.This has illustrated superiority of the present invention.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.Read after foregoing those skilled in the art, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (12)
1. the deep hole silicon etching method carrying out in plasma etch chamber chamber, wherein, comprises the steps:
Step (a), provides a silicon substrate, and supply the first gas is to described chamber, and on described silicon substrate the photoresist layer of deposition pattern, form opening;
Step (b), deposited oxide layer on the bottom of described opening and sidewall and photoresist layer;
Step (c), supply the second gas is to described chamber, taking described oxide layer and described photoresist layer as silicon substrate described in mask continues etching is to desired depth.
2. deep hole silicon etching method according to claim 1, is characterized in that, described the first gas comprises SiF4 and O2, or SiH4 and O2.
3. deep hole silicon etching method according to claim 1, is characterized in that, described the second gas comprises CF4.
4. deep hole silicon etching method according to claim 1, is characterized in that, the span of described step (b) time of implementation is 15s to 1min, and the span of the time of implementation of described step (c) is 1min to 10min.
5. deep hole silicon etching method according to claim 1, is characterized in that, described step (b) and step (c) hocket.
6. deep hole silicon etching method according to claim 5, is characterized in that, the span of described step (b) time of implementation is 10s to 30s, and the span of the time of implementation of described step (c) is 30s to 2min.
7. deep hole silicon etching method according to claim 1, is characterized in that, the span of the thickness of the oxide layer depositing on described sidewall is 90nm to 110nm.
8. deep hole silicon etching method according to claim 1, is characterized in that, the span of the thickness of the oxide layer on described photoresist sidewall is 90nm to 110nm.
9. according to the deep hole silicon etching method described in claim 7 or 8, it is characterized in that, described oxide layer comprises SiO2.
10. according to the deep hole silicon etching method described in claim 7 or 8, it is characterized in that, the span of described chamber pressure is 100mt to 300mt.
11. deep hole silicon etching methods according to claim 1, is characterized in that, described desired depth is relevant with critical size bar.
12. deep hole silicon etching methods according to claim 11, is characterized in that, the span of described desired depth is 10micro to 300micro.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210528536.1A CN103871956A (en) | 2012-12-10 | 2012-12-10 | Silicon deep via etching method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210528536.1A CN103871956A (en) | 2012-12-10 | 2012-12-10 | Silicon deep via etching method |
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| CN103871956A true CN103871956A (en) | 2014-06-18 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105845650A (en) * | 2015-01-12 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole structure and manufacturing method therefor |
| CN109119401A (en) * | 2018-08-28 | 2019-01-01 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and preparation method thereof |
| CN112738704A (en) * | 2021-04-01 | 2021-04-30 | 中芯集成电路制造(绍兴)有限公司 | Manufacturing method of MEMS microphone |
| CN113933935A (en) * | 2021-11-03 | 2022-01-14 | 山东师范大学 | Method for preparing KTP nonlinear runway type micro-ring resonator |
| CN115116843A (en) * | 2022-07-29 | 2022-09-27 | 捷捷微电(南通)科技有限公司 | Deep silicon etching method |
| WO2023000656A1 (en) * | 2021-07-19 | 2023-01-26 | 长鑫存储技术有限公司 | Method for fabricating semiconductor structure and semiconductor structure |
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| US20060189144A1 (en) * | 2005-02-22 | 2006-08-24 | Krawczyk John W | Multiple layer etch stop and etching method |
| TW200806567A (en) * | 2006-07-26 | 2008-02-01 | Touch Micro System Tech | Method of deep etching |
| CN101292197A (en) * | 2005-08-18 | 2008-10-22 | 朗姆研究公司 | Etch features with reduced line edge roughness |
| WO2011063552A1 (en) * | 2009-11-27 | 2011-06-03 | C Sun Mfg, Ltd. | Method for forming via interconnects for 3-d wafer/chip stacking |
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| US6380095B1 (en) * | 1998-06-22 | 2002-04-30 | Applied Materials, Inc. | Silicon trench etch using silicon-containing precursors to reduce or avoid mask erosion |
| US20060189144A1 (en) * | 2005-02-22 | 2006-08-24 | Krawczyk John W | Multiple layer etch stop and etching method |
| CN101292197A (en) * | 2005-08-18 | 2008-10-22 | 朗姆研究公司 | Etch features with reduced line edge roughness |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105845650A (en) * | 2015-01-12 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole structure and manufacturing method therefor |
| CN105845650B (en) * | 2015-01-12 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of through-silicon via structure and preparation method thereof |
| CN109119401A (en) * | 2018-08-28 | 2019-01-01 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and preparation method thereof |
| CN112738704A (en) * | 2021-04-01 | 2021-04-30 | 中芯集成电路制造(绍兴)有限公司 | Manufacturing method of MEMS microphone |
| WO2023000656A1 (en) * | 2021-07-19 | 2023-01-26 | 长鑫存储技术有限公司 | Method for fabricating semiconductor structure and semiconductor structure |
| CN113933935A (en) * | 2021-11-03 | 2022-01-14 | 山东师范大学 | Method for preparing KTP nonlinear runway type micro-ring resonator |
| US11681099B2 (en) | 2021-11-03 | 2023-06-20 | Shandong Normal University | Method to build monolithic ring-shape frequency converter on potassium titanyl phosphate water |
| CN115116843A (en) * | 2022-07-29 | 2022-09-27 | 捷捷微电(南通)科技有限公司 | Deep silicon etching method |
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