CN102130045B - Processing method of through holes - Google Patents
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- CN102130045B CN102130045B CN201010619478.4A CN201010619478A CN102130045B CN 102130045 B CN102130045 B CN 102130045B CN 201010619478 A CN201010619478 A CN 201010619478A CN 102130045 B CN102130045 B CN 102130045B
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Abstract
Processing method of through holes according to the present invention comprises step: provide mask; Etched substrate is carried out to form through hole according to mask; Be partially filled described through hole, to form the insulating oxide that guarantor's type covers on the sidewall of described through hole; And remove described mask.The present invention can eliminate the scallop pattern of the through-silicon via sidewall that the assorted etching technics of ripple produces to the impact of subsequent technique, and the insulating oxide layer film of surface smoothing is formed at the sidewall of silicon through hole, improve guarantor's type spreadability of insulating oxide layer film, reduce the difficulty of follow-up silicon filling through hole, finally reduce the possibility of component failure.
Description
Technical field
The present invention relates to semiconductor manufacturing and encapsulation field, a kind of processing method of through holes particularly in semiconductor fabrication, especially silicon processing method of through holes.
Background technology
Along with the integrated level of integrated circuit improves constantly, the develop rapidly that semiconductor technology also continues.The Road Development that current semiconductor technology evolves walks miniaturization along Moore's Law has arrived 22nm, has started close to its physics limit.Now, introduce other relevant new technologies and could promote further developing of integrated circuit.Wherein, silicon through hole (ThroughSiliconVia, TSV) technology is a rare fast development now, and can have influence on consumption and the technical field of industrial electronics widely, its 3-DIC brought is integrated is constantly promoting the integrated development with encapsulation technology of multi-chip.
TSV is by making vertical conducting between chip and chip, between wafer and wafer, realize the state-of-the-art technology interconnected between chip, it achieve short, the abundantest Z-direction interconnection, chip-stacked integrated by difference in functionality, more function, better performance, lower power consumption and cost can be realized simultaneously, strive for larger manufacture flexibility and shorter time to market (TTM), therefore generally had an optimistic view of by industry, and think the following mainstream technology dominating whole microelectronic industry.Internationally famous market survey advisory machinery Yoledeveloppement expects 3D-TSV wafer throughput in 2015 will reach millions of, occupy the storage market share of 25%.
The most key in TSV technology is exactly etching, i.e. the formation of TSV through hole.Because semi-conductor silicon chip substrate all has suitable thickness usually, the technique of described formation through hole is plasma etching industrial, the technology that current industry is commonly used is the assorted etching technics of ripple (Boschprocess), and the assorted etching of ripple can form the quite high vertical through hole of depth-to-width ratio.
But owing to alternately using two steps containing different plasma to etch in technical process, the through-hole side wall therefore formed is rough, rough and uneven in surface, and likeness in form wave, is also referred to as scallop pattern (scallopingorroughness).This will make the technique of the follow-up insulating barrier in through-hole side wall formation quite difficult.In addition, also difficulty can be brought to guarantor's type covering of follow-up formation copper barrier layer and copper seed layer.This just easily affects the property of interconnections of whole TSV, thus makes whole component failure.
Therefore, it is desirable to propose a kind of silicon processing method of through holes of scallop pattern on the impact of subsequent technique eliminating TSV through hole sidewall.
Summary of the invention
One object of the present invention is just to provide a kind of can passing through and forms the good insulating oxide (film) of guarantor's type spreadability, eliminate the scallop pattern of TSV through hole (silicon through hole) sidewall to the method for the impact of subsequent technique.
Processing method of through holes according to the present invention comprises step: provide mask; Etched substrate is carried out to form through hole according to mask; Be partially filled described through hole, to form the insulating oxide that guarantor's type covers on the sidewall of described through hole; And remove described mask.
Thus, the present invention can eliminate the scallop pattern of the through-silicon via sidewall that the assorted etching technics of ripple produces to the impact of subsequent technique, and the insulating oxide layer film of surface smoothing is formed at the sidewall of silicon through hole, improve guarantor's type spreadability of insulating oxide layer film, reduce the difficulty of follow-up silicon filling through hole, finally reduce the possibility of component failure.
Preferably, in above-mentioned processing method of through holes, be partially filled described through hole and make the centre of described through hole leave gap; And the described through hole after being partially filled is revised.
Preferably, in above-mentioned processing method of through holes, described substrate is silicon substrate, and described through hole is silicon through hole.
Preferably, in above-mentioned processing method of through holes, the step being partially filled described through hole comprises: by high-aspect-ratio technique grown oxide layer.
Preferably, in above-mentioned processing method of through holes, described through hole after being partially filled is revised and comprises with the step forming the insulating oxide that guarantor's type covers on the sidewall of described through hole: use SiCoNi to etch the oxide be partially fill in described through hole, to form the insulating oxide that guarantor's type covers on the sidewall of described through hole.
Preferably, in above-mentioned processing method of through holes, describedly carry out etched substrate according to mask and realized by the assorted etching technics of ripple with the step forming through hole.
Preferably, in above-mentioned processing method of through holes, in high-aspect-ratio technique, at O
3the time of/TEOS is grow oxide under the condition of 100s-3000s.
Preferably, in above-mentioned processing method of through holes, in high-aspect-ratio technique, after grow oxide, silicon chip is placed in 900 DEG C to 1200 DEG C, annealing 20 minutes to 1 hour under the environment of steam.
Preferably, in above-mentioned processing method of through holes, described in be partially filled described through hole step do not close described through hole.
Preferably, in above-mentioned processing method of through holes, described mask is hard mask, and described hard mask comprises the stacked structure of silicon nitride, anti-reflecting layer and photoresist layer.
Preferably, in above-mentioned processing method of through holes, the step of the described mask of described removal comprises employing wet processing and removes described mask.
Compared with prior art, technical scheme of the present invention also has the following advantages: the present invention need not experience long high temperature oxidation process, simplifies processing step simultaneously; Sidewall creates scallop pattern, directly can form the good insulating oxide of guarantor's type spreadability on scallop pattern, reduce the difficulty of filling TSV through hole, finally reduce the possibility of TSV component failure.
In addition, current HARP and SiCoNi technique is mainly used in shallow-trench isolation (ShallowTrenchIsolation, STI), wherein HARP standard technology adopts three step depositions, deposition rate from fast to slow, then carries out double annealing, and wherein first step steam annealing temperature is very low, general between 600-800 DEG C, be oxidized to SiO to avoid the Si on sidewall
2, and second step is annealed into N
2annealing, temperature is 900-1100 DEG C, to make the SiO of growth
2film is finer and close, repairs issuable gap.Adopt the HARP fill process of low rate in the present invention always, enhance the repair ability of HARP to TSV sidewall scallop pattern, adopt a step steam high annealing afterwards, just in time make the sidewall of TSV through hole scallop pattern and the silicon of bottom be oxidized to very thin one deck SiO
2, ensure that sidewall SiO
2layer continuous, strengthen the SiO that HARP grows
2layer and the combination of the rear scallop profile sidewalls of etching, make the SiO grown simultaneously
2film becomes finer and close.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 be according to the TSV through hole processing method of the embodiment of the present invention mask is provided after schematic diagram.
Fig. 2 be according to the TSV through hole processing method of the embodiment of the present invention be partially filled through hole after schematic diagram.
Fig. 3 is according to the schematic diagram after the revising the through hole after being partially filled of the TSV through hole processing method of the embodiment of the present invention.
Fig. 4 be according to the described mask of removal of the TSV through hole processing method of the embodiment of the present invention after schematic diagram.
Fig. 5 is the flow chart of the TSV through hole processing method according to the embodiment of the present invention.
It should be noted that, accompanying drawing is not drawn in proportion, and accompanying drawing is for illustration of the present invention, and unrestricted the present invention.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
In a preferred embodiment of the invention, providing a kind of scallop pattern eliminating TSV through hole sidewall to the impact of subsequent technique forms the method for the good insulating oxide layer film of guarantor's type spreadability, comprise: provide the Semiconductor substrate being formed with hard mask graph, described hard mask graph is corresponding with through hole; With described hard mask graph for mask, the assorted etching of ripple (Boschetch) is adopted to form through hole to described Semiconductor substrate etching; High-aspect-ratio technique (HighAspectRatioProcess, HARP) is used to be partially filled described silicon through hole; A step high annealing annealing process is used to heat-treat silicon chip; Use SiCoNi to revise the silicon through hole pattern after being partially filled, thus make the silicon through hole of formation have the good insulating oxide layer film of guarantor's type spreadability; Remove described hard mask graph.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in detail.
Fig. 1 to Fig. 4 is the schematic diagram of the TSV through hole processing method according to the embodiment of the present invention.Fig. 5 is the flow chart of the TSV through hole processing method according to the embodiment of the present invention.
As shown in Figure 5, in the step S1 of Fig. 5, provide hard mask 2 first on a silicon substrate.
Specifically, Fig. 1 be according to the TSV through hole processing method of the embodiment of the present invention mask is provided after schematic diagram.More particularly, Fig. 1 is the schematic diagram of the silicon substrate at TSV structure place, wherein preparation TSV through hole before, may one or more layers other films of deposit (as Si
3n
4deng).With reference to figure 1, provide the Semiconductor substrate being formed with hard mask 2, described hard mask graph is corresponding with through hole.It should be noted that, hard mask 2 can be that one or more layers other films are (as Si
3n
4deng).
Concrete, described substrate is silicon-based substrate, such as: N-shaped silicon substrate or p-type silicon substrate.
Described hard mask 2 can be single layer structure or multilayer lamination structure, does exemplary illustrated in the present embodiment with the single layer structure of silicon nitride.In other embodiments, described hard mask 2 can also be the stacked structure of silicon nitride, anti-reflecting layer and photoresist layer, can realize better etching effect thus.
The forming step of described hard mask 2 comprises: adopt chemical vapor deposition method to form hard mask layer (not shown) in Semiconductor substrate 1, spin coating proceeding is adopted to form photoresist layer (not shown) on hard mask layer surface, exposure imaging is carried out to described photoresist layer, form the photoetching offset plate figure corresponding with through hole, with described photoetching offset plate figure for mask, etch described hard mask layer until form hard mask 2, remove photoresist layer.
As shown in Figure 1, with described hard mask 2 for mask, etch semiconductor substrates 1 forms through hole.
In the present embodiment; described etching technics is the assorted etching technics of ripple; it should be noted that; due to the assorted etching technics of described ripple be Semiconductor substrate 1 form through hole while to form the protective layer of polymer at the sidewall of through hole; thus form the quite high vertical through hole of depth-to-width ratio; specifically; when etched portions Semiconductor substrate; polymer is formed at the through-hole side wall of the part formed; and then down etch, and then etched portions semiconductor, form polymer at the through-hole side wall of the part formed; down etch again, until form through hole.Therefore, the assorted etching technics of described ripple is adopted can to form scallop pattern by through-hole side wall after etching.
In the present embodiment, the via depth that etching is formed is 10-500um, and the diameter of through hole is 1-50um.
Refer again to Fig. 5, as shown in Figure 5, in the step S2 of Fig. 5, described silicon through hole is partially filled.Be partially filled and fill together with sidewall in bottom, the object carrying out being partially filled is exactly to repair scallop pattern; Therefore in a preferred embodiment, the technique that directly can form the covering of guarantor's type and surperficial smooth oxide layer is preferably adopted.If have employed the technique that directly can form the covering of guarantor's type and surperficial smooth oxide layer, etch step so described later can be omitted.
But, because the technique that directly can form the covering of guarantor's type and surperficial smooth oxide layer is comparatively complicated and expensive, so have employed other technique in certain embodiments, in this case, " be partially filled " and mainly refer to that through hole is not done and fill up, gap is left, to be that follow-up SiCoNi etches ready such as.Therefore, in this case, then need to carry out follow-up etching work.
Specifically, Fig. 2 be according to the TSV through hole processing method of the embodiment of the present invention be partially filled through hole after schematic diagram.Be by high-aspect-ratio technique (HARP), described silicon through hole is partially filled with further reference to Fig. 2, Fig. 2, thus repair the SiO of the scallop pattern of through-silicon via sidewall
2the schematic diagram of thin layer.As shown in Figure 2, high-aspect-ratio technique is used to be partially filled described silicon through hole.High-aspect-ratio process deposits oxide (such as SiO
2) keep low rate, i.e. O
3/ TEOS is higher, and the time is 100s-3000s, and now high-aspect-ratio technique is comparatively strong to the scallop pattern repair ability of TSV through hole sidewall, and high-aspect-ratio technique can not fill whole TSV through hole to airtight.
Then carry out a step high annealing Technology for Heating Processing, silicon chip is placed in 900 DEG C to 1200 DEG C, steam (H
2o) anneal 20 minutes to 1 hour under environment.
Preferably, control the silicon through hole that high-aspect-ratio technique makes not close on substrate, thus be conducive to speed and the accuracy of the execution of subsequent technique.
Refer again to Fig. 5, as shown in Figure 5, in the step S3 of Fig. 5, use SiCoNi to the through-silicon via sidewall SiO after being partially filled
2thin layer is revised.
In the present embodiment, SiCoNi is utilized to carry out etching oxide by chemical reaction, so the oxide in the present embodiment can be such as SiO
2, because SiO
2chemical reaction can be carried out with SiCoNi; Therefore, if other oxide owing to being etched by chemical reaction with SiCoNi, can adopt SiO certainly
2outside other oxide.SiCoNi is a kind of new etch chamber, is mainly used to etch SiO
2, so the technique adopted in the present embodiment can be standard technology, the condition wherein carrying out etching is exactly mainly pass into reacting gas, and raised temperature.
Specifically, Fig. 3 is according to the schematic diagram after the revising the through hole after being partially filled of the TSV through hole processing method of the embodiment of the present invention.Use SiCoNi to the through-silicon via sidewall SiO after being partially filled with further reference to Fig. 3, Fig. 3
2thin layer carries out the schematic diagram revised.As shown in Figure 3, with SiCoNi to the through-silicon via sidewall SiO after being partially filled
2thin layer is revised.Silicon through hole after SiCoNi has the good insulating oxide layer film of one deck guarantor type spreadability.The term " covering of guarantor's type " used in this specification is this area generic term, and specifically, guarantor's type covers and refers to that the surface of total is all capped, but overall pattern is substantially constant.
Refer again to Fig. 5, as shown in Figure 5, in the step S4 of Fig. 5, wet-cleaned is carried out to silicon chip.
Specifically, Fig. 4 be according to the described mask of removal of the TSV through hole processing method of the embodiment of the present invention after schematic diagram.It is the schematic diagram of one or more layers other films (as silicon nitride etc.) being removed the region of non-TSV structure by wet-cleaned with further reference to Fig. 4, Fig. 4.As shown in Figure 4, illustrated therein is the schematic diagram of the silicon chip obtained after employing wet processing removes hard mask.
Thus, then the processing step performing the follow-up guarantor's type covering such as forming copper barrier layer and copper seed layer and so on can be continued.Further, subsequent step after this can not have received the impact of the scallop pattern of TSV through hole sidewall, ensure that processing quality and rate of finished products.
In a word, according to the present invention, can when creating the scallop pattern of TSV through hole sidewall, the insulating oxide that guarantor's type covers is formed on scallop pattern, thus reduce the difficulty of filling TSV through hole, thus improve the quality of the subsequent techniques such as the filling of TSV through hole, finally reduce the possibility of TSV component failure.Meanwhile, the present invention need not experience long thermal oxidation technology to eliminate the scallop pattern of sidewall, improves production efficiency.
In a preferred embodiment of the invention, adopt high-aspect-ratio technique (HARP) and SiCoNi technique to define the insulating oxide of guarantor's type covering, realize splendid guarantor's type coverage effect thus.But meanwhile, those skilled in the art obviously can realize above-mentioned insulating oxide according to other method more well known in the art.
It should be noted that, although above-described embodiment with silicon materials (such as silicon substrate and silicon through hole) for example describes principle of the present invention; But, it will be understood by those skilled in the art that, if do not adopt silicon materials as substrate in semiconductor fabrication process, but adopt such as germanium and so on other material do or some composite materials as substrate, still principle of the present invention can be implemented equally, therefore, the present invention is not limited to silicon substrate and silicon through hole.Further, other technique outside wet processing such as certainly can be adopted to remove hard mask; And the selection of mask is not limited to the hard mask exemplified in embodiment.
Further, those skilled in the art are understandable that, the present invention can not only eliminate the scallop pattern of the through-silicon via sidewall that the assorted etching technics of ripple produces, and can eliminate the scallop pattern of the through-silicon via sidewall that other technique produces.
It should be noted that, those skilled in the art are understandable that, although describe the present invention with each step in above-mentioned flow process, the present invention does not get rid of the existence of other step in addition to the foregoing steps.Those skilled in the art are understandable that, without departing from the scope of the invention, can add other step to form other structure or to realize other object in described step.It will be apparent to those skilled in the art that and can carry out various change and distortion to the present invention without departing from the scope of the invention.Described embodiment is only for illustration of the present invention, instead of restriction the present invention; The present invention is not limited to described embodiment, but is only defined by the following claims.
Claims (9)
1. a processing method of through holes, is characterized in that comprising step:
Mask is provided;
Etched substrate is carried out to form through hole according to mask;
Be partially filled described through hole, to form the insulating oxide that guarantor's type covers on the sidewall of described through hole; And remove described mask; Wherein being partially filled described through hole makes the centre of described through hole leave gap, and revises the described through hole after being partially filled; Wherein the described through hole after being partially filled is revised and comprise with the step forming the insulating oxide that guarantor's type covers on the sidewall of described through hole: use SiCoNi to etch the oxide be partially fill in described through hole, to form the insulating oxide that guarantor's type covers on the sidewall of described through hole.
2. processing method of through holes according to claim 1, is characterized in that, wherein said substrate is silicon substrate, and described through hole is silicon through hole.
3. processing method of through holes according to claim 1, is characterized in that, the step being wherein partially filled described through hole comprises: by high-aspect-ratio technique grown oxide layer.
4. processing method of through holes according to claim 1, is characterized in that, wherein saidly carrys out etched substrate according to mask and is realized by the assorted etching technics of ripple with the step forming through hole.
5. processing method of through holes according to claim 3, is characterized in that, wherein in high-aspect-ratio technique, at O
3the time of/TEOS is grow oxide under the condition of 100s-3000s.
6. processing method of through holes according to claim 5, is characterized in that, wherein in high-aspect-ratio technique, after grow oxide, silicon chip is placed in 900 DEG C to 1200 DEG C, annealing 20 minutes to 1 hour under the environment of steam.
7. processing method of through holes according to claim 1, is characterized in that, the wherein said step being partially filled described through hole does not close described through hole.
8. processing method of through holes according to claim 1, is characterized in that, wherein said mask is hard mask, and described hard mask comprises the stacked structure of silicon nitride, anti-reflecting layer and photoresist layer.
9. processing method of through holes according to claim 1, is characterized in that, the step of the described mask of wherein said removal comprises employing wet processing and removes described mask.
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050434B (en) * | 2011-10-17 | 2015-09-02 | 中芯国际集成电路制造(上海)有限公司 | The lithographic method of silicon through hole |
| US10269863B2 (en) * | 2012-04-18 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for via last through-vias |
| CN102738074B (en) * | 2012-07-05 | 2014-07-02 | 中微半导体设备(上海)有限公司 | Method for forming semiconductor structure |
| CN103879951B (en) * | 2012-12-19 | 2016-01-06 | 中国科学院上海微系统与信息技术研究所 | The preparation method of silicon through hole |
| CN103700617B (en) * | 2013-11-04 | 2016-01-20 | 中国航天科技集团公司第九研究院第七七一研究所 | Based on the TSV process of SOI substrate high reliability |
| CN104944366A (en) * | 2014-03-26 | 2015-09-30 | 中国科学院微电子研究所 | Monitoring method for silicon deep hole process |
| CN104051321A (en) * | 2014-04-22 | 2014-09-17 | 上海华力微电子有限公司 | Method for preparing shallow trench isolation structure |
| US10585254B2 (en) * | 2017-11-17 | 2020-03-10 | Samsung Electronics Co., Ltd. | Vertical optical via and method of fabrication |
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| CN101075554A (en) * | 2006-05-19 | 2007-11-21 | 三洋电机株式会社 | Manufacturing method of semiconductor device |
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| US6586334B2 (en) * | 2000-11-09 | 2003-07-01 | Texas Instruments Incorporated | Reducing copper line resistivity by smoothing trench and via sidewalls |
| JP2006012889A (en) * | 2004-06-22 | 2006-01-12 | Canon Inc | Method for manufacturing semiconductor chip and semiconductor device |
| US7262134B2 (en) * | 2005-09-01 | 2007-08-28 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
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