CN208767278U - Semiconductor devices - Google Patents
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- CN208767278U CN208767278U CN201821649396.2U CN201821649396U CN208767278U CN 208767278 U CN208767278 U CN 208767278U CN 201821649396 U CN201821649396 U CN 201821649396U CN 208767278 U CN208767278 U CN 208767278U
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Abstract
The utility model provides a kind of semiconductor devices, belongs to technical field of semiconductors.The device includes: semiconductor substrate, the fleet plough groove isolation structure in semiconductor substrate between the multiple active areas and active area being arranged in array of setting；Embedded type word line is located in semiconductor substrate, and intersects with the array of active area；Groove is located above embedded type word line；Separation layer is partially filled in groove, and covers embedded type word line；Bit line contact layer, bottom are fin structure, the top in region between embedded type word line in each active area, and two base angles of bit line contact layer are located in same active area in two grooves；Bit line conductive layer, vertical view face are projected as bar shaped, and bit line conductive layer covers the upper surface of bit line contact layer, and intersects with the array of active area.The utility model can increase the area of bit line contact, reduce contact resistance, improve the reading and writing data performance of storage unit.
Description
Technical field
The utility model relates to technical field of semiconductors more particularly to a kind of semiconductor devices.
Background technique
With the development of semiconductor technology, the size of semiconductor devices is smaller and smaller.In existing semiconductor devices, formed
Bitline contact areas also with device size reduction and reduce, typically resulting in bitline contact region, to generate higher contact electric
Resistance, so that storage unit is difficult to carry out normal reading and writing data, influences the performance of semiconductor devices.
It is therefore desirable to propose a kind of new semiconductor device structure.
It should be noted that information is only used for reinforcing the background to the utility model disclosed in above-mentioned background technology part
Understanding, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Utility model content
The purpose of this utility model is to provide a kind of semiconductor devices, and then overcome at least to a certain extent existing
The higher problem of bit line of semiconductor device contact resistance.
Other characteristics and advantages of the utility model will be apparent from by the following detailed description, or partially by this
The practice of utility model and acquistion.
The utility model provides a kind of semiconductor devices, comprising: semiconductor substrate, the interior setting of the semiconductor substrate are multiple
The fleet plough groove isolation structure between active area and the active area being arranged in array；Embedded type word line is partly led positioned at described
In body substrate, and intersect with the array of the active area；Groove is located above the embedded type word line；Separation layer is partly filled out
It fills in the groove, and covers the embedded type word line；Bit line contact layer, bottom are fin structure, are located at each described active
In area between embedded type word line region top, and two base angles of institute's bitline contact layer are located at two in same active area
In a groove；Bit line conductive layer, vertical view face are projected as bar shaped, and institute's bit line conductive layer covers the upper table of institute's bitline contact layer
Face, and intersect with the array of the active area.
In a kind of exemplary embodiment of the utility model, the semiconductor devices further include: insulating layer, described in covering
The upper surface of bit line conductive layer.
In a kind of exemplary embodiment of the utility model, the semiconductor devices further include: dielectric layer, described in filling
The upper surface of semiconductor devices, and there is the upper surface concordant with institute's bit line conductive layer.
In a kind of exemplary embodiment of the utility model, the semiconductor devices further include: storage node contact plug,
In the dielectric layer.
In a kind of exemplary embodiment of the utility model, the semiconductor devices further include: barrier layer, described in covering
Semiconductor substrate upper surface, the upper surface of the barrier, institute's bit line conductive layer side wall and bit line contact layer side wall.
The exemplary embodiment of the utility model has the advantages that
On the one hand, the structure for changing existing semiconductor devices neutrality line contact, passes through side contact, fin structure etc.
Mode increases bit line contact layer and the contact surface quantity of semiconductor substrate and reduces to increase the area of bit line contact
Contact resistance improves the reading and writing data performance of storage unit.On the other hand, the semiconductor devices of the present exemplary embodiment is formed
The process flow of structure is simple, and practicability is higher.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The utility model can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows and meets the utility model
Embodiment, and be used to explain the principles of the present invention together with specification.It should be evident that the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, it is also possible to obtain other drawings based on these drawings.
Fig. 1 shows a kind of flow chart of bit line of semiconductor device forming method in the present exemplary embodiment；
Fig. 2 to Figure 17 shows a kind of flow chart signal of bit line of semiconductor device forming method in the present exemplary embodiment；
Figure 18 and Figure 19 shows a kind of sub-process diagram of bit line of semiconductor device forming method in the present exemplary embodiment
Meaning；
Figure 20 to Figure 22 shows the sub-process figure of another bit line of semiconductor device forming method in the present exemplary embodiment
Signal；
Figure 23 and Figure 24 show a kind of structural schematic diagram of semiconductor devices in the present exemplary embodiment；
Figure 25 shows the structural schematic diagram of another semiconductor devices in the present exemplary embodiment.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, thesing embodiments are provided so that the utility model will
More fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described spy
Sign, structure or characteristic can be incorporated in any suitable manner in one or more embodiments.
The exemplary embodiment of the utility model provides firstly a kind of bit line of semiconductor device forming method, with reference to Fig. 1
With shown in Fig. 2~Figure 17, this method may comprise steps of S110~S160:
Step S110 provides semiconductor substrate 101 with reference to Fig. 2 and Fig. 3, and semiconductor substrate 101 includes active area 102, shallow
The groove 105 of 103 top of groove isolation construction 104, embedded type word line 103 and embedded type word line.
Fig. 2 is the top view of semiconductor substrate 101, makees side view respectively with AA ' and the direction BB ', obtains Fig. 3.Wherein, half
Conductor substrate 101 can be p-type silicon substrate, n-type silicon substrate, silicon-Germanium substrate etc..Active area 102 leads in semiconductor substrate 101
It often arranges, is separated by fleet plough groove isolation structure 104 in the form of an array；Source electrode and drain electrode can be pre-formed in active area 102,
The position of source electrode and drain electrode can also be pre-defined, and during the present embodiment forms bit line, passes through ion implantation technology
Source electrode and drain electrode are formed in the corresponding position of semiconductor substrate 101.
Embedded type word line 103 can intersect with active area 102, generally include wordline conductive layer and grid electrode layer, grid
Electrode layer is located at the region that embedded type word line 103 intersects with active area 102, can use polysilicon, and wordline conductive layer is located at grid
The top of pole electrode layer can use tungsten, can also add the adherency formed by conductive materials such as titanium nitride, titaniums between the two
Layer, the present embodiment are not specially limited this.When forming embedded type word line 103, it can be initially formed embedded type word line hole, then to
The material of above-mentioned grid electrode layer Yu wordline conductive layer is wherein filled, can be not completely filled to the progress of embedded type word line hole, or
Person is etched back after filling, to reserve the groove of certain depth in embedded type word line hole, in order to it is subsequent can be
Isolated material is filled in groove, the structure of embedded type word line 103 Yu top is isolated.
Step S120, with reference to Fig. 4, layer deposited isolating 106, separation layer 106 fills groove and covers semiconductor substrate 101
Upper surface.
Wherein, separation layer 106 can be used for being isolated flush type word-line and the subsequent other structures formed above, can adopt
With isolated materials such as silica, boron-phosphorosilicate glass；In one exemplary embodiment, the material of separation layer 106 can be nitridation
The insulation performance of silicon or silicon oxynitride, both materials is preferable, and silicon therein-nitrogen key is conducive to be selected in the next steps
Selecting property etching.
Can by CVD (Chemical Vapor Deposition, chemical vapor deposition) process deposits separation layer 106,
During the deposition process, then the groove being first filled with above flush type word-line covers the upper table of entire semiconductor substrate 101
Face forms complete separation layer 106.In one exemplary embodiment, after layer deposited isolating 106, CMP can also be passed through
(Chemical Mechanical Polishing, chemical mechanical grinding) technique planarizes the upper surface of separation layer 106
Processing, obtains smooth film layer.
Step S130 is isolated with reference to Fig. 5 to Fig. 8 using 107 selective etch of the first mask layer with active area figure
Layer 106 makes remaining 106 thickness of separation layer in groove be less than the depth of groove.
Active area figure can be as shown in figure 5, form the first mask layer of exposed active area 102 along 102 direction of active area
107 figure.In etching process, the separation layer 106 of 102 top of active area is removed, 104 top of fleet plough groove isolation structure
Separation layer 106 is retained；It can be etch stop layer with semiconductor substrate 101, and carry out a degree of over etching, by groove
Interior separation layer 106 etches a part, reserves the smaller shallow grooves of depth.Pay attention to needing the isolation in groove in the process
Layer 106 carries out certain over etching, but can not etch completely it, will affect the effect of the insulation blocking to embedded type word line 103.
In one exemplary embodiment, the biggish groove of depth can be reserved above embedded type word line 103 in advance, then is walked
The depth of over etching can be controlled in rapid S130, in a wider context to control remaining 106 thickness of separation layer.
In one exemplary embodiment, when the material of separation layer 106 is silicon nitride, tetrafluoro can be used in step S130
Methane and oxygen are used as etching gas, and progress dry etching is preferable to the etching effect of silicon nitride, to silicon substrate or shallow trench every
From silica etching effect it is poor, can effectively remove separation layer 106, retain the surface texture of semiconductor substrate 101.
Step S140, with reference to Fig. 9 and Figure 10, depositing bitlines contact layer 108, bit line contact layer 108 fills separation layer 106
Upper surface groove.
With reference to shown in above-mentioned Fig. 7 and Fig. 8, in step s 130 after selective etch separation layer 106, between active area 102
The separation layer 106 of the top of fleet plough groove isolation structure 104 be retained, therefore there is more groove in the upper surface of separation layer 106,
I.e. along the groove in 102 direction of active area.Above-mentioned groove can be filled with depositing bitlines contact layer 108 in step S140, in other words,
Bit line contact layer 108 can fill the 103 remaining groove in top of embedded type word line, and cover the upper surface of active area 102.
It should be noted that the upper surface of bit line contact layer 108 can be concordant with the upper surface of insulating layer, control can be passed through
The process conditions of deposition are made, to obtain the suitable bit line contact layer 108 of thickness；A degree of excess deposition can also be carried out,
Excessive bit line contact layer 108 is removed by CMP process again, and obtains table on smooth bit line contact layer 108 and separation layer 106
Face, CMP process process can be stop layer with separation layer 106.
Bit line contact layer 108 can be formed using conductive material, such as can use PVD (Physical Vapor
Deposition, physical vapour deposition (PVD)) process deposits tungsten, titanium, aluminium etc.；In one exemplary embodiment, bit line contact layer
108 material is also possible to polysilicon, and the electric conductivity of polysilicon is preferable, and preferable with the contact performance of semiconductor substrate 101.
Step S150, with reference to Figure 11 and Figure 12, depositing bitlines conductive layer 109.
Bit line conductive layer 109 can cover the upper surface of entire device architecture, specifically, covering bit line contact layer 108
With the upper surface of separation layer 106.
In one exemplary embodiment, the material of bit line conductive layer 109 may include tungsten, titanium tungsten, one in titanium nitride
Kind is a variety of, and when including multiple material, bit line conductive layer 109 can be deposited simultaneously by multiple material and be formed, a variety of materials
Ingredient is uniformly distributed in bit line conductive layer 109.
In one exemplary embodiment, bit line conductive layer 109 can be identical with the material of bit line contact layer 108, such as can
To be all tungsten, usually before depositing bitlines contact layer 108, it can be initially formed one layer of adhesion layer, adhesion layer is usually titanium nitride layer,
Then depositing bitlines conductive layer 109 can be completed with bit line contact layer 108 by primary depositing, deposit excessive tungsten, covering every
The upper surface of absciss layer 106.
Step S160 utilizes the 110 selective etch bit line of the second mask layer with bit line figure with reference to figures 13 to Figure 17
Conductive layer 109 and bit line contact layer 108, the second mask layer 110 are greater than the active area along the cross-sectional width of any active area 102
Section spacing of two embedded type word lines 103 along active area 102 in 102.
As shown in Figure 13 and Figure 15, the second mask layer 110 defines bit line figure, intersects with active area 102, the area of intersection
Domain, that is, bit line contact region, the second mask layer 110 cover bit line region, the region other than exposure bit line.As shown in figure 14,
Second mask layer 110 is H along the cross-sectional width of active area 102, and two embedded type word lines 103 are along active area 102 in the active area 102
Section spacing be h, H > h.In etching process, the only bit line conductive layer 109 and bit line contact layer of the lower section of the second mask layer 110
108 are retained, wherein in the shallow grooves of two embedded type word lines, 103 top of same active area 102, at least one shallow grooves
Interior bit line contact layer 108 is partly retained, Figure 16 with Figure 17 shows bit line contact layers 108 simultaneously partially to remain in two
In a shallow grooves, in other cases, can also only partially it remain in the shallow grooves in left side or the shallow grooves on right side, then position
Line contact layer 108 is in addition to yet forming the contact of at least one side with other than the overlying contact of semiconductor substrate 101, to increase
The area for having added bit line contact, reduces contact resistance.
In one exemplary embodiment, the second mask layer 110 can be with the active area along the section of any active area 102
The intermediate region of two embedded type word lines 103 is aligned along the kernel of section of active area 102 in 102, i.e. the section of the second mask layer 110
The boundary of the intermediate region of embedded type word line 103 is all had exceeded in two sides, then carries out selective etch using the second mask layer 110
Afterwards, can be formed bottom as shown in figure 17 be fin (Fin) structure bit line contact layer 108, be equivalent on three faces with
Semiconductor substrate 101 forms contact, can further increase the area of bit line contact, reduces contact resistance.
It should be noted that the material of the first mask layer 107 and the second mask layer 110 may be the same or different, lead to
It often can be using bottom anti-reflection layer (Bottom Anti-Reflection Coating, BARC) and photoresist layer (Photo
Resist, PR) lamination form the first mask layer 107 and the second mask layer 110；In some embodiments, in order to further protect
The structure for protecting 110 lower section of the first mask layer 107 or the second mask layer is not etched, and can also increase silicon in the top of photoresist layer
The hard mask layer of the ingredients such as oxide or silicon nitride.This example embodiment is not specially limited this.
Based on above description, in the present example embodiment, on the one hand, change existing semiconductor devices neutrality line and connect
The structure of touching increases the contact of bit line contact layer 108 with semiconductor substrate 101 by modes such as side contact, fin structures
Face quantity reduces contact resistance to increase the area of bit line contact, improves the reading and writing data performance of storage unit.
On the other hand, the present exemplary embodiment is by controlling the cross-sectional width of the second mask layer 110, and is selected by the second mask layer 110
Selecting property etches bit line contact layer 108, and to realize the structural improvement of bit line contact, process flow is simple, and practicability is higher.
In one exemplary embodiment, after step s 150, bit line of semiconductor device forming method can also include following
Step:
With reference to Figure 18, depositing insulating layer 111；
Correspondingly, step S160 can be realized by following steps:
It is connect using 110 selective etch insulating layer of the second mask layer, bit line conductive layer 109 with bit line figure with bit line
Contact layer 108；Obtain structure as shown in figure 19.
Wherein, insulating layer 111 covers the upper surface of bit line conductive layer 109.Usually in the subsequent process, capacitor will also be formed
Structure, therefore insulating layer 111 can play insulation and buffer action to bit line structure.After depositing the insulating layer, in step S160
It also needs to perform etching insulating layer 111, according to the actual situation, step etching can be used, can also be etched using a step.
In one exemplary embodiment, the material of insulating layer 111 may include silica, silicon nitride, in silicon oxynitride
It is one or more, these three materials all have preferable insulating properties and isolation.Wherein, when insulating layer 111 includes a variety of materials
When expecting ingredient, the lamination being made of multiple single component film layers can be.
In one exemplary embodiment, after step S160, bit line of semiconductor device forming method can also include following
Step:
With reference to Figure 20, dielectric layer 112, dielectric layer 112 fills the upper surface gap of separation layer 106 and covers semiconductor
The upper surface of substrate 101；
With reference to Figure 21, storage node contact plug 113 is formed in dielectric layer 112.
Wherein, dielectric layer 112 can be silicon dioxide layer, is also possible to silicon nitride/silicon dioxide/silicon nitride structure and answers
Close layer.Dielectric layer 112 can be used to form interlayer dielectric (Inter-level dielectric, ILD) structure, and to bitline junction
Structure plays certain fixation and protective effect.Storage node contact plug 113 is used for the top in semiconductor substrate 101 and rear technique
Contact is formed between the capacity cell of formation, and conductive material, such as polysilicon, titanium nitride, titanium, tungsten etc. can be used, it can also be by
These materials form the storage node contact plug 113 of laminated construction, and the present embodiment is not specially limited this.
It further,, can be first in 101 upper surface of semiconductor substrate, isolation before dielectric layer 112 with reference to Figure 22
The side wall of 106 upper surface of layer, the side wall of bit line conductive layer 109 and bit line contact layer 108 forms barrier layer 114, barrier layer 114
Material may include one of silica, silicon nitride, silicon oxynitride or a variety of, and barrier layer 114 can further play
Insulation and buffer action.In one exemplary embodiment, ALD (Atomic layer deposition, atomic layer can be passed through
Deposition) technique formation barrier layer 114, be conducive to the thickness and uniformity that control barrier layer 114.
The exemplary embodiment of the utility model additionally provides a kind of semiconductor devices, and the structure of the semiconductor devices can be with
With reference to shown in Figure 23 and Figure 24, comprising: semiconductor substrate 101, semiconductor substrate 101 is interior to be arranged multiple active areas 102 and have
Fleet plough groove isolation structure 104 between source region 102；Embedded type word line 103 is located in semiconductor substrate 101, and and active area
102 intersections；Groove 105 is located at 103 top of embedded type word line；Separation layer 106 is partially filled in groove 105, and covers
Embedded type word line 103；Bit line contact layer 108, bottom are fin structure, are located in each active area 102 between embedded type word line 103
The top in region, and two base angles of bit line contact layer 106 are located in two grooves 105 in same active area 102；Position
Line conductive layer 109, vertical view face are projected as bar shaped, cover the upper surface of bit line contact layer 108, and the array with active area 102
Intersection.
Structure based on the semiconductor devices, on the one hand, the structure of existing semiconductor devices neutrality line contact is changed,
The contact surface quantity that bit line contact layer and semiconductor substrate are increased by modes such as side contact, fin structures, to increase
The area of bit line contact, reduces contact resistance, improves the reading and writing data performance of storage unit.On the other hand, this example
The semiconductor devices of property embodiment can through the foregoing embodiment in method formed, process flow is simple, and practicability is higher.
In one exemplary embodiment, with reference to shown in above-mentioned Figure 19, semiconductor devices can also include insulating layer 111, cover
The upper surface of lid bit line conductive layer 109.
In one exemplary embodiment, with reference to shown in above-mentioned Figure 20, semiconductor devices further includes dielectric layer 112, filling half
The upper surface of conductor device, and there is the upper surface concordant with bit line conductive layer 109.
In one exemplary embodiment, with reference to shown in above-mentioned Figure 21, semiconductor devices further includes storage node contact plug
113, it is located in dielectric layer 112.
In one exemplary embodiment, with reference to shown in above-mentioned Figure 22, semiconductor devices further includes barrier layer 114, covering half
101 upper surface of conductor substrate, 106 upper surface of separation layer, bit line conductive layer 109 side wall and bit line contact layer 108 side wall.
In one exemplary embodiment, the structure of semiconductor devices can be with reference to shown in Figure 25, and bit line structure includes fin
Bit line contact layer 108 and bit line conductive layer 109, and be formed with barrier layer 114 on the outer wall；The upper surface of semiconductor devices is empty
Gap is filled with dielectric layer 112, is equipped with storage node contact plug 113 in dielectric layer 112.
It is practical new to will readily occur to this after considering specification and practicing embodiment disclosed herein by those skilled in the art
The other embodiments of type.This application is intended to cover any variations, uses, or adaptations of the utility model, these changes
Type, purposes or adaptive change follow the general principle of the utility model, and including undocumented skill of the utility model
Common knowledge or conventional techniques in art field.The description and examples are only to be considered as illustrative, the utility model
True scope and spirit are pointed out by claim.
It should be understood that the utility model is not limited to the accurate knot for being described above and being shown in the accompanying drawings
Structure, and can carry out various modifications and change in the case where without departing from the scope.The scope of the utility model is only by appended
Claim limit.
Claims (5)
1. a kind of semiconductor devices characterized by comprising
Semiconductor substrate, the semiconductor substrate is interior to be arranged between multiple active areas being arranged in array and the active area
Fleet plough groove isolation structure；
Embedded type word line is located in the semiconductor substrate, and intersects with the array of the active area；
Groove is located above the embedded type word line；
Separation layer is partially filled in the groove, and covers the embedded type word line；
Bit line contact layer, bottom are fin structure, the top in region between embedded type word line in each active area, and institute
Two base angles of bitline contact layer are located in same active area in two grooves；
Bit line conductive layer, vertical view face are projected as bar shaped, and institute's bit line conductive layer covers the upper surface of institute's bitline contact layer, and
Intersect with the array of the active area.
2. semiconductor devices according to claim 1, which is characterized in that further include:
Insulating layer covers the upper surface of institute's bit line conductive layer.
3. semiconductor devices according to claim 1, which is characterized in that further include:
Dielectric layer fills the upper surface of the semiconductor devices, and has the upper surface concordant with institute's bit line conductive layer.
4. semiconductor devices according to claim 3, which is characterized in that further include:
Storage node contact plug is located in the dielectric layer.
5. semiconductor devices according to claim 1, which is characterized in that further include:
Barrier layer covers the semiconductor substrate upper surface, the upper surface of the barrier, the side wall of institute's bit line conductive layer and position
The side wall of line contact layer.
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| CN201821649396.2U CN208767278U (en) | 2018-10-11 | 2018-10-11 | Semiconductor devices |
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| CN201821649396.2U CN208767278U (en) | 2018-10-11 | 2018-10-11 | Semiconductor devices |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048467A (en) * | 2018-10-11 | 2020-04-21 | 长鑫存储技术有限公司 | Semiconductor device bit line forming method and semiconductor device |
| WO2021109580A1 (en) * | 2019-12-06 | 2021-06-10 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| CN113594097A (en) * | 2021-07-29 | 2021-11-02 | 长鑫存储技术有限公司 | Embedded bit line structure, manufacturing method thereof and semiconductor structure |
| CN114639721A (en) * | 2022-04-29 | 2022-06-17 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
-
2018
- 2018-10-11 CN CN201821649396.2U patent/CN208767278U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048467A (en) * | 2018-10-11 | 2020-04-21 | 长鑫存储技术有限公司 | Semiconductor device bit line forming method and semiconductor device |
| WO2021109580A1 (en) * | 2019-12-06 | 2021-06-10 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| CN113594097A (en) * | 2021-07-29 | 2021-11-02 | 长鑫存储技术有限公司 | Embedded bit line structure, manufacturing method thereof and semiconductor structure |
| CN113594097B (en) * | 2021-07-29 | 2023-09-26 | 长鑫存储技术有限公司 | Buried bit line structure, manufacturing method thereof and semiconductor structure |
| CN114639721A (en) * | 2022-04-29 | 2022-06-17 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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