TW201711169A - Cell contact structure - Google Patents

Abstract

A cell contact structure includes a semiconductor substrate having a main surface, an upwardly protruding structure disposed on the main surface, a cell contact region on the main surface and adjacent to the upwardly protruding structure, an interfacial thin film conformally covering the upwardly protruding structure and the cell contact region, and a contact plug on the cell contact region. The interfacial thin film is disposed between the contact plug and the cell contact region.

Description

Cell contact structure

SUMMARY OF THE INVENTION The present invention generally relates to a semiconductor device and a method of fabricating the same, and more particularly to a cell contact structure of a dynamic random access memory (DRAM) and a method of fabricating the same.

In the field of semiconductors, a dynamic random access memory (DRAM) is a capacitive storage element that is integrated in an integrated circuit and stores individual bit data in individual capacitors and can be randomly read. DRAMs typically consist of a number of charge storage cells arranged in an array, where each charge storage cell typically contains a capacitor and a transistor.

In general, each transistor in a DRAM includes a gate, a drain in the semiconductor substrate, and a source spaced apart from the drain. The gate is usually electrically connected to a word line, the source is usually electrically connected to a digit line, and the drain is usually electrically connected to a capacitor by a cell contact structure.

The need for continuous miniature components accelerates the evolution of DRAM cell design, resulting in smaller feature sizes, cell area, and unit density. However, as the contact area is reduced, the size of the cell contact structure is also reduced, resulting in higher contact resistance and tighter process window.

Therefore, there is still a need in the art for an improved DRAM cell contact structure that avoids the problems faced by the prior art described above without increasing process complexity.

SUMMARY OF THE INVENTION A primary object of the present invention is to provide an improved unit cell contact structure and method of fabricating the same that can reduce contact resistance increase and improve process margin.

A cell contact structure according to the present invention includes a semiconductor substrate having a major surface; an upwardly convex structure on the major surface; and a cell contact region on the major surface adjacent to the upwardly convex a structure; an interface film on the sidewall of the upwardly convex structure and the cell contact region; and a contact plug on the cell contact region, wherein the interface film is interposed between the contacts The plug is in contact with the unit cell.

According to an embodiment of the invention, the interface film comprises a metal oxide. The metal oxide comprises aluminum oxide, cerium oxide, cerium oxide, or cerium oxide. Wherein the interface film has a thickness of less than 10 nm.

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In the following description, numerous specific details are set forth in the However, it is apparent that the invention may be practiced without these specific details. Moreover, some well known system configurations and process steps have not been disclosed in detail, as these should be well known to those skilled in the art.

The drawings of the embodiments of the present invention are to be considered as illustrative and not to In addition, the same or similar features are generally described with the same reference numerals to facilitate the description and description.

In the field of transistor and integrated circuit processes, the proper term "main surface" is generally considered to be the side that forms a plurality of transistors, for example, in a planar process of a semiconductor. Similarly, in the present specification, the proper noun "vertical" is generally considered to be substantially at right angles to the major surface. Usually the main surface is the same as the <100> lattice plane of the single crystal germanium layer, which is where the field effect transistor is formed.

1 to 8 illustrate a method of fabricating a cell contact structure of a dynamic random access memory (DRAM) device in accordance with an embodiment of the invention. First, as shown in Fig. 1, a semiconductor substrate 10, such as a germanium substrate, is provided. It is to be understood that the semiconductor substrate 10 can also be composed of other semiconductor materials or wafers. The semiconductor substrate 10 has a major surface 10a. According to an embodiment of the present invention, a shallow trench isolation (STI) structure 20 and a plurality of trench gate structures 21, 22, 23, and 24 are formed under the main surface 10a of the semiconductor substrate 10. Each of the trench gate structures 21, 22, 23 and 24 includes a gate dielectric layer 202, a conductive layer 210 and a cap layer 220. The conductive layer 210 may include titanium nitride or tungsten, but is not limited thereto. The cap layer 220 may contain hafnium oxide or tantalum nitride or the like.

In accordance with an embodiment of the present invention, at least two adjacent upwardly projecting structures 30 and 40 are provided on the major surface 10a of the semiconductor substrate 10. In accordance with an embodiment of the invention, the upwardly projecting structures 30 and 40 are in close proximity. When viewed from above, the upwardly projecting structures 30 and 40 extend along a first direction and are parallel to each other. When viewed from above, the upwardly projecting structures 30 and 40 each have a wavy or zigzag pattern. It will be appreciated that for ease of illustration and description, this embodiment exemplifies only two upwardly convex structures.

In accordance with an embodiment of the present invention, the upwardly convex structure 30 includes a lower portion 300 of enamel, a metal portion 310 directly above the lower portion 300 of the enamel, and an insulating layer over the metal portion 310 and covering the sidewall thereof. 320, for example, a tantalum nitride layer. A patterned contact oxide layer 330, such as a hafnium oxide layer, is disposed over the insulating layer 320. The upwardly projecting structure 30 has two opposing side walls 30a and 30b.

In accordance with an embodiment of the present invention, the upwardly projecting structure 40 includes a lower portion 400 of enamel, a metal portion 410 directly above the lower portion 400 of the enamel, and a sidewall over the metal portion 410 covering the metal portion. The insulating layer 420 is, for example, a tantalum nitride layer. A patterned contact oxide layer 430, such as a hafnium oxide layer, is disposed over the insulating layer 420. The upwardly projecting structure 40 has two opposing side walls 40a and 40b. Therein, the side wall 40a is close to and directly faces the side wall 30a.

It is to be understood that the upwardly projecting structures 30 and 40 are for illustrative and descriptive purposes only. According to embodiments of the present invention, the metal portions 310 and 410 directly above the lower portions 300 and 400 of the enamel may serve as digit lines in the DRAM device, but are not limited thereto.

The patterned contact oxide layers 330 and 430 extend in a second direction and are parallel to each other when viewed from above. According to an embodiment of the invention, the first direction and the second direction are orthogonal to each other at a right angle, but are not limited thereto. According to an embodiment of the present invention, the patterned contact oxide layers 330 and 430 may be composed of a spin-on (SOD) dielectric material, but are not limited thereto. The patterned contact oxide layers 330 and 430 may be straight lines, but are not limited thereto.

In accordance with an embodiment of the invention, a cell contact region 230 is adjacent to the trench gate structure 22 on the semiconductor substrate 10, and a cell contact region 240 is adjacent to the trench gate structure 23. It is to be understood that the shallow trench isolation (STI) structure 20 and the layout configuration of the plurality of trench gate structures 21, 22, 23 and 24 are merely illustrative and are not intended to limit the scope of the invention.

As shown in FIG. 2, an interface film is deposited conformally on the semiconductor substrate 10 and on the upwardly convex structures 30 and 40 by a chemical vapor deposition (CVD) process or other suitable process according to an embodiment of the present invention. Interfacial thin film) 260. In accordance with an embodiment of the present invention, the interface film 260 is conformally overlying the surfaces of the contact oxide layers 330 and 430, the sidewalls 30a, 30b, 40a, 40b of the upwardly protruding structures 30 and 40, and the cell contact regions 230, 240. on.

According to an embodiment of the present invention, the interface film 260 may be a metal oxide film, for example, aluminum oxide (Al _x O _y ), yttrium oxide (Y _x O _y ), lanthanum oxide (LaO _x ), strontium oxide (SrO _x ), or the like. , but not limited to this. In other embodiments, the interface film 260 can also be a metal nitride film, such as titanium nitride. According to an embodiment of the invention, the thickness of the interface film 260 is preferably less than 10 nanometers. According to an embodiment of the present invention, prior to depositing the interface film 260, an ion implantation process may be performed to form doped regions (not shown), such as N-doped regions, in the cell contact regions 230, 240.

As shown in FIG. 3, a polysilicon layer 50 is deposited over the interface film 260 by a chemical vapor deposition process in accordance with an embodiment of the present invention. The polysilicon layer 50 covers the upwardly convex structures 30 and 40 and the patterned contact oxide layers 330 and 430. The polysilicon layer 50 is then etched back such that the patterned contact oxide layers 330 and 430 protrude from a top surface 50a of the polysilicon layer 50. A portion of the interface film 260 on the patterned contact oxide layers 330 and 430 is now exposed.

As shown in FIG. 4, a top surface 50a of the polysilicon layer 50 and the raised patterned contact oxide layers 330 and 430 are deposited by another chemical vapor deposition (CVD) process in accordance with an embodiment of the present invention. A shaped sidewall sublayer, such as a tantalum nitride layer. An anisotropic dry etch process is then performed to etch the sidewall sub-layers until the top surface 50a of the polysilicon layer 50 is exposed such that sidewall spacers 52a are formed on opposite sidewalls of the patterned contact oxide layers 330 and 430. The side wall 52a directly contacts the interface film 260. The sidewall sublayer may be tantalum nitride, hafnium oxynitride or hafnium oxide, but is not limited thereto.

As shown in FIG. 5, in accordance with an embodiment of the present invention, a dry etching process is performed to etch the polysilicon layer 50 not covered by the sidewall spacers 52a until the semiconductor substrate 10 is self-aligned by the sidewall sub-mount 52a as a hard mask. The interface film 260 on the major surface 10a is exposed such that a recessed trench 54 is formed in the polysilicon layer 50. In this etching step, the interface film 260 can serve as an etch stop layer. The self-aligned dry etch process described above splits the polysilicon layer 50 between the upwardly protruding structures 30 and 40 into two, forming a separate polysilicon contact plug 510.

As shown in FIG. 6, an etching process is then performed to selectively etch away the interface film 260 exposed at the bottom of the recess trench 54 to expose the main surface 10a of the semiconductor substrate 10. At this time, the exposed surface of the bottom of the recessed trench 54 may include the surface of the shallow trench insulating structure 20 and the surface of the partial cell contact regions 230, 240. The above etching process has a high etching selectivity, so that the degree of erosion of the main surface 10a of the semiconductor substrate 10 can be greatly reduced, thereby improving the problem of insufficient etching margin selection process in the past polycrystalline germanium/germanium substrate, and solving the past active region. AA clipping problem.

As shown in FIG. 7, a chemical vapor deposition process is subsequently performed to deposit a dielectric layer 60, such as a germanium oxide layer, on the semiconductor substrate 10. Dielectric layer 60 may fill recessed trenches 54 and cover sidewall spacers 52a and patterned contact oxide layers 330 and 430, in accordance with an embodiment of the present invention.

Most leaking, as shown in FIG. 8, a chemical mechanical polishing (CMP) process is performed to polish the dielectric layer 60, the interface film 260, the sidewalls 52a, and the patterned contact oxide layers 330 and 430 until the polysilicon contacts the plug 510. The top surface 510a is revealed. At this time, the sidewall spacer 52a and the patterned contact oxide layers 330 and 430 have been removed by polishing, and the interface film 260 on the surface of the patterned contact oxide layers 330 and 430 is also removed.

Structural features, as shown in FIG. 8, the cell contact structure 500 of the present invention is comprised of a polysilicon contact plug 510 and sidewalls 30a, 30b between the polysilicon contact plug 510 and the upwardly protruding structures 30 and 40, The interface film 260 is formed between 40a and 40b. The interface film 260 has an L-shaped cross-sectional profile and is interposed between the polysilicon contact plugs 510 and the cell contact regions 230, 240. In other words, the polysilicon contact plug 510 does not directly contact the cell contact regions 230, 240.

The interface film 260 may be a metal oxide film, for example, alumina (Al _x O _y ), yttrium oxide (Y _x O _y ), lanthanum oxide (LaO _x ), strontium oxide (SrO _x ), or the like, but is not limited thereto. In other embodiments, the interface film 260 can also be a metal nitride film, such as titanium nitride. According to an embodiment of the invention, the thickness of the interface film 260 is preferably less than 10 nanometers. By providing the interface film 260 between the polysilicon contact plug 510 and the cell contact regions 230, 240, the energy barrier of the interface can be reduced, thereby achieving the purpose of reducing the contact resistance. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Semiconductor substrate
10a‧‧‧Main surface
20‧‧‧Shallow trench insulation structure
21/22/23/24‧‧‧ Ditch-type gate structure
30/40‧‧‧Upward protruding structure
30a/30b/40a/40b‧‧‧ side wall
50‧‧‧Polysilicon layer
52a‧‧‧ Sidewall
54‧‧‧ recessed trench
60‧‧‧ dielectric layer
202‧‧‧ gate dielectric layer
210‧‧‧ Conductive layer
220‧‧‧ cover
230/240‧‧‧cell contact area
260‧‧‧Interface film
300/400‧‧‧Low quality parts
310/410‧‧‧Metal parts
320/420‧‧‧Insulation
330/430‧‧‧ patterned contact oxide
500‧‧‧cell contact structure
510‧‧‧Polysilicon contact plug
510a‧‧‧ top

The object and features of the present invention are apparent from the detailed description of the embodiments of the invention. 1 through 8 are schematic cross-sectional views illustrating a method of fabricating a cell contact structure of a dynamic random access memory (DRAM) device in accordance with an embodiment of the present invention. It should be noted that all the drawings are schematic diagrams for the purpose of illustration and drawing convenience, and the relative sizes and proportions are adjusted. The same symbols represent corresponding or similar features in different embodiments.

10‧‧‧Semiconductor substrate

10a‧‧‧Main surface

20‧‧‧Shallow trench insulation structure

21/22/23/24‧‧‧ Ditch-type gate structure

30/40‧‧‧Upward protruding structure

30a/30b/40a/40b‧‧‧ side wall

60‧‧‧ dielectric layer

202‧‧‧ gate dielectric layer

210‧‧‧ Conductive layer

220‧‧‧ cover

230/240‧‧‧cell contact area

260‧‧‧Interface film

300/400‧‧‧Low quality parts

310/410‧‧‧Metal parts

320/420‧‧‧Insulation

500‧‧‧cell contact structure

510‧‧‧Polysilicon contact plug

510a‧‧‧ top

Claims (11)

A cell contact structure comprising: a semiconductor substrate having a major surface; an upwardly convex structure on the major surface; a cell contact region on the major surface adjacent to the upwardly convex structure; a film covering the sidewall of the upwardly convex structure and the cell contact region; and a contact plug on the cell contact region, wherein the interface film is interposed between the contact plug and the crystal Between cell contact areas. The unit cell contact structure of claim 1, wherein the interface film comprises a metal oxide. The unit cell contact structure of claim 2, wherein the metal oxide comprises aluminum oxide, cerium oxide, cerium oxide, or cerium oxide. The unit cell contact structure of claim 2, wherein the interface film has a thickness of less than 10 nm. The unit cell contact structure of claim 1, wherein the interface film comprises a metal nitride. The unit cell contact structure of claim 5, wherein the metal nitride comprises titanium nitride. The unit cell contact structure of claim 1, wherein at least one trench gate structure is further disposed in the semiconductor substrate, and the cell contact region is adjacent to the trench gate structure. The unit cell contact structure of claim 7, wherein a shallow trench isolation structure is further disposed in the semiconductor substrate, and the cell contact region is located between the trench gate structure and the shallow trench isolation structure. . The unit cell contact structure of claim 1, wherein the upwardly convex structure comprises a lower portion of the enamel, a metal portion directly on the lower portion of the enamel, and a metal portion Insulation layer. The unit cell contact structure of claim 9, wherein the metal portion is a digit line of a dynamic random access memory element. The unit cell contact structure of claim 1, wherein the contact plug is a polysilicon contact plug.