CN106129010B - A method of forming 3D nand flash memory - Google Patents
A method of forming 3D nand flash memory Download PDFInfo
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- CN106129010B CN106129010B CN201610806577.0A CN201610806577A CN106129010B CN 106129010 B CN106129010 B CN 106129010B CN 201610806577 A CN201610806577 A CN 201610806577A CN 106129010 B CN106129010 B CN 106129010B
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 230000015654 memory Effects 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000000926 separation method Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000003860 storage Methods 0.000 abstract description 16
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000005457 optimization Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention relates to technical field of manufacturing semiconductors, a kind of more particularly to method for forming 3D nand flash memory, pass through the optimization to vertical hole and the structure of grid line, it may be implemented in a grid line, it is put into the figure of 9 row's vertical holes, then after the completion of vertical hole processing procedure, passes through the etching of first groove, realizing the separation of two rows vertical hole, reducing second groove and being spaced required area.The technique etched finally by back segment double patterning, realize the difference line of each CH BL in same layer GL SL, effectively to reduce the size of effective storage unit, to under the premise of not increasing technology difficulty, by optimization planar technology structure and back segment connecting line technics, equivalent storage area about 35% ~ 40% is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of methods for forming 3D nand flash memory.
Background technique
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges: physics limit, the existing developing technique limit.Under this background, it is
The difficulty that planar flash memory encounters is solved, has most sought lower unit storage unit production cost, a variety of different three-dimensional flash memories are deposited
Reservoir structures are come into being.But the ultimate challenge that three-dimensional storage faces is the storage density for how improving unit area, to reach
To cost more lower than planar flash memory.
Currently, 3D NAND be difficult to realize volume production a main cause be exactly unit area storage density it is not high enough, with
It causes in the cost of unit storage unit and the 1Y NAND product of plane and does not have advantage, it is even higher.3D NAND is come
It says, the method for improving storage density mainly passes through raising stacking number, but not only causes the difficulty of technique by the method
It increases, the reliability requirement for also resulting in product is got higher.
Therefore how technology difficulty is not being improved, and on the basis of not influencing product reliability, is improving depositing for unit area
Storage density becomes the problem of 3D NAND can be realized scale of mass production, replace 2D NAND must overcome.
Summary of the invention
In view of the above problems, the invention discloses a kind of methods for forming 3D nand flash memory, comprising:
Step S1 provides a light shield (mask), and in the light shield, at row's grid line (Gate line, abbreviation GL)
In, it is formed with the vertical hole pattern (Channel hole, abbreviation CH) of predetermined number of rows；
Step S2 provides a substrate, and the substrate surface is formed with stacked structure, and the stacked structure includes that multilayer is handed over
The virtual medium layer and interlayer dielectric layer that mistake stacks, the interlayer dielectric layer are formed between adjacent virtual medium layer；
Step S3 etches the stacked structure to the substrate using the light shield and forms multiple vertical holes, hangs down in described
Straight hole fills polysilicon and forms polysilicon plug (CH Poly Plug)；
Step S4, one layer of oxide of continued growth carry out the first etching technics etching oxide to the stacking and tie
The upper surface of the layer 5 interlayer dielectric layer of structure forms first groove (SL1)；
Step S5 is full of the oxide in the first groove, and carries out the second etching technics and etch the oxidation
Object to the upper surface of the substrate forms second groove (SL2), and the second groove is located at the interposition of adjacent first trenches
It sets；
Step S6 removes the virtual medium layer and forms third groove, and in the second groove and third groove
Fill metal；
Step S7 continues back segment connecting line technics.
The method of above-mentioned formation 3D nand flash memory, wherein the virtual medium layer is silicon nitride.
The method of above-mentioned formation 3D nand flash memory, wherein the interlayer dielectric layer and the oxide are titanium dioxide
Silicon.
The method of above-mentioned formation 3D nand flash memory, wherein the metal is tungsten (W).
The method of above-mentioned formation 3D nand flash memory, wherein first etching technics and second etching technics are equal
For dry etch process.
The method of above-mentioned formation 3D nand flash memory, wherein in the step S5, using the side of atomic layer deposition (ALD)
Method deposition oxide on the stacked structure, and after the oxide for using chemical mechanical grinding (CMP) removal extra,
Form the oxide for being full of the first groove.
The method of above-mentioned formation 3D nand flash memory, wherein the critical size (CD) of the first groove is 90~
110nm。
The method of above-mentioned formation 3D nand flash memory, wherein in the method, the step S6 specifically: utilize digraph
Case photoetching process (DPL) realizes the separation of the metal word lines (Metal Bit Line, abbreviation MBL) of the vertical hole of adjacent two rows,
To achieve the purpose that control respectively.
The method of above-mentioned formation 3D nand flash memory, wherein the predetermined number of rows is 9 rows.
The method of above-mentioned formation 3D nand flash memory, wherein in the step S7, institute is removed using wet-etching technology
It states virtual medium layer and forms third groove.
Foregoing invention is with the following advantages or beneficial effects:
The invention discloses a kind of methods for forming 3D nand flash memory, pass through the excellent of the structure to vertical hole and grid line
Change, may be implemented to be put into the vertical hole pattern of 9 rows in a grid line, then after the completion of vertical hole processing procedure, pass through the first ditch
The etching of slot, to realize the separation of two rows vertical hole, area needed for reducing second groove and OLP (over lap, interval).
Finally by the technique of back segment double patterning etching (DPL), each CH BL (bit line, bit line) in same layer GL SL is realized
Line respectively, effectively to reduce the size of effective storage unit, to pass through optimization under the premise of not increasing technology difficulty
Planar technology structure and back segment connecting line technics, improve equivalent storage area about 35%~40%.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in all the attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the gist of the present invention.
Fig. 1 is the method flow diagram that 3D nand flash memory is formed in the embodiment of the present invention；
Fig. 2 is the structural schematic diagram for the light shield that traditional technology forms vertical hole.
Fig. 3~12 are the flowage structure schematic diagrames that 3D nand flash memory is formed in the embodiment of the present invention.
Specific embodiment
The present invention is further illustrated with specific embodiment with reference to the accompanying drawing, but not as limit of the invention
It is fixed.
As shown in Figure 1, the present embodiment is related to a kind of method for forming 3D nand flash memory, this method specifically includes following step
It is rapid:
Step S1 provides a light shield, and in the light shield, in row's grid line, forms the vertical hole pattern of predetermined number of rows
Shape；Preferably, which is 9 rows, i.e., in the light shield, in row's grid line, forms the vertical hole pattern of 9 rows, such as Fig. 3
Shown in structure.
Fig. 2 is the structural schematic diagram of the existing light shield for forming vertical hole, it is clear that, the light shield institute in the present embodiment
The round mode of the vertical hole of formation more optimizes, and can be very good to save area, improves storage density.
Step S2 provides a substrate 1, forms stacked structure in 1 surface of substrate, which includes multi-layer intercrossed stacking
Virtual medium layer 2 and interlayer dielectric layer 3, in the stacked structure, interlayer dielectric layer 3 is formed in adjacent virtual medium layer 2
Between, the concrete technology due to forming the stacked structure is well known to those skilled in the art, and simultaneously non-present invention is improved heavy
Point, is not just repeated herein, structure as shown in Figure 4.
In a preferred embodiment of the invention, above-mentioned virtual medium layer 2 is silicon nitride.
In a preferred embodiment of the invention, above-mentioned interlayer dielectric layer 3 is silica.
Step S3 forms multiple vertical holes 4 using light shield etching stacked structure to the substrate 1 provided in above-mentioned steps S1,
Structure as shown in Figure 5, and fill polysilicon in multiple vertical holes 4 and form polysilicon plug 5, structure as shown in FIG. 6.
Due in row's grid line, forming the vertical hole pattern of predetermined number of rows, then in the light shield that provides in step sl
In this step S3, using the light shield in row's grid line, the vertical hole 4 of corresponding number of rows is formed.
In an embodiment of the present invention, due in row's grid line, being preferably formed as 9 in the light shield that step S1 is provided
Vertical hole pattern is arranged, then in this step S3, using the light shield in row's grid line, forms 9 row's vertical holes 4.
Step S4, one layer of oxide 6 of continued growth, structure as shown in Figure 7 carry out first time etching technics etching oxidation
Object 6 to the upper surface of stacked structure layer 5 interlayer dielectric layer 3 forms first groove (SL1) 7, structure as shown in Figure 8.
In a preferred embodiment of the invention, above-mentioned oxide 6 is silica, and the thickness of the oxide 6
It is 500 angstroms.
Specifically, carrying out GL later in the top of stacked structure growth one with a thickness of 500 angstroms of silica membrane
The photoetching (photolithography) of SL1 light shield (mask) then carries out first time etching technics using the GL SL1 light shield
Etching silicon dioxide film to the upper surface of stacked structure layer 5 interlayer dielectric layer 3 forms first groove 7.
In a preferred embodiment of the invention, the critical size (CD) of first groove 7 be 90~110nm (such as
90nm, 100nm, 105nm or 110nm etc.).
In a preferred embodiment of the invention, the first etching technics is dry etch process.
Step S5 is full of oxide 8, structure as shown in Figure 9 in first groove 7, and carried out for the second etching technics quarter
It loses oxide 8 to the upper surface of substrate 1 and forms second groove 9 (SL2), and second groove 9 is located at the centre of adjacent first trenches 7
Position, structure as shown in Figure 10.
In an embodiment of the present invention, the oxide 6 in the oxide 8 and above-mentioned steps S4 is preferably oxide of the same race.
In a preferred embodiment of the invention, the second etching technics is dry etch process.
In a preferred embodiment of the invention, in above-mentioned steps S5, using the method for atomic layer deposition (ALD) in institute
Deposition oxide 8 (silica) on stacked structure is stated in first groove 7, and is removed using chemical mechanical grinding (CMP) more
After remaining oxide 8, the oxide 8 for being full of first groove 7 is formed.
Specifically, use the method for atomic layer deposition on first groove 7 deposition thickness for 1500 angstroms of silica
Film, and using chemical mechanical grinding remove with a thickness of 500 angstroms of silica membrane after, formed be full of first groove 7 oxygen
Compound 8.
Step S6, removal virtual medium layer 2 form third groove (SL3), and in first groove 7, second groove 9 and the
Metal 10, structure as shown in figure 11 are filled in three grooves.
In a preferred embodiment of the invention, metal 10 is tungsten (W).
In a preferred embodiment of the invention, third ditch is formed using wet-etching technology removal virtual medium layer 2
Slot.
Step S7 continues back segment connecting line technics.
In a preferred embodiment of the invention, above-mentioned steps S7 specifically: it utilizes double patterning photoetching process (DPL),
The separation of the MBL of the vertical hole 4 of adjacent two rows is realized, to achieve the purpose that control respectively, wherein 11 be first layer metal hole
(Via1, abbreviation V1)；Structure as shown in figure 12 can be fine due to the line width of minimum M2 (Metal2, second metal layer)
Raising storage density.
According to specific experimental data it is found that the spacing (BL of the vertical hole X-direction formed by traditional vertical hole light shield
It pitch) is 196nm, the spacing (GL pitch) of Y-direction is 480nm, and vertical hole CD is 110nm, then effective unit size
(Effective cell Size) is 47040nm2；Wherein, effective unit size=BL pitch*GL pitch/CH；And it adopts
The spacing (pitch) of the vertical hole X-direction formed with the present embodiment is 196nm, and the spacing of Y-direction is 1050nm, vertical hole CD
For 110nm, then effective unit (Effective cell Size)=196*1050/8=25725nm2, it is clear that, this reality
Example is applied by optimization planar technology structure and back segment connecting line technics, improves equivalent storage area about 35%~40%.
The invention discloses a kind of methods for forming 3D nand flash memory, pass through the excellent of the structure to vertical hole and grid line
Change, the figure that may be implemented to be put into 9 row's vertical holes in a grid line passes through first then after the completion of vertical hole processing procedure
The etching of groove, to realize the separation of two rows vertical hole, area needed for reducing second groove and being spaced.Finally by back segment
The technique of double patterning etching, realizes the difference line of each CH BL in same layer GL SL, single effectively to reduce effectively storage
The size of member, to, by optimization planar technology structure and back segment connecting line technics, be improved under the premise of not increasing technology difficulty
Equivalent storage area about 35%~40%.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize change case, this will not be repeated here.Such change case does not affect the essence of the present invention, and it will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (9)
1. a kind of method for forming 3D nand flash memory characterized by comprising
Step S1 provides a light shield, and in the light shield, in row's grid line, is formed with the vertical hole pattern of predetermined number of rows；
Step S2 provides a substrate, and the substrate surface is formed with stacked structure, and the stacked structure includes multi-layer intercrossed heap
Folded virtual medium layer and interlayer dielectric layer, the interlayer dielectric layer are formed between adjacent virtual medium layer；
Step S3 etches the stacked structure to the substrate using the light shield and forms multiple vertical holes, in the vertical hole
It fills polysilicon and forms polysilicon plug；
Step S4, one layer of oxide of continued growth carry out the first etching technics and etch the oxide to the stacked structure
The upper surface of layer 5 interlayer dielectric layer forms first groove；
Step S5 is full of the oxide in the first groove, and carries out the second etching technics and etch the oxide extremely
The upper surface of the substrate forms second groove, and the second groove is located at the middle position of adjacent first trenches；
Step S6 removes the virtual medium layer and forms third groove, and fills out in the second groove and third groove
Fill metal；
Step S7 continues back segment connecting line technics；
Wherein, the predetermined number of rows is 9 rows.
2. forming the method for 3D nand flash memory as described in claim 1, which is characterized in that the virtual medium layer is nitridation
Silicon.
3. forming the method for 3D nand flash memory as described in claim 1, which is characterized in that the interlayer dielectric layer and described
Oxide is silica.
4. forming the method for 3D nand flash memory as described in claim 1, which is characterized in that the metal is tungsten.
5. forming the method for 3D nand flash memory as described in claim 1, which is characterized in that first etching technics and institute
Stating the second etching technics is dry etch process.
6. forming the method for 3D nand flash memory as described in claim 1, which is characterized in that in the step S5, using atom
The method of layer deposition deposits the oxide on the stacked structure, and is removed using chemical mechanical grinding extra described
After oxide, the oxide for being full of the groove is formed.
7. forming the method for 3D nand flash memory as described in claim 1, which is characterized in that the crucial ruler of the first groove
Very little is 90~110nm.
8. forming the method for 3D nand flash memory as described in claim 1, which is characterized in that in the method, the step S7
Specifically: double patterning photoetching process is utilized, the separation of the MBL of the vertical hole of adjacent two rows is realized, to reach the mesh controlled respectively
's.
9. forming the method for 3D nand flash memory as described in claim 1, which is characterized in that in the step S6, using wet process
Etching technics removes the virtual medium layer and forms third groove.
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| CN106910746B (en) | 2017-03-08 | 2018-06-19 | 长江存储科技有限责任公司 | A kind of 3D nand memories part and its manufacturing method, packaging method |
| CN107731846B (en) * | 2017-08-31 | 2019-01-01 | 长江存储科技有限责任公司 | Improve the three-dimensional storage forming method of channel through-hole homogeneity |
| CN107994029B (en) * | 2017-11-16 | 2020-07-21 | 长江存储科技有限责任公司 | Preparation method of 3D NAND flash memory adopting novel trench hole electric connection layer material and flash memory |
| CN107946311B (en) * | 2017-11-21 | 2020-09-25 | 长江存储科技有限责任公司 | Method for controlling critical dimension of channel in 3D NAND flash memory structure |
| CN109065536B (en) * | 2018-08-22 | 2020-04-17 | 长江存储科技有限责任公司 | Wafer and chip |
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| US8829589B2 (en) * | 2010-09-17 | 2014-09-09 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory device |
| KR102108879B1 (en) * | 2013-03-14 | 2020-05-11 | 삼성전자주식회사 | Vertical memory devices and methods of manufacturing the same |
| KR20150061429A (en) * | 2013-11-27 | 2015-06-04 | 삼성전자주식회사 | Vertical memory devices and methods of manufacturing the same |
| KR102128465B1 (en) * | 2014-01-03 | 2020-07-09 | 삼성전자주식회사 | Vertical structure non-volatile memory device |
| CN104157654B (en) * | 2014-08-15 | 2017-06-06 | 中国科学院微电子研究所 | Three-dimensional storage and its manufacture method |
| US9484357B2 (en) * | 2014-12-16 | 2016-11-01 | Sandisk Technologies Llc | Selective blocking dielectric formation in a three-dimensional memory structure |
| CN105810683B (en) * | 2014-12-31 | 2019-05-28 | 上海格易电子有限公司 | A kind of 3D NAND flash memory structure and preparation method thereof |
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Effective date of registration: 20240401 Address after: No. 88, Weilai Third Road, Donghu New Technology Development Zone, Wuhan City, Hubei Province, 430000 Patentee after: YANGTZE MEMORY TECHNOLOGIES Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |