CN107731841A - A kind of method of improvement 3D nand flash memory SEG growth qualities - Google Patents
A kind of method of improvement 3D nand flash memory SEG growth qualities Download PDFInfo
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- CN107731841A CN107731841A CN201710755081.XA CN201710755081A CN107731841A CN 107731841 A CN107731841 A CN 107731841A CN 201710755081 A CN201710755081 A CN 201710755081A CN 107731841 A CN107731841 A CN 107731841A
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- silicon
- nand flash
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- flash memory
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- 230000015654 memory Effects 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000012010 growth Effects 0.000 title claims abstract description 21
- 230000006872 improvement Effects 0.000 title claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000012805 post-processing Methods 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 32
- 239000011229 interlayer Substances 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 6
- 229910002091 carbon monoxide Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 5
- 239000000908 ammonium hydroxide Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000010926 purge Methods 0.000 claims 1
- 230000002349 favourable effect Effects 0.000 abstract description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides the method for improving 3D nand flash memory SEG growth qualities, the described method comprises the following steps：Deposition substrate stacked structure and etched substrate stacked structure are to form the silicon groove of raceway groove and substrate surface；Post processing (Post Etch Treatment, PET) is performed etching to raceway groove and silicon groove；DHF cleanings for the first time are used to remove silicon groove interface oxide；Using NH4OH second is to remove silicon groove interface non-crystalline silicon.The present invention can reduce the heat load of device, and it is favourable to the performance during periphery to reduce heat load, and the pattern of SEG bottoms can be improved, and the pattern for improving SEG bottoms can improve the homogeneity of growing epitaxial silicon height, and then improve the overall performance of 3D nand flash memories.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of SEG of 3D NAND flash memory structures access opening making
Method.
Background technology
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges：Physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty and most ask being produced into for lower unit storage unit that planar flash memory runs into
This, a variety of three-dimensional (3D) flash memories structures are arisen at the historic moment, such as 3D NOR (3D or non-) flash memories and 3D NAND
(3D with non-) flash memory.
Wherein, in the 3D flash memories of NOR-type structure, memory cell is arranged in parallel between bit line and ground wire, and in NAND
In the 3D flash memories of type structure, memory cell tandem between bit line and ground wire arranges.NAND-type flash memory tool with cascaded structure
There is relatively low reading speed, but there is higher writing speed, so as to which NAND-type flash memory is suitable for data storage, its is excellent
Point is that small volume, capacity are big.Flush memory device can be divided into stacked grid type and separate gate type according to the structure of memory cell, and
And floating gate device and silicon-oxide-nitride-oxide (SONO) device are divided into according to the shape of charge storage layer.Its
In, SONO types flush memory device has the reliability more excellent than floating grid polar form flush memory device, and can be performed with relatively low voltage
Programming and erasing operation, and ONOS types flush memory device has very thin unit, and be easy to manufacture.
Generally post processing (Post Etch Treatment, PET) is etched and etches in raceway groove hole in the prior art to carry out afterwards
The selective epitaxial growth (SEG) of silicon, now interface can have oxide (OX) and non-crystalline silicon (a-Si), in the prior art,
Oxide is removed using hydrogen fluoride (HF), and the non-crystalline silicon of interface is removed using a small amount of HCl high-temperature bakings.
However, HCl high-temperature bakings will increase the heat load of device, it is unfavorable to the performance of peripheral devices；Moreover, hydrochloric acid toasts
By etching silicon substrate and change bottom SEG pattern.
The content of the invention
It is an object of the invention to provide a kind of method of improvement 3D nand flash memory SEG growth qualities, this method is by changing
The handling process in silicon groove and raceway groove hole improves SEG growth quality before entering SEG growths, so as to improving the property of 3D nand flash memories
Energy.
To achieve these goals, the present invention proposes a kind of method of improvement 3D nand flash memory SEG growth qualities, wraps
Include following steps：
Deposition substrate stacked structure；
Etched substrate stacked structure is to form the silicon groove of raceway groove and substrate surface；
Post processing (Post Etch Treatment, PET) is performed etching to raceway groove and silicon groove；
Clean for the first time to remove silicon groove interface oxide；
Second of cleaning removes silicon groove interface non-crystalline silicon；
Growing epitaxial silicon.
Further, the deposition substrate stacked structure, specifically, providing substrate, multilayer is formed in the substrate surface
The interlayer dielectric layer and sacrificial dielectric layer being staggeredly stacked, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；Institute
It is oxide skin(coating) to state interlayer dielectric layer, and the sacrificial dielectric layer is silicon nitride layer, so as to form NO stacked structures (NO
Stacks)。
Further, the etched substrate stacked structure, specifically, using anisotropic dry etch process vertically to
To form raceway groove, the raceway groove passes to the substrate and forms the silicon groove of certain depth the lower etching substrate stacked structure.
Further, the etching post processing is, using nitrogen (N2), nitrogen (N2) and carbon monoxide (CO) gaseous mixture
Body or nitrogen (N2) and hydrogen (H2) mixed gas the silicon groove region being etched is purged.
Further, the first time cleaning is using the oxide that interface is removed using diluted hydrofluoric acid (DHF).
Further, second of cleaning is to remove silicon groove interface non-crystalline silicon as using ammonium hydroxide (NH4OH) carry out
Processing.
Further, the growing epitaxial silicon is that new life surface of silicon carries out silicon and is epitaxially-formed silicon at silicon groove
Epitaxial layer (SEG).
Present invention also offers a kind of 3D nand flash memories, and it improves 3D nand flash memory SEG growth qualities by above-mentioned raising
Method be prepared.
The interface of post processing is etched by residual oxide (OX), non-crystalline silicon (a-Si)；Wherein, oxide will cause silicon epitaxy
Layer can not be in its superficial growth, so as to form room；And it is slow in amorphous silicon surfaces, growing silicon epitaxy layer speed, influence silicon epitaxy
The quality of layer, and room may also be formed.And the existing method that non-crystalline silicon is removed using HCl high-temperature bakings easily etches silicon
Substrate
For these reasons, compared with prior art, the beneficial effect for the method that the present invention uses is mainly reflected in：
First, the oxide of residual can be removed with DHF (diluted hydrofluoric acid)；
Second, with ammonium hydroxide (NH4OH non-crystalline silicon) can be removed, but silicon substrate is not caused to damage；
3rd, the heat load of device can be reduced by not using HCl to carry out high-temperature baking, and reduce heat load to during periphery
Performance it is favourable, and the pattern of SEG bottoms can be improved, and the pattern for improving SEG bottoms can improve growing epitaxial silicon height
Homogeneity, and then improve 3D nand flash memories overall performance.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 a-d improve SEG growing height homogeneity method process charts to be a kind of in the present invention.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in accompanying drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expended
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 1 is refer to, in the present embodiment, it is proposed that a kind of method of improvement 3D nand flash memory SEG growth qualities, bag
Include following steps：
S100：Deposition substrate stacked structure；
S200：Etched substrate stacked structure is to form the silicon groove of raceway groove and substrate surface；
S300：Post processing (Post Etch Treatment, PET) is performed etching to raceway groove and silicon groove；
S400：Clean for the first time to remove silicon groove interface oxide；
S500：Second to remove silicon groove interface non-crystalline silicon；
S600：Growing epitaxial silicon.
Specifically, Fig. 1 a are refer to, and in the step s 100, deposition substrate stacked structure, specifically, providing substrate 100, institute
State interlayer dielectric layer 110 and sacrificial dielectric layer 120 of the surface of substrate 100 formed with multi-layer intercrossed stacking, the sacrificial dielectric layer
120 are formed between adjacent interlayer dielectric layer 110；The interlayer dielectric layer 110 is oxide skin(coating), the sacrificial dielectric layer
120 be silicon nitride layer, so as to form NO stacked structures (NO Stacks)；
Please continue to refer to Fig. 1 a, in step s 200, the substrate stacked structure is etched, specifically, using anisotropy
Dry etch process etch the interlayer dielectric layer 110 and sacrificial dielectric layer 120 vertically downward to form raceway groove 130, it is described
Raceway groove 130 passes to the substrate 100 and forms the silicon groove 140 of certain depth.
Please continue to refer to Fig. 1 a, in step S300, post processing (Post Etch are performed etching to raceway groove and silicon groove
Treatment, PET), i.e., using nitrogen (N2), nitrogen (N2) and carbon monoxide (CO) or nitrogen (N2) and hydrogen (H2) to being carved
The silicon groove region of erosion is purged, and non-crystalline silicon 150 and oxide 160 will be produced in silicon rooved face after this processing；
Fig. 1 b are refer to, in step S400, clean the raceway groove 130 and silicon groove 140 for the first time to remove interface oxygen
Compound 160, specifically, carrying out the first time cleaning using diluted hydrofluoric acid (DHF)；
Fig. 1 c are refer to, in step S500, using ammonium hydroxide (NH4OH second of cleaning) is carried out to remove silicon
Groove interface non-crystalline silicon, obtain the silicon groove 170 with newborn Si surfaces；
Fig. 1 d are refer to, in step S600, growing epitaxial silicon, the extension of progress silicon specially at newborn silicon groove 170
Growth forms silicon epitaxy layer 180 (SEG).
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (8)
- A kind of 1. method of improvement 3D nand flash memory SEG growth qualities, it is characterised in that comprise the following steps：Deposition substrate stacked structure；Etched substrate stacked structure is to form the silicon groove of raceway groove and substrate surface；Post processing (Post Etch Treatment, PET) is performed etching to raceway groove and silicon groove；Clean for the first time to remove silicon groove interface oxide；Clean for the second time to remove silicon groove interface non-crystalline silicon；Growing epitaxial silicon.
- 2. improve the method for 3D nand flash memory SEG growth qualities as claimed in claim 1, it is characterised in that the deposition lining Bottom stacked structure, specifically, providing substrate, form the interlayer dielectric layer of multi-layer intercrossed stacking in the substrate surface and sacrifice Jie Matter layer, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；The interlayer dielectric layer is oxide skin(coating), described sacrificial Domestic animal dielectric layer is silicon nitride layer, so as to form NO stacked structures (NO Stacks).
- 3. improve the method for 3D nand flash memory SEG growth qualities as claimed in claim 2, it is characterised in that the etching lining Bottom stacked structure, specifically, using anisotropic dry etch process to etch the substrate stacked structure vertically downward with shape Into raceway groove, the raceway groove passes to the substrate and forms the silicon groove of certain depth.
- 4. improve the method for 3D nand flash memory SEG growth qualities as claimed in claim 1, it is characterised in that after the etching Handle and be, using nitrogen (N2), nitrogen (N2) and carbon monoxide (CO) mixed gas or nitrogen (N2) and hydrogen (H2) mixing Gas purges to the silicon groove region being etched.
- 5. improve the method for 3D nand flash memory SEG growth qualities as claimed in claim 1, it is characterised in that the first time Clean as using the oxide that interface is removed using diluted hydrofluoric acid (DHF).
- 6. improve the method for 3D nand flash memory SEG growth qualities as claimed in claim 1, it is characterised in that described second Cleaning is to remove silicon groove interface non-crystalline silicon as using ammonium hydroxide (NH4OH) handled.
- 7. improve the method for 3D nand flash memory SEG growth qualities as claimed in claim 1, it is characterised in that the silicon epitaxy Growth is that new life surface of silicon carries out silicon and is epitaxially-formed silicon epitaxy layer (SEG) at silicon groove.
- 8. a kind of 3D nand flash memories, it is as the improvement 3D nand flash memory SEG growth qualities described in claim 1-7 any one Method be prepared.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710755081.XA CN107731841A (en) | 2017-08-29 | 2017-08-29 | A kind of method of improvement 3D nand flash memory SEG growth qualities |
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| CN201710755081.XA CN107731841A (en) | 2017-08-29 | 2017-08-29 | A kind of method of improvement 3D nand flash memory SEG growth qualities |
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Cited By (2)
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| CN109216372A (en) * | 2018-09-19 | 2019-01-15 | 长江存储科技有限责任公司 | The forming method of semiconductor structure |
| CN109346470A (en) * | 2018-11-12 | 2019-02-15 | 长江存储科技有限责任公司 | Three-dimensional storage and forming method thereof |
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