CN107611130A - The technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures - Google Patents
The technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures Download PDFInfo
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- CN107611130A CN107611130A CN201710727917.5A CN201710727917A CN107611130A CN 107611130 A CN107611130 A CN 107611130A CN 201710727917 A CN201710727917 A CN 201710727917A CN 107611130 A CN107611130 A CN 107611130A
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Abstract
The present invention provides a kind of technique of growing epitaxial silicon in 3D NAND flash memory structures, including deposition substrate stacked structure；Etched substrate stacked structure is to form the silicon groove of raceway groove and substrate surface；Clean raceway groove and the silicon groove；The high temperature anneal；Growing epitaxial silicon prerinse；Growing epitaxial silicon.Pass through the high temperature anneal, the silicon rooved face damaged to etching aoxidizes, so as to eliminate the polymer residue in trench bottom silicon groove, while can also certain oxidation repair be produced to the surface of the follow-up growing epitaxial silicon destroyed, eliminate interfacial failure and lattice defect；The step of increasing wet-cleaning before the high temperature anneal, the effect of follow-up preferably oxidizing annealing and interface reparation can be obtained；The technique of the present invention can be performed etching effectively to deep trench, and avoid the residual of oxide and etching from destroying the generation of boundary layer, so as to improve the uniformity of growing epitaxial silicon height, and avoided the space of growing epitaxial silicon, improved 3D nand flash memory overall performances.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of 3D NAND flash memory structures and preparation method thereof, especially
It is a kind of technique of growing epitaxial silicon in 3D NAND flash memory structures that can improve growing silicon epitaxy layer quality.
Background technology
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges：Physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty and most ask being produced into for lower unit storage unit that planar flash memory runs into
This, a variety of three-dimensional (3D) flash memories structures are arisen at the historic moment, such as 3D NOR (3D or non-) flash memories and 3D NAND
(3D with non-) flash memory.
Wherein, in the 3D flash memories of NOR-type structure, memory cell is arranged in parallel between bit line and ground wire, and in NAND
In the 3D flash memories of type structure, memory cell tandem between bit line and ground wire arranges.NAND-type flash memory tool with cascaded structure
There is relatively low reading speed, but there is higher writing speed, so as to which NAND-type flash memory is suitable for data storage, its is excellent
Point is that small volume, capacity are big.Flush memory device can be divided into stacked grid type and separate gate type according to the structure of memory cell, and
And floating gate device and silicon-oxide-nitride-oxide (SONO) device are divided into according to the shape of charge storage layer.Its
In, SONO types flush memory device has the reliability more excellent than floating grid polar form flush memory device, and can be performed with relatively low voltage
Programming and erasing operation, and ONOS types flush memory device has very thin unit, and be easy to manufacture.
Specifically, refer to Fig. 1 a-1d, in the prior art in 3D NAND flash memory structures growing epitaxial silicon technique, generally
Employ following method：
S1：Deposition substrate stacked structure, referring to Fig. 1 a, specifically, providing substrate 1, the substrate surface is formed with multilayer
The interlayer dielectric layer 2 and sacrificial dielectric layer 3 being staggeredly stacked, the sacrificial dielectric layer 3 be formed at adjacent interlayer dielectric layer 2 it
Between；The interlayer dielectric layer 2 is oxide skin(coating), and the sacrificial dielectric layer 3 is silicon nitride layer, so as to form NO stacked structures (NO
Stacks)；
S2：Etched substrate stacked structure, referring to Fig. 1 a, specifically, etching the interlayer dielectric layer 2 and sacrificial dielectric layer 3
To form raceway groove 4, the raceway groove 4 passes to the substrate 1 and forms the silicon groove 5 of certain depth；
S3：Post processing (Post Etch Treatment) is performed etching, referring to Fig. 1 b, specifically, using nitrogen (N2)、
Nitrogen (N2) and carbon monoxide (CO) or nitrogen (N2) and hydrogen (H2) the silicon groove region being etched is purged, this etching
The method of post processing, there is more preferable polymer removal effect than common cleaning.
S4：Growing epitaxial silicon prerinse, referring to Fig. 1 c, specifically, using wet-cleaning and/or plasma clean to silicon
Groove region carries out prerinse processing.
S5：Growing epitaxial silicon, referring to Fig. 1 d, silicon is carried out specially at silicon groove 5 is epitaxially-formed silicon epitaxy layer 6
(SEG)。
But in above-mentioned technique, with the stacking number of N/O (Nitride/Oxide) stacked structure in 3D nand flash memories
Mesh is more and more so that logical etching raceway groove is formed in three-dimensional storage and the difficulty of subsequent cleaning is increasing.For
Effective etching forms raceway groove, and etching is often formed at the interface of etch areas and destroys layer 7 (referring to Fig. 1 a), and these are carved
Erosion destroys interfacial failure and lattice defect of layer etc. and can't be repaired in subsequent prerinse step, so as to further influence
The quality of growing epitaxial silicon, such as cause the generation in the highly non-uniform and room 8 (referring to Fig. 1 d) of silicon epitaxy layer.Not only such as
This, deep trench also results in the polymer 9 (referring to Fig. 1 a) for being difficult to effectively remove etching trench bottom residual, so as to also influence outside silicon
The quality of epitaxial growth.And problems above can all influence the preparation of raceway groove and the performance of final 3D nand flash memories.
Therefore, how effectively deep trench to be performed etching, and avoids the residual of oxide and etching from destroying boundary layer
Generation, always by those skilled in the art endeavour research direction.
The content of the invention
It is an object of the invention to provide a kind of preparation method of 3D nand flash memories, can realize for depth trenches
Effectively etching, and avoid the residual of oxide and etching from destroying the generation of boundary layer, so as to improve the property of 3D nand flash memories
Energy.
To achieve these goals, the present invention proposes a kind of technique of growing epitaxial silicon in 3D NAND flash memory structures, bag
Include following steps：
Deposition substrate stacked structure；
Etched substrate stacked structure is to form the silicon groove of raceway groove and substrate surface；
Clean raceway groove and the silicon groove；
The high temperature anneal；
Growing epitaxial silicon prerinse；
Growing epitaxial silicon.
Further, the deposition substrate stacked structure, specifically, providing substrate, multilayer is formed in the substrate surface
The interlayer dielectric layer and sacrificial dielectric layer being staggeredly stacked, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；Institute
It is oxide skin(coating) to state interlayer dielectric layer, and the sacrificial dielectric layer is silicon nitride layer, so as to form NO stacked structures (NO
Stacks)。
Further, the etched substrate stacked structure, specifically, using anisotropic dry etch process vertically to
To form raceway groove, the raceway groove passes to the substrate and forms the silicon groove of certain depth the lower etching substrate stacked structure.
Further, raceway groove and the silicon groove, including etching post processing (Post Etch Treatment) and wet method are cleaned
Cleaning, it is preferred that the etching post processing is, using nitrogen (N2), nitrogen (N2) and carbon monoxide (CO) mixed gas or nitrogen
Gas (N2) and hydrogen (H2) mixed gas the silicon groove region being etched is purged.The method of this etching post processing, than general
Logical cleaning has more preferable polymer removal effect.
Further, the high temperature anneal forms one layer of oxide repair layer in silicon rooved face.
Further, the high temperature anneal is under inertia environmental protection, is handled under conditions of 750-1200 DEG C
60-180 minutes.
Further, the growing epitaxial silicon prerinse, wet-cleaning and/or plasma clean specifically are used.
Further, the growing epitaxial silicon is to carry out silicon at silicon groove to be epitaxially-formed silicon epitaxy layer (SEG).
Present invention also offers a kind of 3D NAND flash memory structures, growing epitaxial silicon in the flash memory structure its by above-mentioned
Technique be prepared.
Compared with prior art, the beneficial effects are mainly as follows：
First, by the high temperature anneal, the silicon rooved face damaged to etching aoxidizes, so as to eliminate raceway groove
Polymer residue in bottom silicon groove, eliminate interfacial failure and lattice defect；
Second, before the high temperature anneal the step of increase wet-cleaning, follow-up more preferable oxidizing annealing can be obtained
The effect repaired with interface；
3rd, by the technique of the present invention, effectively deep trench can be performed etching, and avoid the residual of oxide with
And etching destroys the generation of boundary layer, so as to improve the uniformity of growing epitaxial silicon height, and avoids the space of growing epitaxial silicon,
And then improve the overall performance of 3D nand flash memories.
4th, in subsequent growing epitaxial silicon prerinse step, the high temperature anneal can be readily removed in silicon groove
Surface formed one layer of oxide repair layer so that the repairing effect to silicon rooved face can be played, again will not be to follow-up silicon outside
The interface of epitaxial growth impacts.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 a-d are the process chart of growing epitaxial silicon in 3D nand flash memories in the prior art；
Fig. 2 a-e are the process chart of growing epitaxial silicon in 3D nand flash memories in the present invention.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in accompanying drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expended
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 2 is refer to, in the present embodiment, it is proposed that the technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures, bag
Include following steps：
S100：Deposition substrate stacked structure；
S200：Etched substrate stacked structure is to form the silicon groove of raceway groove and substrate surface；
S300：Clean raceway groove and the silicon groove；
S400：The high temperature anneal；
S500：Growing epitaxial silicon prerinse；
S600：Growing epitaxial silicon.
Specifically, Fig. 2 a are refer to, and in the step s 100, deposition substrate stacked structure, specifically, providing substrate 100, institute
State interlayer dielectric layer 110 and sacrificial dielectric layer 120 of the surface of substrate 100 formed with multi-layer intercrossed stacking, the sacrificial dielectric layer
120 are formed between adjacent interlayer dielectric layer 110；The interlayer dielectric layer 110 is oxide skin(coating), the sacrificial dielectric layer
120 be silicon nitride layer, so as to form NO stacked structures (NO Stacks)；
Please continue to refer to Fig. 2 a, in step s 200, the substrate stacked structure is etched, specifically, using anisotropy
Dry etch process etch the interlayer dielectric layer 110 and sacrificial dielectric layer 120 vertically downward to form raceway groove 130, it is described
Raceway groove 130 passes to the substrate 100 and forms the silicon groove 140 of certain depth.Channel etching can cause to polymerize at silicon groove 140
Thing residual 150 and etching interface destroy layer 160
Fig. 2 b are refer to, in step S300, the raceway groove 130 and silicon groove 140 are cleaned, specifically, carrying out step first
S310, enter etching post processing (Post Etch Treatment), i.e., using nitrogen (N2), nitrogen (N2) and carbon monoxide (CO) or
Nitrogen (N2) and hydrogen (H2) the silicon groove region being etched is purged, the method for this etching post processing, than common cleaning
With more preferable polymer removal effect；Step S320 is then carried out, carries out wet-cleaning, is moved back with obtaining follow-up preferably high temperature
Fiery treatment effect.By cleaning, polymer residue 150 can be removed as far as possible.
Fig. 2 c are refer to, in step S400, the high temperature anneal, to destroy layer to the etching interface on the surface of silicon groove 140
160 carry out oxidation modification, and then form one layer of oxide repair layer 170.Specifically, the high temperature anneal is in N2Or Ar
Inertia environmental protection under, under conditions of 750-1200 DEG C handle 60-180 minutes, can be obtained under such treatment conditions
Obtain optimal repairing effect.
Fig. 2 d are refer to, in step S500, growing epitaxial silicon prerinse, specifically, using wet-cleaning and plasma
Body cleaning carries out prerinse processing to silicon groove region, to obtain clean growing epitaxial silicon interface 180.
Fig. 2 e are refer to, in step S600, growing epitaxial silicon, the epitaxial growth of silicon are carried out specially at silicon groove 140
Form silicon epitaxy layer 190 (SEG).
To sum up, by the high temperature anneal, the silicon rooved face damaged to etching aoxidizes, so as to eliminate raceway groove
Polymer residue in bottom silicon groove, while can also certain oxygen be produced to the surface of the follow-up growing epitaxial silicon destroyed
Change repair, eliminate interfacial failure and lattice defect；The step of increasing wet-cleaning before the high temperature anneal, it can obtain
Obtain the effect of subsequently more preferable oxidizing annealing and interface reparation；By the technique of the present invention, effectively deep trench can be carried out
Etching, and avoid the residual of oxide and etching from destroying the generation of boundary layer, so as to improve the uniform of growing epitaxial silicon height
Property, and the space of growing epitaxial silicon is avoided, and then improve the overall performance of 3D nand flash memories.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (10)
1. the technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures, it is characterised in that comprise the following steps：
Deposition substrate stacked structure；
Etched substrate stacked structure is to form the silicon groove of raceway groove and substrate surface；
Clean raceway groove and the silicon groove；
The high temperature anneal；
Growing epitaxial silicon prerinse；
Growing epitaxial silicon.
2. the technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures according to claim 1, it is characterised in that：
The deposition substrate stacked structure, specifically, providing substrate, the interlayer of multi-layer intercrossed stacking is formed in the substrate surface
Dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；The interlayer dielectric layer is
Oxide skin(coating), the sacrificial dielectric layer are silicon nitride layer, so as to form NO stacked structures (NO Stacks).
3. the technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures according to claim 1, it is characterised in that：
The etched substrate stacked structure, specifically, etching the lining vertically downward using anisotropic dry etch process
To form raceway groove, the raceway groove passes to the substrate and forms the silicon groove of certain depth bottom stacked structure.
4. the technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures according to claim 1, it is characterised in that：
Clean raceway groove and the silicon groove, including etching post processing (Post Etch Treatment) and wet-cleaning.
5. the technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures according to claim 4, it is characterised in that：
The etching post processing is, using nitrogen (N2), nitrogen (N2) and carbon monoxide (CO) mixed gas or nitrogen (N2) and
Hydrogen (H2) mixed gas the silicon groove region being etched is purged.
6. the technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures according to claim 1, it is characterised in that：
The high temperature anneal forms one layer of oxide repair layer in silicon rooved face.
7. the technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures according to claim 6, it is characterised in that：
The high temperature anneal is under inertia environmental protection, and 60-180 minutes are handled under conditions of 750-1200 DEG C.
8. the technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures according to claim 1, it is characterised in that：
The growing epitaxial silicon prerinse, specifically use wet-cleaning and/or plasma clean.
9. the technique of growing epitaxial silicon in a kind of 3D NAND flash memory structures according to claim 1, it is characterised in that：
The growing epitaxial silicon is to carry out silicon at silicon groove to be epitaxially-formed silicon epitaxy layer (SEG).
A kind of 10. 3D NAND flash memory structures, it is characterised in that：Growing epitaxial silicon in the flash memory structure is by claim 1-9
Technique described in any one is prepared.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109148452A (en) * | 2018-09-10 | 2019-01-04 | 长江存储科技有限责任公司 | The forming method of semiconductor structure |
| CN109216372A (en) * | 2018-09-19 | 2019-01-15 | 长江存储科技有限责任公司 | The forming method of semiconductor structure |
| CN111162088A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Manufacturing method of groove in silicon-containing substrate, three-dimensional NAND memory and manufacturing method |
| WO2020102990A1 (en) * | 2018-11-20 | 2020-05-28 | 长江存储科技有限责任公司 | Formation method and annealing device for epitaxial layer and 3d nand memory |
| CN111785729A (en) * | 2020-06-11 | 2020-10-16 | 长江存储科技有限责任公司 | Manufacturing method of three-dimensional memory |
| CN112017953A (en) * | 2020-09-07 | 2020-12-01 | 长江存储科技有限责任公司 | Epitaxial growth method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102945793A (en) * | 2012-12-03 | 2013-02-27 | 上海集成电路研发中心有限公司 | Pre-cleaning method for epitaxial growth of Ge-Si stress layer |
| CN103887176A (en) * | 2014-03-20 | 2014-06-25 | 上海华力微电子有限公司 | Method for reducing source drain epitaxial growth defects |
| US20160056169A1 (en) * | 2014-08-22 | 2016-02-25 | Woong Lee | Semiconductor device, method of fabricating the semiconductor device, and method of forming epitaxial layer |
| US20160118397A1 (en) * | 2014-10-24 | 2016-04-28 | SanDisk Technologies, Inc. | Nand memory strings and methods of fabrication thereof |
-
2017
- 2017-08-23 CN CN201710727917.5A patent/CN107611130A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102945793A (en) * | 2012-12-03 | 2013-02-27 | 上海集成电路研发中心有限公司 | Pre-cleaning method for epitaxial growth of Ge-Si stress layer |
| CN103887176A (en) * | 2014-03-20 | 2014-06-25 | 上海华力微电子有限公司 | Method for reducing source drain epitaxial growth defects |
| US20160056169A1 (en) * | 2014-08-22 | 2016-02-25 | Woong Lee | Semiconductor device, method of fabricating the semiconductor device, and method of forming epitaxial layer |
| US20160118397A1 (en) * | 2014-10-24 | 2016-04-28 | SanDisk Technologies, Inc. | Nand memory strings and methods of fabrication thereof |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109148452A (en) * | 2018-09-10 | 2019-01-04 | 长江存储科技有限责任公司 | The forming method of semiconductor structure |
| CN109216372A (en) * | 2018-09-19 | 2019-01-15 | 长江存储科技有限责任公司 | The forming method of semiconductor structure |
| CN112997272A (en) * | 2018-11-20 | 2021-06-18 | 长江存储科技有限责任公司 | Epitaxial layer and 3D NAND memory forming method and annealing equipment |
| WO2020102990A1 (en) * | 2018-11-20 | 2020-05-28 | 长江存储科技有限责任公司 | Formation method and annealing device for epitaxial layer and 3d nand memory |
| CN112997272B (en) * | 2018-11-20 | 2024-03-29 | 长江存储科技有限责任公司 | Epitaxial layer and forming method and annealing equipment of 3D NAND memory |
| CN111162088A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Manufacturing method of groove in silicon-containing substrate, three-dimensional NAND memory and manufacturing method |
| CN111785729A (en) * | 2020-06-11 | 2020-10-16 | 长江存储科技有限责任公司 | Manufacturing method of three-dimensional memory |
| CN111785729B (en) * | 2020-06-11 | 2021-10-26 | 长江存储科技有限责任公司 | Manufacturing method of three-dimensional memory |
| CN112017953A (en) * | 2020-09-07 | 2020-12-01 | 长江存储科技有限责任公司 | Epitaxial growth method |
| CN112017953B (en) * | 2020-09-07 | 2023-10-24 | 长江存储科技有限责任公司 | Epitaxial growth method |
| CN113257831A (en) * | 2021-05-12 | 2021-08-13 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN113257831B (en) * | 2021-05-12 | 2022-09-23 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN113838857A (en) * | 2021-10-12 | 2021-12-24 | 长江存储科技有限责任公司 | Three-dimensional memory and method for preparing three-dimensional memory |
| CN113838857B (en) * | 2021-10-12 | 2023-12-12 | 长江存储科技有限责任公司 | Three-dimensional memory and method for preparing same |
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Application publication date: 20180119 |