CN112216703A - Manufacturing method of semiconductor structure and semiconductor structure - Google Patents
Manufacturing method of semiconductor structure and semiconductor structure Download PDFInfo
- Publication number
- CN112216703A CN112216703A CN202011079578.2A CN202011079578A CN112216703A CN 112216703 A CN112216703 A CN 112216703A CN 202011079578 A CN202011079578 A CN 202011079578A CN 112216703 A CN112216703 A CN 112216703A
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor
- channel hole
- substrate
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 45
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 36
- 239000007789 gas Substances 0.000 claims description 33
- 235000012239 silicon dioxide Nutrition 0.000 claims description 22
- 239000000377 silicon dioxide Substances 0.000 claims description 22
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000009826 distribution Methods 0.000 abstract description 27
- 230000003071 parasitic effect Effects 0.000 abstract description 16
- 230000002829 reductive effect Effects 0.000 abstract description 9
- 230000015654 memory Effects 0.000 description 11
- 230000008569 process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000036961 partial effect Effects 0.000 description 5
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000010893 electron trap Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Landscapes
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application provides a manufacturing method of a semiconductor structure and the semiconductor structure, wherein the manufacturing method of the semiconductor structure comprises the following steps: forming a substrate structure, wherein the substrate structure comprises a substrate, a stacked structure, an epitaxial layer and a semiconductor filling structure, the stacked structure is positioned on the substrate, the stacked structure comprises a body structure and a channel hole positioned in the body structure, the body structure comprises sacrificial layers and insulating medium layers which are alternately arranged, the epitaxial layer is respectively positioned on the bottom of the channel hole, and the semiconductor filling structure is positioned in the channel hole; etching and removing part of the semiconductor filling structure by adopting an anisotropic etching method to form a groove for accommodating the drain contact structure; and filling the drain contact material in the groove to form a drain contact structure. By adopting the manufacturing method, the groove is formed by the anisotropic etching method, so that the bottom surface of the groove is relatively flat, the influence of parasitic capacitance is reduced, the problem of wider voltage distribution is solved, and the total voltage distribution interval is ensured to be relatively large.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor structure and the semiconductor structure.
Background
In the prior art, a Flash Memory (Flash Memory) has a main function of maintaining stored information for a long time without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, so that the Flash Memory is widely applied to electronic products. To increase the Bit Density (Bit Density) of flash memories and reduce the Bit Cost (Bit Cost), 3D NAND memory architectures are proposed.
A way to further reduce Bit cost is to develop MLC (Multi Level Cell, Multi Level storage), TLC (Trinary Level Cell, 3Bit MLC), and QLC (Quad Level Cell, 4Bit MLC) on the basis of SLC (Single Level Cell, Single Level storage), that is, to implement storage of multiple bits in a Single Cell; taking TLC as an example, there are four voltage distributions, i.e., E, P0, P1, P2, and the sum of the intervals between the four voltage distributions is ESUM (Edge Summary, sum of voltage distribution intervals); in order to ensure that the reliability meets the use requirement, it is necessary to ensure that the four voltage distributions are kept in a small range, and further ensure that the sum of the four voltage distribution intervals is large enough, that is, ensure that the ESUM is large enough.
There is a need for a method that can improve the ESUM of a device.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a method for fabricating a semiconductor structure and a semiconductor structure, so as to solve the problem in the prior art that the reliability of a device is poor due to a small ESUM.
In order to achieve the above object, according to one aspect of the present application, there is provided a method of fabricating a semiconductor structure, including: forming a base structure, wherein the base structure comprises a substrate, a stacked structure, an epitaxial layer and a semiconductor filling structure, the stacked structure is positioned on the substrate, the stacked structure comprises a body structure and a channel hole positioned in the body structure, the body structure comprises sacrificial layers and insulating medium layers which are alternately arranged, the epitaxial layer is respectively positioned on the bottom of the channel hole, and the semiconductor filling structure is positioned in the channel hole; etching and removing part of the semiconductor filling structure by adopting an anisotropic etching method to form a groove for accommodating the drain contact structure; and filling a drain contact material in the groove to form a drain contact structure.
Optionally, the semiconductor filling structure includes a cap layer, and the step of forming a groove for accommodating the drain contact structure by removing a portion of the semiconductor filling structure by anisotropic etching includes: and etching and removing part of the cover layer by adopting an anisotropic etching method, and forming the groove with the plane bottom surface in the channel hole.
Optionally, the cap layer is a silicon dioxide layer, and an anisotropic etching method is used to etch and remove a portion of the cap layer, so as to form the groove with a planar bottom surface in the channel hole, including: and etching and removing part of the silicon dioxide layer by using etching gas containing hydrofluoric acid gas to form the groove.
Optionally, the forming the groove by removing a portion of the silicon dioxide layer by etching using an etching gas including a hydrofluoric acid gas includes: controlling the temperature of the reaction cavity to be between 30 and 120 ℃, and introducing ammonia gas and the hydrofluoric acid gas into the reaction cavity to etch the silicon dioxide layer; controlling the temperature of the reaction cavity between 100 ℃ and 250 ℃, and introducing nitrogen into the reaction cavity.
Optionally, forming a base structure comprising: providing the substrate; forming a preparation stacking structure on the substrate, wherein the preparation stacking structure comprises insulating medium layers and sacrificial layers which are alternately arranged; forming the channel hole exposing the substrate in the preliminary stacked structure; and sequentially forming a gate dielectric layer, a channel layer and a cover layer in the channel hole, wherein the gate dielectric layer, the channel layer and the cover layer form the semiconductor filling structure.
Optionally, after forming the channel hole exposing the substrate in the preliminary stacked structure, before sequentially forming a gate dielectric layer, a channel layer, and a cap layer in the channel hole, the method further includes: and forming an epitaxial layer in the channel hole, wherein the epitaxial layer penetrates through the sacrificial layer closest to the substrate and the two insulating medium layers closest to the substrate.
In order to achieve the above object, according to another aspect of the present application, there is also provided a semiconductor structure, including a base structure, a groove, and a drain contact structure, wherein the base structure includes a substrate, a stack structure, an epitaxial layer, and a semiconductor filling structure, wherein the stack structure is located on the substrate, the stack structure includes a body structure and a channel hole located in the body structure, the body structure includes sacrificial layers and insulating dielectric layers alternately arranged, the epitaxial layer is located on the bottom of the channel hole, respectively, and the semiconductor filling structure is located in the channel hole; the groove is formed in the channel hole and is formed by etching and removing part of the semiconductor filling structure by adopting an anisotropic etching method; the drain contact structure is located in the groove.
Optionally, the bottom surface of the groove is planar.
Optionally, the semiconductor filling structure includes a gate dielectric layer, a channel layer and a cap layer sequentially disposed in the channel hole, and the recess is formed by etching and removing a portion of the cap layer.
Optionally, the capping layer is a silicon dioxide layer.
The manufacturing method comprises the steps of forming a base structure comprising a substrate, sacrificial layers and insulating medium layers which are arranged alternately, a channel hole, an epitaxial layer and a semiconductor filling structure, removing a part of the semiconductor filling structure through etching by an anisotropic etching method, forming a groove for containing a drain contact structure, filling a drain contact material in the groove, and forming the drain contact structure. The groove is formed by an anisotropic etching method, so that the bottom surface of the groove is relatively flat, the parasitic capacitance generated by mutual capacitance of the groove and the drain electrode contact structure is reduced, the problems of wide voltage distribution and small total voltage distribution interval caused by the voltage division of the parasitic capacitance are solved, the total voltage distribution interval is ensured to be large, namely ESUM is large, the reliability of the device is ensured to be good, and the use requirement is met.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 illustrates a flow diagram generated by a method of fabricating a semiconductor structure according to an embodiment of the present application;
FIG. 2 illustrates a partial schematic view of a semiconductor structure during fabrication according to an embodiment of the present application;
FIG. 3 shows a schematic diagram of the structure of FIG. 2 after a cap layer is provided;
FIG. 4 is a schematic diagram illustrating the structure formed after etching a portion of the cap layer shown in FIG. 3;
fig. 5 is a schematic structural diagram illustrating the formation of the groove shown in fig. 4 filled with a drain contact material.
Wherein the figures include the following reference numerals:
100. a substrate; 101. a channel hole; 102. a sacrificial layer; 103. an insulating dielectric layer; 104. an epitaxial layer; 106. a channel layer; 107. a cap layer; 108. a groove; 109. a drain contact structure; 111. a charge blocking layer; 112. an electron trapping layer; 113. a tunneling layer.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background, the problem of poor device reliability caused by the smaller ESUM in the prior art is solved by the present application, which provides a method for fabricating a semiconductor structure and a semiconductor structure.
According to an exemplary embodiment of the present application, as shown in fig. 1 to 5, there is provided a method for fabricating a semiconductor structure, including the steps of:
step S101: forming a base structure, wherein the base structure comprises a substrate 100, a stacked structure, an epitaxial layer 104 and a semiconductor filling structure, the stacked structure is located on the substrate 100, the stacked structure comprises a body structure and a channel hole 101 located in the body structure, the body structure comprises sacrificial layers 102 and insulating medium layers 103 which are alternately arranged, the epitaxial layers 104 are respectively located on the bottoms of the channel holes 101, the semiconductor filling structure is located in the channel hole 101, and fig. 2 is a schematic diagram of a semiconductor structure without the semiconductor filling structure;
step S102: etching and removing part of the semiconductor filling structure by adopting an anisotropic etching method to form a groove 108 for accommodating the drain contact structure;
step S103: the recess 108 is filled with a drain contact material to form a drain contact structure 109, as shown in fig. 5.
According to the manufacturing method of the semiconductor structure, the base structure comprising the substrate, the sacrificial layers and the insulating medium layers which are alternately arranged, the channel holes, the epitaxial layer and the semiconductor filling structure is formed, part of the semiconductor filling structure is removed through etching by an anisotropic etching method, the groove for containing the drain contact structure is formed, and the drain contact material is filled in the groove to form the drain contact structure. The groove is formed by an anisotropic etching method, so that the bottom surface of the groove is relatively flat, the parasitic capacitance generated by mutual capacitance of the groove and the drain electrode contact structure is reduced, the problems of wide voltage distribution and small voltage distribution interval caused by the partial pressure of the parasitic capacitance are solved, the voltage distribution interval sum is large, namely ESUM (electron beam unit) is large, the reliability of the device is good, and the use requirement is met.
In a specific embodiment according to the present application, as shown in fig. 3, the forming of the recess 108 for accommodating the drain contact structure by using the semiconductor filling structure including the cap layer 107 and etching and removing a portion of the semiconductor filling structure by using an anisotropic etching method includes: an anisotropic etching process is used to remove a portion of the cap layer 107, thereby forming the recess 108 having a planar bottom surface in the channel hole 101. And etching part of the cover layer by an anisotropic etching method to form the groove with the plane bottom surface in the channel hole, thereby further relieving the problem that the existing groove with the U-shaped bottom surface generates parasitic capacitance, relieving the problems of larger voltage distribution and smaller sum of voltage distribution intervals caused by the partial pressure influence of the parasitic capacitance, and further ensuring that the sum of the voltage distribution intervals is larger.
In the actual process, a person skilled in the art may determine the corresponding etching gas and the corresponding process parameters according to the specific material of the cap layer, as long as the cap layer can be etched and the groove with the planar bottom surface is formed.
According to another specific embodiment of the present application, the forming of the trench having a planar bottom surface in the channel hole by removing a portion of the capping layer by anisotropic etching includes: and etching and removing part of the silicon dioxide layer by using etching gas containing hydrofluoric acid gas to form the groove. The silicon dioxide layer is etched by the hydrofluoric acid gas through an anisotropic etching method, so that the bottom surface of the groove formed by etching is further ensured to be a plane, the generation of parasitic capacitance is further reduced, and the narrow voltage distribution is further ensured, so that the total sum of voltage distribution intervals is ensured to be larger. Meanwhile, the etching residues of the etching method are all gas, so that the etching method is convenient to remove. According to another embodiment of the present application, the forming the recess by removing a portion of the silicon dioxide layer by etching using an etching gas including a hydrofluoric acid gas includes: controlling the temperature of the reaction cavity to be between 30 and 120 ℃, and introducing ammonia gas and the hydrofluoric acid gas into the reaction cavity to etch the silicon dioxide layer; controlling the temperature of the reaction cavity between 100 ℃ and 250 ℃, and introducing nitrogen into the reaction cavity. The temperature of the reaction cavity is controlled to be between 30 ℃ and 120 ℃, the ammonia gas and the hydrofluoric acid gas are introduced, the hydrofluoric acid gas and the silicon dioxide layer react to form water vapor and silicon tetrafluoride gas, the ammonia gas is used as a catalyst to accelerate the reaction rate, the reaction is a reversible reaction, the forward proceeding of the reaction is guaranteed within the temperature range, and the efficient and rapid formation of the groove is further guaranteed. And then, the temperature of the reaction cavity is controlled to be between 100 and 250 ℃, the nitrogen is introduced and serves as a heat-conducting medium, so that the gas generated after the reaction can be rapidly volatilized, the forward proceeding of the reaction is further accelerated, the concentration of the hydrofluoric acid gas is diluted by adding the nitrogen, and the influence of the hydrofluoric acid gas on the reaction cavity is avoided.
In a specific embodiment, in order to ensure that the etching speed is high and the etching cost is low, the temperature of the reaction chamber is controlled at 105 ℃, and the ammonia gas and the hydrofluoric acid gas are introduced into the reaction chamber. Therefore, the cost is saved while the etching speed and the etching quality are ensured.
In yet another specific embodiment according to the present application, as shown in fig. 3, a base structure is formed comprising: providing the substrate 100 described above; forming a preparation stacking structure on the substrate, wherein the preparation stacking structure comprises insulating medium layers 103 and sacrificial layers 102 which are alternately arranged; forming the channel hole 101 exposing the substrate in the preliminary stacked structure; forming an epitaxial layer 104 in the channel hole, wherein the epitaxial layer 104 penetrates through one sacrificial layer 102 closest to the substrate and two insulating medium layers 103 closest to the substrate; a gate dielectric layer, a channel layer 106 and a cap layer 107 are sequentially formed in the channel hole, and the gate dielectric layer, the channel layer 106 and the cap layer form the semiconductor filling structure. The manufacturing method sequentially forms the gate dielectric layer, the channel layer and the cover layer in the channel hole, provides a structural basis for removing part of the semiconductor filling structure and forming the groove by a subsequent anisotropic etching method, and further ensures the effective formation of the groove, thereby achieving the purpose of eliminating parasitic capacitance.
It should be noted that each step in the above-mentioned embodiment of forming the base structure can be implemented in a feasible manner in the prior art. The substrate in the base structure may be selected according to actual requirements of devices, and may include a silicon substrate, a germanium substrate, a sige substrate, an SOI substrate, or a GOI substrate, and may also be other substrates that are feasible in the prior art.
The insulating dielectric layer and the sacrificial layer may also be made of a material that is conventional in the art, for example, the insulating dielectric layer is a silicon dioxide layer, and the sacrificial layer is a silicon nitride layer. Specifically, the process of etching to form the channel hole may be performed by masking with a hard mask layer.
The gate dielectric layer of the present application may be any gate dielectric layer available in the art, and those skilled in the art may select a suitable gate dielectric layer according to the actual situation. In one embodiment of the present application, as shown in fig. 4, the gate dielectric layer is a stacked structure of oxide-silicon nitride-oxide. Specifically, the gate dielectric layer includes a charge blocking layer 111, an electron trapping layer 112, and a tunneling layer 113 sequentially formed in a direction away from the channel via. The material of each structural layer may also be any feasible material in the prior art, for example, the channel layer may be a polysilicon layer, the insulating dielectric layer may be silicon dioxide, and the drain contact structure is formed of a polysilicon material. Of course, the materials of these structural layers may be replaced by other suitable materials, which will not be described herein.
These structural layers described above may be formed via one or more of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Metal Organic Vapor Phase Epitaxy (MOVPE), Hydride Vapor Phase Epitaxy (HVPE), and/or other well-known crystal growth processes.
In addition, the semiconductor structure in the present application may be a memory or may be a memory cell of a memory.
In another exemplary embodiment of the present application, a semiconductor structure is provided, which is formed using any of the above-described fabrication methods.
The semiconductor structure is formed by any one of the manufacturing methods, and the groove in the channel hole is guaranteed to be formed by an anisotropic etching method, so that the bottom surface of the groove is guaranteed to be smooth, parasitic capacitance generated by the existing U-shaped bottom surface and the drain electrode contact structure is effectively reduced, the distribution of voltage is guaranteed to be narrow, the sum of voltage distribution intervals is guaranteed to be large, and the reliability of the semiconductor structure is guaranteed to be good.
In an embodiment according to the present application, as shown in fig. 4, the semiconductor structure includes a base structure, a recess 108, and a drain contact structure, wherein the base structure includes a substrate 100, a stacked structure, an epitaxial layer 104, and a semiconductor filling structure, the stacked structure is located on the substrate, the stacked structure includes a body structure and a trench hole 101 located in the body structure, the body structure includes sacrificial layers 102 and insulating dielectric layers 103 which are alternately arranged, the epitaxial layers 104 are respectively located on bottoms of the trench holes, and the semiconductor filling structure is located in the trench hole; the groove 108 is formed in the trench hole, and the groove 108 is formed by etching and removing a part of the semiconductor filling structure by using an anisotropic etching method; the drain contact structure is located in the recess 108.
The semiconductor structure comprises the substrate structure, the groove and the drain contact structure, wherein the groove is formed by removing part of the semiconductor filling structure through anisotropic etching, so that the bottom surface of the groove is smooth, the influence of parasitic capacitance generated by mutual capacitance of the groove and the drain contact structure is further reduced, and the semiconductor structure is ensured to have small voltage distribution and large voltage distribution interval sum.
In order to further reduce the influence of parasitic capacitance on the reliability of the semiconductor device, according to another embodiment of the present application, the bottom surface of the groove is a plane. The bottom surface of the groove is a plane, so that the partial pressure influence of parasitic capacitance caused by the fact that the bottom surface of the existing groove is a U-shaped surface is effectively reduced.
In another embodiment of the present application, as shown in fig. 4, the semiconductor filling structure includes a gate dielectric layer, a channel layer 106 and a cap layer 107 sequentially disposed in the channel hole, and the recess 108 is formed by etching and removing a portion of the cap layer 107. The semiconductor structure is formed by sequentially disposing the gate dielectric layer, the channel layer and the cap layer in the channel hole.
It should be noted that each step in the above-mentioned embodiment of forming the base structure can be implemented in a feasible manner in the prior art. The substrate in the base structure may be selected according to actual requirements of devices, and may include a silicon substrate, a germanium substrate, a sige substrate, an SOI substrate, or a GOI substrate, and may also be other substrates that are feasible in the prior art.
The insulating dielectric layer and the sacrificial layer may also be made of a material that is conventional in the art, for example, the insulating dielectric layer is a silicon dioxide layer, and the sacrificial layer is a silicon nitride layer. Specifically, the process of etching to form the channel hole may be performed by masking with a hard mask layer.
The gate dielectric layer of the present application may be any gate dielectric layer available in the art, and those skilled in the art may select a suitable gate dielectric layer according to the actual situation. In one embodiment of the present application, as shown in fig. 4, the gate dielectric layer is a stacked structure of oxide-silicon nitride-oxide. Specifically, the gate dielectric layer includes a charge blocking layer 111, an electron trapping layer 112, and a tunneling layer 113 sequentially formed in a direction away from the channel via. The material of each structural layer may also be any feasible material in the prior art, for example, the channel layer may be a polysilicon layer, the insulating dielectric layer may be silicon dioxide, and the drain contact structure is formed of a polysilicon material. Of course, the materials of these structural layers may be replaced by other suitable materials, which will not be described herein.
These structural layers described above may be formed via one or more of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Metal Organic Vapor Phase Epitaxy (MOVPE), Hydride Vapor Phase Epitaxy (HVPE), and/or other well-known crystal growth processes.
In addition, the semiconductor structure in the present application may be a memory or may be a memory cell of a memory.
In yet another embodiment of the present application, the capping layer is a silicon dioxide layer. And by adopting an anisotropic etching method and introducing the mixed gas of the hydrofluoric acid gas and ammonia gas into the reaction cavity, the hydrofluoric acid gas reacts with the silicon dioxide layer, so that the bottom surface of the formed groove is further ensured to be a plane.
Of course, in practical applications, the cap layer is not limited to the silicon dioxide layer, and may be made of other materials, the etching gas is not limited to the mixed gas of hydrofluoric acid gas and ammonia gas, and may also be other etching gases, and a person skilled in the art may determine the corresponding etching gas and the corresponding process parameters according to the specific material of the cap layer as long as the cap layer can be etched and the groove with the bottom surface being a plane can be formed.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) the manufacturing method forms a base structure comprising a substrate, sacrificial layers and insulating medium layers which are arranged alternately, a channel hole, an epitaxial layer and a semiconductor filling structure, removes part of the semiconductor filling structure through anisotropic etching, forms a groove for containing a drain contact structure, and fills drain contact materials in the groove to form the drain contact structure. The groove is formed by an anisotropic etching method, so that the bottom surface of the groove is relatively flat, the parasitic capacitance generated by mutual capacitance of the groove and the drain electrode contact structure is reduced, the problems of wide voltage distribution and small voltage distribution interval caused by the partial pressure of the parasitic capacitance are solved, the voltage distribution interval sum is large, namely ESUM (electron beam unit) is large, the reliability of the device is good, and the use requirement is met.
2) The application provides a semiconductor structure, the semiconductor structure is formed by adopting any one of the manufacturing methods, and the groove in the channel hole is formed by adopting an anisotropic etching method, so that the bottom surface of the groove is relatively smooth, the parasitic capacitance generated by the existing U-shaped bottom surface and the drain electrode contact structure is effectively reduced, the distribution of voltage is relatively narrow, the sum of voltage distribution intervals is relatively large, and the reliability of the semiconductor structure is relatively good.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
forming a base structure, wherein the base structure comprises a substrate, a stacked structure, an epitaxial layer and a semiconductor filling structure, the stacked structure is positioned on the substrate, the stacked structure comprises a body structure and a channel hole positioned in the body structure, the body structure comprises sacrificial layers and insulating medium layers which are alternately arranged, the epitaxial layer is respectively positioned on the bottom of the channel hole, and the semiconductor filling structure is positioned in the channel hole;
etching and removing part of the semiconductor filling structure by adopting an anisotropic etching method to form a groove for accommodating the drain contact structure;
and filling a drain contact material in the groove to form a drain contact structure.
2. The method of claim 1, wherein the semiconductor fill structure includes a cap layer, and the step of forming a recess for receiving the drain contact structure by removing a portion of the semiconductor fill structure by anisotropic etching comprises:
and etching and removing part of the cover layer by adopting an anisotropic etching method, and forming the groove with the plane bottom surface in the channel hole.
3. The method of claim 2, wherein the cap layer is a silicon dioxide layer,
etching and removing part of the cover layer by adopting an anisotropic etching method, and forming the groove with the plane bottom surface in the channel hole, wherein the method comprises the following steps:
and etching and removing part of the silicon dioxide layer by using etching gas containing hydrofluoric acid gas to form the groove.
4. The method of claim 3, wherein the forming the recess by removing a portion of the silicon dioxide layer by etching using an etching gas comprising hydrofluoric acid gas comprises:
controlling the temperature of the reaction cavity to be between 30 and 120 ℃, and introducing ammonia gas and the hydrofluoric acid gas into the reaction cavity to etch the silicon dioxide layer;
controlling the temperature of the reaction cavity between 100 ℃ and 250 ℃, and introducing nitrogen into the reaction cavity.
5. The method of claim 1, wherein forming a base structure comprises:
providing the substrate;
forming a preparation stacking structure on the substrate, wherein the preparation stacking structure comprises insulating medium layers and sacrificial layers which are alternately arranged;
forming the channel hole exposing the substrate in the preliminary stacked structure;
and sequentially forming a gate dielectric layer, a channel layer and a cover layer in the channel hole, wherein the gate dielectric layer, the channel layer and the cover layer form the semiconductor filling structure.
6. The method of manufacturing according to claim 5, wherein after forming the channel hole exposing the substrate in the preliminary stacked structure, before sequentially forming a gate dielectric layer, a channel layer and a cap layer in the channel hole, the method further comprises:
and forming an epitaxial layer in the channel hole, wherein the epitaxial layer penetrates through the sacrificial layer closest to the substrate and the two insulating medium layers closest to the substrate.
7. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, a stacked structure, an epitaxial layer and a semiconductor filling structure, wherein the stacked structure is positioned on the substrate and comprises a body structure and a channel hole positioned in the body structure, the body structure comprises sacrificial layers and insulating medium layers which are alternately arranged, the epitaxial layer is respectively positioned on the bottom of the channel hole, and the semiconductor filling structure is positioned in the channel hole;
the groove is formed by etching and removing part of the semiconductor filling structure by adopting an anisotropic etching method;
and the drain contact structure is positioned in the groove.
8. The semiconductor structure of claim 7, wherein a bottom surface of the recess is planar.
9. The semiconductor structure of claim 7, wherein the semiconductor filling structure comprises a gate dielectric layer, a channel layer and a cap layer sequentially disposed in the channel hole, and the recess is formed by etching away a portion of the cap layer.
10. The semiconductor structure of claim 9, wherein the capping layer is a silicon dioxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011079578.2A CN112216703A (en) | 2020-10-10 | 2020-10-10 | Manufacturing method of semiconductor structure and semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011079578.2A CN112216703A (en) | 2020-10-10 | 2020-10-10 | Manufacturing method of semiconductor structure and semiconductor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112216703A true CN112216703A (en) | 2021-01-12 |
Family
ID=74054388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011079578.2A Pending CN112216703A (en) | 2020-10-10 | 2020-10-10 | Manufacturing method of semiconductor structure and semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112216703A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101960560A (en) * | 2007-07-12 | 2011-01-26 | 美光科技公司 | Methods of smoothing oxide spacer |
| CN102543672A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for removing natural silicon oxide layer and method for forming self-aligned silicide |
| CN103794503A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of MOS transistor |
| US9728547B1 (en) * | 2016-05-19 | 2017-08-08 | Sandisk Technologies Llc | Three-dimensional memory device with aluminum-containing etch stop layer for backside contact structure and method of making thereof |
| CN107591408A (en) * | 2017-08-23 | 2018-01-16 | 长江存储科技有限责任公司 | A kind of 3D NAND flash memory structures and preparation method thereof |
| CN108886041A (en) * | 2016-02-22 | 2018-11-23 | 桑迪士克科技有限责任公司 | Three dimensional memory device containing discrete silicon nitride charge storage region |
| CN110767659A (en) * | 2019-09-26 | 2020-02-07 | 长江存储科技有限责任公司 | Memory and forming method thereof |
| CN110854019A (en) * | 2019-11-26 | 2020-02-28 | 上海华力集成电路制造有限公司 | Semiconductor manufacturing method |
| CN111183520A (en) * | 2017-11-06 | 2020-05-19 | 桑迪士克科技有限责任公司 | Three-dimensional memory device with annular blocking dielectric and method of fabricating the same |
| CN111466023A (en) * | 2018-09-26 | 2020-07-28 | 桑迪士克科技有限责任公司 | Three-dimensional memory device including three-dimensional bit line discharge transistor and method of fabricating the same |
| CN111587489A (en) * | 2018-12-17 | 2020-08-25 | 桑迪士克科技有限责任公司 | Three-dimensional memory device with stressed vertical semiconductor channel and preparation method thereof |
-
2020
- 2020-10-10 CN CN202011079578.2A patent/CN112216703A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101960560A (en) * | 2007-07-12 | 2011-01-26 | 美光科技公司 | Methods of smoothing oxide spacer |
| CN102543672A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for removing natural silicon oxide layer and method for forming self-aligned silicide |
| CN103794503A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of MOS transistor |
| CN108886041A (en) * | 2016-02-22 | 2018-11-23 | 桑迪士克科技有限责任公司 | Three dimensional memory device containing discrete silicon nitride charge storage region |
| US9728547B1 (en) * | 2016-05-19 | 2017-08-08 | Sandisk Technologies Llc | Three-dimensional memory device with aluminum-containing etch stop layer for backside contact structure and method of making thereof |
| CN107591408A (en) * | 2017-08-23 | 2018-01-16 | 长江存储科技有限责任公司 | A kind of 3D NAND flash memory structures and preparation method thereof |
| CN111183520A (en) * | 2017-11-06 | 2020-05-19 | 桑迪士克科技有限责任公司 | Three-dimensional memory device with annular blocking dielectric and method of fabricating the same |
| CN111466023A (en) * | 2018-09-26 | 2020-07-28 | 桑迪士克科技有限责任公司 | Three-dimensional memory device including three-dimensional bit line discharge transistor and method of fabricating the same |
| CN111587489A (en) * | 2018-12-17 | 2020-08-25 | 桑迪士克科技有限责任公司 | Three-dimensional memory device with stressed vertical semiconductor channel and preparation method thereof |
| CN110767659A (en) * | 2019-09-26 | 2020-02-07 | 长江存储科技有限责任公司 | Memory and forming method thereof |
| CN110854019A (en) * | 2019-11-26 | 2020-02-28 | 上海华力集成电路制造有限公司 | Semiconductor manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6201051B2 (en) | Manufacturing method of semiconductor structure | |
| JP4583910B2 (en) | Transistor of semiconductor device and manufacturing method thereof | |
| US7402493B2 (en) | Method for forming non-volatile memory devices | |
| US7348246B2 (en) | Methods of fabricating non-volatile memory devices including divided charge storage structures | |
| KR20080033100A (en) | Vertical channel memory, manufacturing method thereof and operating method using the same | |
| US10580782B2 (en) | Methods of forming an array of elevationally-extending strings of memory cells individually comprising a programmable charge-storage transistor | |
| US8563441B2 (en) | Methods for fabricating memory cells having fin structures with smooth sidewalls and rounded top corners and edges | |
| CN109411475B (en) | Memory and forming method thereof | |
| CN111627918A (en) | 3D NAND memory and manufacturing method thereof | |
| CN107039446B (en) | Semiconductor structure and forming method thereof | |
| KR100573480B1 (en) | Method of manufacturing a semiconductor device | |
| US7829936B2 (en) | Split charge storage node inner spacer process | |
| CN109256393B (en) | Method for forming memory structure | |
| CN112216703A (en) | Manufacturing method of semiconductor structure and semiconductor structure | |
| US20210398985A1 (en) | Semiconductor structure and method for forming the same | |
| KR100814376B1 (en) | Non-volatile memory device and method of manufacturing the same | |
| US6884680B2 (en) | Method for manufacturing non-volatile memory devices | |
| US20080064165A1 (en) | Dual storage node memory devices and methods for fabricating the same | |
| CN110676325A (en) | Semiconductor structure and manufacturing process thereof | |
| CN113327848B (en) | Flash memory device and method of manufacturing the same | |
| KR100946120B1 (en) | Semiconductor memory device and method for fabricatingthe same | |
| KR100509809B1 (en) | Method for manufacturing sonos type non-volatile memory device | |
| JP4584736B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| US8076712B2 (en) | Semiconductor memory comprising dual charge storage nodes and methods for its fabrication | |
| KR100483438B1 (en) | a method of forming cell of non-volatile memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210112 |