CN116584170A - Three-dimensional memory and forming method thereof - Google Patents

Three-dimensional memory and forming method thereof Download PDF

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Publication number
CN116584170A
CN116584170A CN202180007120.2A CN202180007120A CN116584170A CN 116584170 A CN116584170 A CN 116584170A CN 202180007120 A CN202180007120 A CN 202180007120A CN 116584170 A CN116584170 A CN 116584170A
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China
Prior art keywords
radio frequency
opening
channel hole
etching
layer
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张珍珍
刘隆冬
李明
周颖
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The present disclosure relates to a three-dimensional memory and a method of forming the same. The method for forming the three-dimensional memory comprises the following steps: providing a substrate, wherein the surface of the substrate is provided with a first stacking structure and a connecting layer covering the surface of the first stacking structure; forming an opening penetrating through the connecting layer and a first channel hole penetrating through the first stacking structure, wherein the opening is communicated with the first channel hole; enlarging the feature size of the opening so that the feature size of the bottom of the enlarged opening is larger than the feature size of the top of the first channel hole; and forming a filling layer in the opening and the empty first channel hole.

Description

Three-dimensional memory and forming method thereof
Cross Reference to Related Applications
The present application is based on a chinese patent application having application number 202011546787.3, application date 2020, 12 months and 24 days, application name "three-dimensional memory and method for forming the same", and claims priority from the chinese patent application, the entire contents of which are incorporated herein by reference.
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a three-dimensional memory and a method for forming the same.
Background
With the development of planar flash memories, the production process of semiconductors has made tremendous progress. But in recent years, the development of planar flash memory has met with various challenges: physical limits, current development technology limits, stored electron density limits, and the like. In this context, to address the difficulties encountered with planar flash memories and the pursuit of lower unit cell production costs, various three-dimensional (3D) flash memory structures have been developed, such as 3D NOR flash and 3D NAND flash.
The 3D NAND memory uses the small volume and large capacity as starting points, uses the high integration of stacking the storage units layer by layer in a three-dimensional mode as a design concept, produces the memory with high storage density per unit area and high performance of the storage units, and has become the mainstream technology of the design and production of the emerging memory.
In order to improve the integration level of a three-dimensional memory such as a 3D NAND memory, a three-dimensional memory having a double-layer channel hole structure has been developed. A three-dimensional memory having a dual-layer channel hole structure generally includes a lower channel hole in a lower stack structure and an upper channel hole in an upper stack structure. However, in the process, the prepared three-dimensional memory has larger defects in terms of structure and performance due to the limitation of the upper and lower channel hole process, and the manufacturing flow is complex and the manufacturing cost is high.
Therefore, how to simplify the manufacturing process of the three-dimensional memory, reduce the manufacturing cost of the three-dimensional memory, and improve the performance and the manufacturing yield of the three-dimensional memory is a technical problem to be solved currently.
Disclosure of Invention
The disclosure provides a three-dimensional memory and a forming method thereof, which are used for solving the problems of complex manufacturing process and high manufacturing cost of the three-dimensional memory and improving the performance and the manufacturing yield of the three-dimensional memory.
In order to solve the above problems, the present disclosure provides a method for forming a three-dimensional memory, including the steps of:
providing a substrate, wherein the surface of the substrate is provided with a first stacking structure and a connecting layer covering the surface of the first stacking structure;
forming an opening penetrating through the connecting layer and a first channel hole penetrating through the first stacking structure, wherein the opening is communicated with the first channel hole;
etching by adopting a dry etching process and only etching the connecting layer to enlarge the characteristic size of the opening, so that the characteristic size of the bottom of the enlarged opening is larger than the characteristic size of the top of the first channel hole; the dry etching process at least comprises a first-stage dry etching process and a second-stage dry etching process which adopt different radio frequency powers;
and forming a filling layer in the opening and the empty first channel hole.
In some embodiments of the present disclosure, before enlarging the feature size of the opening, the method further includes the steps of:
and forming an epitaxial semiconductor layer at the bottom of the first channel hole.
In some embodiments of the present disclosure, the specific step of etching only the connection layer by using a dry etching process includes:
performing first-stage dry etching on the connecting layer;
and performing second-stage dry etching on the connecting layer, wherein the radio frequency power adopted by the second-stage dry etching is smaller than that adopted by the first-stage dry etching.
In some embodiments of the present disclosure, the specific step of performing the first-stage dry etching on the connection layer includes:
introducing etching gas under the conditions of a first radio frequency and a first radio frequency power, introducing adjusting gas under the conditions of a second radio frequency and a second radio frequency power, and performing first-stage dry etching on the connecting layer, wherein the first radio frequency is smaller than the second radio frequency, the first radio frequency power is larger than the second radio frequency power, the etching gas is used for etching the connecting layer, and the adjusting gas is used for adjusting the etching rate of the connecting layer etched by the etching gas;
the specific step of performing second-stage dry etching on the connection layer comprises the following steps:
and introducing the etching gas under the conditions of the first radio frequency and the third radio frequency power, introducing the adjusting gas under the conditions of the second radio frequency and the fourth radio frequency power, and performing second-stage dry etching on the connecting layer, wherein the third radio frequency power is smaller than the first radio frequency power, and the fourth radio frequency power is smaller than the second radio frequency power.
In some embodiments of the disclosure, the third radio frequency power is equal to the fourth radio frequency power, and the third radio frequency power and the fourth radio frequency power are both less than the second radio frequency power.
In some embodiments of the present disclosure, the first rf power is 2-5 times the second rf power;
the first radio frequency power is 30-120 times of the third radio frequency power.
In some embodiments of the present disclosure, the first radio frequency is 350KHz to 450KHz, and the second radio frequency is 55MHz to 65MHz;
the first radio frequency power is 17500W-20000W, the second radio frequency power is 4500W-6500W, and the third radio frequency power is 200W-500W.
In some embodiments of the present disclosure, the flow rate of the conditioning gas is greater than the etching gas.
In some embodiments of the present disclosure, the flow rate of the conditioning gas is 20 to 300 times the flow rate of the etching gas.
In some embodiments of the present disclosure, the flow rate of the conditioning gas is 1000sccm to 3000sccm, and the flow rate of the etching gas is 10sccm to 50sccm.
In some embodiments of the present disclosure, the material of the connection layer is an oxide material;
the etching gas is a gas containing carbon element and fluorine element;
the conditioning gas is oxygen.
In some embodiments of the present disclosure, the specific step of forming a filling layer in the opening and in the empty first channel hole includes:
and depositing a filling material in the empty first channel hole and the opening to form the filling layer which fills the first channel hole, the opening and closes the top of the opening.
In some embodiments of the present disclosure, after forming a filling layer in the first channel hole and in the opening, the method further includes the steps of:
forming a second stacking structure on the surface of the connecting layer;
and etching the second stacked structure and part of the filling layer to form a second channel hole penetrating the second stacked structure and extending into the opening, wherein the second channel hole is aligned with the first channel hole, and the residual filling layer in the opening at least covers the whole side wall of the opening.
In order to solve the above-mentioned problems, the present disclosure also provides a three-dimensional memory including:
the substrate is provided with a first stacking structure and a connecting layer covering the surface of the first stacking structure on the surface;
a first channel hole penetrating the first stack structure;
an opening in the connection layer and in communication with the first channel hole, the bottom of the opening having a characteristic dimension greater than the characteristic dimension of the top of the first channel hole;
the three-dimensional memory is formed by performing the method described in any of the embodiments above.
According to the three-dimensional memory and the forming method thereof, after the first channel hole is formed in the first stacking structure by etching and the opening which is communicated with the first channel hole is formed in the connecting layer at the top of the first stacking structure, the characteristic size of the opening in the connecting layer is enlarged, so that the characteristic size of the bottom of the opening after enlargement is larger than that of the top of the first channel hole, on one hand, the width of an alignment window between the subsequent second channel hole and the first channel hole is enlarged, and on the other hand, the side wall of the first channel hole is prevented from being damaged in the subsequent process, and the performance and the manufacturing yield of the three-dimensional memory are effectively improved. In addition, the filling layer is formed by performing a filling process in the first channel hole and the opening only once, so that the manufacturing steps of the three-dimensional memory are greatly simplified, and the manufacturing cost of the three-dimensional memory is reduced.
Drawings
In order to make the above objects, features and advantages of the present disclosure more comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is a flow chart of a method of forming a three-dimensional memory in embodiments of the present disclosure;
FIGS. 2A-2F are schematic cross-sectional views of the main process of forming a three-dimensional memory according to embodiments of the present disclosure;
fig. 3 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present disclosure.
Detailed Description
Specific embodiments of the three-dimensional memory and the method of forming the same provided by the present disclosure are described in detail below with reference to the accompanying drawings.
In the process of forming a three-dimensional memory with a double-layer channel hole, the currently adopted process generally comprises the steps of firstly forming a lower layer stack structure and a connecting layer covering the surface of the lower layer stack structure, and etching the lower layer stack structure and the connecting layer to form a lower channel hole; depositing a first filling layer on the side wall of the lower channel hole and the surface of the connecting layer; then, removing the first filling layer covered on the side wall of the connecting layer and the side wall of the top of the lower channel hole through an etching process, and exposing the connecting layer at the side wall of the lower channel hole; then, removing part of the connecting layer at the top of the lower channel hole through a wet etching process, and forming a groove in the connecting layer; finally, a second filling layer is deposited in the lower channel hole and the groove. Although the width of the alignment window of the subsequent upper channel hole and the subsequent lower channel hole can be increased in the process steps, on one hand, the wet etching process has higher cost and more complicated operation; on the other hand, two deposition processes are required, thereby further increasing the complexity of the manufacturing process. If the trench is not formed in the connection layer by the wet etching process, the misalignment of the upper channel hole and the lower channel hole and the damage of the sidewall of the lower channel hole may be caused in the following steps.
In order to simplify the manufacturing steps of the three-dimensional memory and reduce the manufacturing cost of the three-dimensional memory on the premise of ensuring the alignment of the upper channel hole and the lower channel hole, the embodiment provides a method for forming the three-dimensional memory, fig. 1 is a flowchart of a method for forming the three-dimensional memory in the embodiment of the disclosure, and fig. 2A-2F are schematic cross-sectional views of main processes in the process of forming the three-dimensional memory in the embodiment of the disclosure. The three-dimensional memory described in this embodiment may be, but is not limited to, a 3D NAND memory. As shown in fig. 1 and fig. 2A to fig. 2E, the method for forming a three-dimensional memory according to the present embodiment includes the following steps:
in step S11, a substrate 20 is provided, and the surface of the substrate 20 has a first stacked structure 21 and a connection layer 22 covering the surface of the first stacked structure 21, as shown in fig. 2A.
Specifically, the substrate 20 may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator ), or GOI (Germanium On Insulator, germanium on insulator), or the like. In this embodiment, the substrate 20 may be a silicon substrate for supporting the device structure thereon.
The first stacked structure 21 includes first interlayer insulating layers 211 and first sacrificial layers 212 alternately stacked in a direction in which the substrate 20 points toward the first stacked structure 21 (i.e., a Z-axis direction in fig. 2A). The number of layers in which the first interlayer insulating layer 211 and the first sacrificial layer 212 are alternately stacked may be set as required by those skilled in the art. The greater the number of layers in which the first interlayer insulating layers 211 and the first sacrificial layers 212 are alternately stacked, the greater the degree of integration of the three-dimensional memory formed. A layer of the first sacrificial layer 212 located on top of the first stacked structure 21 is in contact with the connection layer 22. The material of the first interlayer insulating layer 211 may be, but is not limited to, an oxide material, such as silicon dioxide; the material of the first sacrificial layer 212 may be, but is not limited to, a nitride material, such as silicon nitride. In order to facilitate subsequent selective etching, the material of the connection layer 22 and the material of the first sacrificial layer 212 should have a high etching selectivity (e.g., an etching selectivity greater than 3). The material of the connection layer 22 may be, but is not limited to, an oxide material.
In step S12, an opening 24 penetrating the connection layer 22 and a first channel hole 23 of the first stacked structure 21 are formed, and the opening 24 communicates with the first channel hole 23, as shown in fig. 2A.
Specifically, the connection layer 22 and the first stack structure 21 may be etched using a dry etching process or a wet etching process, to form the first channel hole 23 and the opening 24. The first channel hole 23 penetrates the first stacked structure 21 in a direction in which the substrate 20 points toward the first stacked structure 21 (i.e., a Z-axis direction in fig. 2A), the opening 24 penetrates the connection layer 22 in a direction in which the substrate 20 points toward the first stacked structure 21, and the opening 24 communicates with the first channel hole 23.
In step S13, the feature size of the opening 24 is enlarged, so that the feature size of the bottom of the enlarged opening 24 is larger than the feature size of the top of the first channel hole 23, as shown in fig. 2B and 2C, and fig. 2C is a transmission electron microscope image of fig. 2B.
In some embodiments of the present disclosure, before enlarging the feature size of the opening 24, the method further includes the steps of:
an epitaxial semiconductor layer 30 is formed at the bottom of the first channel hole 23.
Specifically, an epitaxial growth process is first used to form the epitaxial semiconductor layer 30 at the bottom of the first channel hole 23, and then a wet oxidation process is used to form an oxide protection layer on the surface of the epitaxial semiconductor layer 30, so as to prevent the epitaxial semiconductor layer 30 from being damaged in the subsequent process.
In some embodiments of the present disclosure, the specific step of expanding the feature size of the opening 24 includes:
the dry etching process is used to etch and only etch the connection layer 22 to enlarge the feature size of the opening 24.
Specifically, the present embodiment etches the connection layer 22 by a dry etching process after forming the first channel hole 23 in the first stack structure 21 and the opening 24 in the connection layer 22 due to complicated operation and high cost of the wet etching process. And, by adjusting parameters of the dry etching process, such as radio frequency, radio frequency power, etc., the connection layer 22 is etched and only etched during the dry etching process. In addition, since the step etches and only etches the connection layer 22 by adjusting the etching parameters, the stacked structure 21 exposed to the sidewall of the first channel hole 23 is not damaged, and thus, a filling material does not need to be deposited in the first channel hole 23 before the step etches the connection layer 22 by using a dry etching process.
In some embodiments of the present disclosure, the specific step of etching and only etching the connection layer 22 by using a dry etching process includes:
performing first-stage dry etching on the connection layer 22;
and performing second-stage dry etching on the connection layer 22, wherein the radio frequency power adopted by the second-stage dry etching is smaller than that adopted by the first-stage dry etching.
In some embodiments of the present disclosure, the specific step of performing the first-stage dry etching on the connection layer 22 includes:
introducing etching gas under the conditions of a first radio frequency and a first radio frequency power, and introducing adjusting gas under the conditions of a second radio frequency and a second radio frequency power, performing first-stage dry etching on the connecting layer 22, wherein the first radio frequency is smaller than the second radio frequency, the first radio frequency power is larger than the second radio frequency power, the etching gas is used for etching the connecting layer 22, and the adjusting gas is used for adjusting the etching rate of the connecting layer etched by the etching gas;
the specific steps of performing the second stage dry etching on the connection layer 22 include:
and introducing the etching gas under the conditions of a first radio frequency and a third radio frequency power, and introducing the adjusting gas under the conditions of a second radio frequency and a fourth radio frequency power, and performing second-stage dry etching on the connection layer 22, wherein the third radio frequency power is smaller than the first radio frequency power, and the fourth radio frequency power is smaller than the second radio frequency power.
Specifically, in enlarging the feature size of the opening 24 in the connection layer 22, a combination of the first-stage dry etching and the second-stage dry etching is adopted. During the first stage dry etching, the connection layer 22 is bombarded with relatively high radio frequency power, thereby controlling the etching depth such that the first stage dry etching process can only etch the connection layer 22. After passing through the first stage dry etching process, the bottom of the opening 24 exposes the first sacrificial layer 212 on top of the first stacked structure 21. Then, the first sacrificial layer 212 on top of the first stacked structure 21 is used as an etching stop layer, and the connection layer 22 is etched with relatively low rf power, so that the feature size of the opening 24 is further increased.
In the process of performing the first-stage dry etching, firstly, etching gas is introduced under the conditions of a first radio frequency and a first radio frequency power, and adjusting gas is introduced under the conditions of a second radio frequency and a second radio frequency power, and the etching rate of the first-stage dry etching is improved and the etching time is saved through the combined action of the etching gas and the adjusting gas. And in the process of performing the second-stage dry etching, the etching gas is introduced under the conditions of the first radio frequency and the third radio frequency power, and the adjusting gas is introduced under the conditions of the second radio frequency and the fourth radio frequency power, so that the etching rate of the second-stage dry etching is improved and the etching time is saved through the combined action of the etching gas and the adjusting gas. The specific type of the etching gas may be selected by those skilled in the art according to the specific material of the connection layer 22. The specific type of conditioning gas may be selected based on the specific type of etching gas and the specific material of the connection layer 22.
The specific values of the third rf power and the fourth rf power may be selected by those skilled in the art according to actual needs. To simplify the operation steps, in some embodiments of the present disclosure, the third rf power is equal to the fourth rf power, and both the third rf power and the fourth rf power are smaller than the second rf power.
In some embodiments of the present disclosure, the first rf power is 2-5 times the second rf power;
the first radio frequency power is 30-120 times of the third radio frequency power.
In some embodiments of the present disclosure, the first radio frequency is 350KHz to 450KHz, and the second radio frequency is 55MHz to 65MHz;
the first radio frequency power is 17500W-20000W, the second radio frequency power is 4500W-6500W, and the third radio frequency power is 200W-500W.
In some embodiments of the present disclosure, the flow rate of the conditioning gas is greater than the etching gas.
In some embodiments of the present disclosure, the flow rate of the conditioning gas is 20 to 300 times the flow rate of the etching gas.
In some embodiments of the present disclosure, the flow rate of the conditioning gas is 1000sccm to 3000sccm, and the flow rate of the etching gas is 10sccm to 50sccm.
In some embodiments of the present disclosure, the material of the connection layer 22 is an oxide material;
the etching gas is a gas containing carbon element and fluorine element;
the conditioning gas is oxygen.
The material of the connection layer 22 is exemplified as an oxide material (e.g., silicon dioxide). The step of etching and only etching the connection layer 22 is performed in two dry etching stages. In the first stage dry etching process, etching gas is continuously introduced under the conditions that the radio frequency is 400KHz and the radio frequency power is 17500W-20000W, adjusting gas is continuously introduced under the conditions that the radio frequency is 60MHz and the radio frequency power is 4500W-6500W, and the connecting layer 22 is etched under the combined action of the etching gas and the adjusting gas; in the second stage dry etching, etching gas is continuously introduced under the conditions that the radio frequency is 400KHz and the radio frequency power is 200W-500W, adjusting gas is continuously introduced under the conditions that the radio frequency is 60MHz and the radio frequency power is 200W-500W, and the connecting layer 22 is etched again under the combined action of the etching gas and the adjusting gas. The total time of the first stage dry etching and the second stage dry etching is greater than 60s. The etching time of the first-stage dry etching is smaller than that of the second-stage dry etching, for example, the etching time of the first-stage dry etching is 5 s-25 s, and the etching time of the second-stage dry etching is 35 s-55 s. The specific values of the etching time of the first stage dry etching and the etching time of the second stage dry etching may be adjusted according to the thickness of the connection layer 22 and the type of the etching gas used. The etching gas adopted by the first-stage dry etching and the second-stage dry etching is CF4, and the adjusting gas adopted by the first-stage dry etching and the second-stage dry etching is O2. In the first stage dry etching and the second stage dry etching, the flow rate of CF4 may be 10sccm to 50sccm, and the flow rate of O2 may be 1000sccm to 3000sccm. By controlling the above etching parameters, the first stage dry etching process and the second stage dry etching process both etch and only etch the connection layer 22, and the stacked structure 21 exposed to the sidewall of the first channel hole 23 is not etched.
The step is to etch and etch the connection layer 22 in a targeted manner, so that the feature size of the opening 24 after expansion is larger than the feature size of the first channel hole 23, not only the width of the alignment window between the second channel hole 28 and the first channel hole 23 formed subsequently is expanded, but also the side wall of the opening 24 after expansion is flat, thereby ensuring good contact between the subsequent and the charge storage layer, and further ensuring good electrical conduction between the first channel hole 23 and the subsequent second channel hole 28.
The particular cross-sectional shape of the enlarged opening 24 may be, but is not limited to, trapezoidal. The feature size of the enlarged bottom of the opening 24 (i.e., the end of the opening 24 contacting the first stacked structure 21) is smaller than the feature size of the top of the opening 24 (i.e., the end opposite to the bottom of the opening 24), and the feature size of the bottom of the opening 24 is larger than the feature size of the top of the first channel hole 23 (i.e., the end of the first channel hole 23 contacting the connection layer 22).
In some embodiments of the present disclosure, a distance between a sidewall of the enlarged opening 24 and a sidewall of the first channel hole 23 on the same side in a radial direction of the first channel hole 23 is 5nm to 6nm.
Specifically, in the X-axis direction in fig. 2B, the distance between the side wall of the opening 24 after enlargement and the side wall of the first channel hole 23 on the same side is 5nm to 6nm, so that alignment of the second channel hole 28 and the first channel hole 23 formed later can be ensured.
In step S14, a filling layer 25 is formed in the opening 24 and the empty first channel hole 23, as shown in fig. 2D.
In some embodiments of the present disclosure, the specific step of forming the filling layer in the opening 24 and the empty first channel hole 23 includes:
a filling material is deposited in the empty first channel hole 23 and in the opening 24, forming the filling layer 25 filling the first channel hole 23, the opening 24 and closing the top of the opening 24.
Specifically, since the first stacked structure 21 exposed to the first channel hole 23 may not be damaged during the expansion of the feature size of the opening 24 by etching by adjusting the etching parameters, the first channel hole 23 does not need to be filled before the expansion of the opening 24. After enlarging the opening 24, the filling layer 25 filling the first channel hole 23, the opening and closing the top of the opening 24 is formed by a one-step filling process, thereby greatly simplifying the manufacturing steps of the three-dimensional memory. The material of the filling layer 25 may be, but is not limited to, a polysilicon material.
In some embodiments of the present disclosure, after forming the filling layer 25 in the first channel hole 23 and the opening 24, the method further includes the following steps:
forming a second stacked structure 26 on the surface of the connection layer 22, as shown in fig. 2E;
the second stacked structure 26 and a portion of the filling layer 25 are etched to form the second channel hole 28 penetrating the second stacked structure 26 and extending into the opening 24, the second channel hole 28 is aligned with the first channel hole 23, and the filling layer 25 remaining in the opening 24 covers at least the entire sidewall of the opening 24, as shown in fig. 2F.
Specifically, the second stacked structure 26 includes second interlayer insulating layers 261 and second sacrificial layers 262 alternately stacked in a direction in which the substrate 20 points toward the first stacked structure 21 (i.e., a Z-axis direction in fig. 2E). The number of layers of the second interlayer insulating layer 261 and the second sacrificial layer 262 alternately stacked may be the same as or different from the number of layers of the first stacked structure 21, and may be set as required by a person skilled in the art. The surface of the second stack 26 is also covered with a cover layer 27. A layer of the second sacrificial layer 262 on top of the second stack 26 is in contact with the cover layer 27. The material of the second interlayer insulating layer 261 may be, but is not limited to, an oxide material, such as silicon dioxide; the material of the second sacrificial layer 262 may be, but is not limited to, a nitride material, such as silicon nitride. The material of the cover layer 27 may be, but is not limited to, an oxide material.
The cover layer 27, the second stacked structure 26 and a portion of the filling layer 25 are etched by an etching process to form the second channel hole 28 penetrating the second stacked structure 26 and extending into the opening 24 in a direction (i.e., a Z-axis direction in fig. 2F) in which the substrate 20 points toward the first stacked structure 21, the position of the second channel hole 28 being aligned with the position of the first channel hole 23. Since the opening 24 is formed in a regular and flat manner, and the feature size of the opening 24 is larger than that of the first trench hole 23, the filling layer 25 remains on the entire surface of the opening 24 during etching the second trench hole 28, so that the sidewall of the first trench hole 23 is not damaged.
Furthermore, the present embodiment also provides a three-dimensional memory, and fig. 3 is a schematic structural diagram of the three-dimensional memory provided in the embodiment of the present disclosure. The three-dimensional memory provided in this embodiment may be formed using the methods shown in fig. 1 and 2A-2F. The three-dimensional memory described in this embodiment may be, but is not limited to, a 3D NAND memory. As shown in fig. 3, the three-dimensional memory provided in this embodiment includes:
a substrate 20, wherein the surface of the substrate 20 is provided with a first stacking structure 21 and a connecting layer 22 covering the surface of the first stacking structure 21;
a first channel hole 23 penetrating the first stack structure 21;
an opening 24 is located in the connection layer 22 and is in communication with the first channel hole 23, and a feature size of a bottom of the opening 24 is larger than a feature size of a top of the first channel hole 23.
According to the three-dimensional memory and the forming method thereof, after the first channel hole is formed in the first stacking structure by etching and the opening penetrating through the first channel hole is formed in the connecting layer at the top of the first stacking structure, the characteristic size of the opening in the connecting layer is enlarged, so that the characteristic size of the bottom of the enlarged opening is larger than the characteristic size of the top of the first channel hole, on one hand, the width of an alignment window between the subsequent second channel hole and the first channel hole is enlarged, on the other hand, the side wall of the first channel hole is prevented from being damaged in the subsequent process, and the performance and the manufacturing yield of the three-dimensional memory are effectively improved. In addition, the filling layer is formed by performing a filling process in the first channel hole and the opening only once, so that the manufacturing steps of the three-dimensional memory are greatly simplified, and the manufacturing cost of the three-dimensional memory is reduced.
The foregoing is merely a few embodiments of the present disclosure and it should be noted that modifications and variations can be made by persons skilled in the art without departing from the principles of the present disclosure, which are also considered to be within the scope of the present disclosure.

Claims (14)

  1. A method of forming a three-dimensional memory, comprising the steps of:
    providing a substrate, wherein the surface of the substrate is provided with a first stacking structure and a connecting layer covering the surface of the first stacking structure;
    forming an opening penetrating through the connecting layer and a first channel hole penetrating through the first stacking structure, wherein the opening is communicated with the first channel hole;
    etching by adopting a dry etching process and only etching the connecting layer to enlarge the characteristic size of the opening, so that the characteristic size of the bottom of the enlarged opening is larger than the characteristic size of the top of the first channel hole; the dry etching process at least comprises a first-stage dry etching process and a second-stage dry etching process which adopt different radio frequency powers;
    and forming a filling layer in the opening and the empty first channel hole.
  2. The method of forming a three-dimensional memory of claim 1, wherein prior to expanding the feature size of the opening, further comprising the steps of:
    and forming an epitaxial semiconductor layer at the bottom of the first channel hole.
  3. The method of forming a three-dimensional memory of claim 2, wherein the specific step of etching only the connection layer using a dry etching process comprises:
    performing first-stage dry etching on the connecting layer;
    and performing second-stage dry etching on the connecting layer, wherein the radio frequency power adopted by the second-stage dry etching is smaller than that adopted by the first-stage dry etching.
  4. The method for forming a three-dimensional memory according to claim 3, wherein the specific step of performing a first-stage dry etching on the connection layer comprises:
    introducing etching gas under the conditions of a first radio frequency and a first radio frequency power, introducing adjusting gas under the conditions of a second radio frequency and a second radio frequency power, and performing first-stage dry etching on the connecting layer, wherein the first radio frequency is smaller than the second radio frequency, the first radio frequency power is larger than the second radio frequency power, the etching gas is used for etching the connecting layer, and the adjusting gas is used for adjusting the etching rate of the connecting layer etched by the etching gas;
    the specific step of performing second-stage dry etching on the connection layer comprises the following steps:
    and introducing the etching gas under the conditions of the first radio frequency and the third radio frequency power, introducing the adjusting gas under the conditions of the second radio frequency and the fourth radio frequency power, and performing second-stage dry etching on the connecting layer, wherein the third radio frequency power is smaller than the first radio frequency power, and the fourth radio frequency power is smaller than the second radio frequency power.
  5. The method of claim 4, wherein the third rf power is equal to the fourth rf power, and the third rf power and the fourth rf power are both less than the second rf power.
  6. The method of claim 4, wherein the first rf power is 2-5 times the second rf power;
    the first radio frequency power is 30-120 times of the third radio frequency power.
  7. The method of forming a three-dimensional memory according to claim 4, wherein the first radio frequency is 350 KHz-450 KHz and the second radio frequency is 55 MHz-65 MHz;
    the first radio frequency power is 17500W-20000W, the second radio frequency power is 4500W-6500W, and the third radio frequency power is 200W-500W.
  8. The method of claim 4, wherein the conditioning gas has a flow rate greater than the etching gas.
  9. The method of claim 4, wherein the flow rate of the conditioning gas is 20 to 300 times the flow rate of the etching gas.
  10. The method of claim 4, wherein the flow rate of the conditioning gas is 1000sccm to 3000sccm and the flow rate of the etching gas is 10sccm to 50sccm.
  11. The method of forming a three-dimensional memory of claim 4, wherein the material of the connection layer is an oxide material;
    the etching gas is a gas containing carbon element and fluorine element;
    the conditioning gas is oxygen.
  12. The method of claim 1, wherein forming a fill layer within the opening and within the empty first trench hole comprises:
    and depositing a filling material in the empty first channel hole and the opening to form the filling layer which fills the first channel hole, the opening and closes the top of the opening.
  13. The method of forming a three-dimensional memory of claim 1, wherein after forming a fill layer within the first channel hole and within the opening, further comprising the steps of:
    forming a second stacking structure on the surface of the connecting layer;
    and etching the second stacked structure and part of the filling layer to form a second channel hole penetrating the second stacked structure and extending into the opening, wherein the second channel hole is aligned with the first channel hole, and the residual filling layer in the opening at least covers the whole side wall of the opening.
  14. A three-dimensional memory formed using the method of forming a three-dimensional memory as recited in any one of claims 1-13, comprising: the substrate is provided with a first stacking structure and a connecting layer covering the surface of the first stacking structure on the surface;
    a first channel hole penetrating the first stack structure;
    and the opening is positioned in the connecting layer and communicated with the first channel hole, and the characteristic dimension of the bottom of the opening is larger than that of the top of the first channel hole.
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