CN112786612A - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
- Publication number
- CN112786612A CN112786612A CN202110062459.4A CN202110062459A CN112786612A CN 112786612 A CN112786612 A CN 112786612A CN 202110062459 A CN202110062459 A CN 202110062459A CN 112786612 A CN112786612 A CN 112786612A
- Authority
- CN
- China
- Prior art keywords
- sub
- layer
- dielectric layer
- channel hole
- sacrificial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 93
- 238000005530 etching Methods 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000000126 substance Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 118
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 28
- 229910052799 carbon Inorganic materials 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 9
- 230000006870 function Effects 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 357
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
- 239000007789 gas Substances 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a three-dimensional memory and a manufacturing method thereof; the method comprises the following steps: providing a first sub-stack structure stacked on a substrate; the first sub-stacking structure comprises a plurality of first dielectric layers and a plurality of second dielectric layers which are arranged at intervals; a first sub-channel hole passes through the first sub-stacking structure; forming a first sacrificial layer in the first sub-channel hole; after the first sacrificial layer is formed, part of the first dielectric layer on the top of the first sub-stacked structure in the side wall of the first sub-channel hole is exposed, and the rest of the first dielectric layers except the first dielectric layer on the top in the first sub-stacked structure are not exposed; performing first etching on the first dielectric layer on the top, and removing part of the first dielectric layer on the top to increase the diameter width corresponding to the exposed side wall part; and when the first etching is carried out, the etching speed of the etching substance to the first dielectric layer is higher than that to the first sacrificial layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a three-dimensional memory.
Background
The three-dimensional memory solves the limitation caused by a two-dimensional or planar flash memory by vertically stacking a plurality of layers of data storage units, supports the accommodation of higher storage capacity in a smaller space, and further effectively reduces the cost and the energy consumption. However, as the number of layers of the vertically stacked data storage units increases, it becomes more and more difficult to form the channel hole at a time by performing deep hole etching in the stacked structure. In practical application, the difficulty of the process for forming the channel hole at one time is reduced by adopting a manufacturing method of sub-channel hole superposition.
The manufacturing method for the sub-channel hole superposition specifically comprises the following steps: and etching the sub-stacking structure at the bottommost layer to form a bottommost sub-channel hole penetrating through the sub-stacking structure at the bottommost layer, and sequentially forming a second sub-stacking structure and a sub-channel hole penetrating through the sub-stacking structure on the sub-stacking structure at the bottommost layer. And sequentially forming a third sub-stacking structure and a sub-channel hole of the third sub-stacking structure on the sub-channel holes of the second sub-stacking structure and the second sub-stacking structure. The above process is repeated until the final stack structure and channel hole are formed. And when the sub-channel holes are superposed, the sub-channel holes in each sub-stack structure are communicated, and all the communicated sub-channel holes form a final channel hole together.
However, when the final channel hole is formed by the related art manufacturing method using sub-channel hole stacking, there is a problem in that alignment between sub-channel holes is difficult.
Disclosure of Invention
In order to solve the related technical problems, embodiments of the present invention provide a three-dimensional memory and a method for manufacturing the same.
The embodiment of the invention provides a method for manufacturing a three-dimensional memory, which comprises the following steps:
providing a first sub-stack structure stacked on a substrate; the first sub-stacking structure comprises a plurality of first dielectric layers and a plurality of second dielectric layers which are arranged at intervals; a first sub-channel hole passes through the first sub-stacking structure;
forming a first sacrificial layer in the first sub-channel hole; after the first sacrificial layer is formed, part of the first dielectric layer on the top of the first sub-stacked structure in the side wall of the first sub-channel hole is exposed, and the other parts of the first dielectric layer except the first dielectric layer on the top in the first sub-stacked structure are not exposed;
performing first etching on the first dielectric layer on the top, and removing part of the first dielectric layer on the top to increase the diameter width corresponding to the exposed side wall part; and when the first etching is carried out, the etching speed of the etching substance to the first dielectric layer is higher than that to the first sacrificial layer.
In the above scheme, the material of the first dielectric layer includes silicon oxide, the material of the second dielectric layer includes silicon nitride, and the material of the first sacrificial layer includes carbon.
In the scheme, wet etching is used in the step of performing first etching on the first dielectric layer on the top; the wet etching is performed using hydrofluoric acid.
In the foregoing aspect, the forming a first sacrificial layer in the first sub-channel hole includes:
filling a first material in the first sub-channel hole to form a first material layer;
and carrying out second etching on the first material layer, and removing part of the first material layer to form the first sacrificial layer.
In the above scheme, the method further comprises:
forming a second sacrificial layer on the first sacrificial layer;
forming a second sub-stack structure and a second sub-channel hole penetrating the second sub-stack structure on the substrate on which the second sacrificial layer is formed; wherein the second sub-channel hole extends into the first sub-channel hole.
In the foregoing solution, the forming a second sacrificial layer on the first sacrificial layer includes:
filling a second material in the first sub-channel hole to form a second material layer on the first sacrificial layer;
polishing the top surface of the second material layer to obtain a second sacrificial layer; wherein a top surface of the second sacrificial layer is flush with a top surface of the first sub-stack structure.
In the above solution, the first sub-stack structure is formed on the front surface of the substrate, and the first material for forming the first sacrificial layer and the second material for forming the second sacrificial layer are attached to both the side surface and the back surface of the substrate;
removing the first material and the second material of the substrate side;
removing the first material and the second material from the back side of the substrate.
In the above scheme, the method further comprises:
removing the first sacrificial layer and the second sacrificial layer;
and forming a storage function layer in the communicated first sub-channel hole and the second sub-channel hole.
In the above scheme, a mask layer for forming a second sub-channel hole exists on the second sub-stacking structure;
the method further comprises the following steps:
and when the mask layer is removed, simultaneously removing the first sacrificial layer and the second sacrificial layer. In the above scheme, a portion of the first dielectric layer on the top of the first sub-stacked structure in the sidewall of the first sub-channel hole is exposed, and a portion of the second dielectric layer in contact with the first dielectric layer on the top is not exposed.
In the foregoing aspect, the forming a first sacrificial layer in the first sub-channel hole includes:
forming the first sacrificial layer in the first sub-channel hole and on top of the first sub-stack structure.
In the above scheme, the substrate further includes a third dielectric layer located on the first sub-stacking structure, and the first sub-channel hole penetrates through the third dielectric layer and the first sub-stacking structure;
the forming of the first sacrificial layer in the first sub-channel hole includes: after the first sacrificial layer is formed, the third dielectric layer and the part of the first dielectric layer in contact with the third dielectric layer in the side wall of the first sub-channel hole are exposed, and the parts of the rest first dielectric layers except the first dielectric layer in contact with the third dielectric layer in the first sub-stacking structure are not exposed;
when the first etching is carried out on the first dielectric layer on the top, the method comprises the following steps: the third dielectric layer is removed at the same time as a portion of the first dielectric layer is removed.
In the above scheme, the material of the third dielectric layer includes silicon nitride.
An embodiment of the present invention further provides a three-dimensional memory, including:
the three-dimensional memory manufactured by the method provided by the embodiment of the invention.
The embodiment of the invention provides a three-dimensional memory and a manufacturing method thereof; the method comprises the following steps: providing a first sub-stack structure stacked on a substrate; the first sub-stacking structure comprises a plurality of first dielectric layers and a plurality of second dielectric layers which are arranged at intervals; a first sub-channel hole passes through the first sub-stacking structure; forming a first sacrificial layer in the first sub-channel hole; after the first sacrificial layer is formed, part of the first dielectric layer on the top of the first sub-stacked structure in the side wall of the first sub-channel hole is exposed, and the other parts of the first dielectric layer except the first dielectric layer on the top in the first sub-stacked structure are not exposed; performing first etching on the first dielectric layer on the top, and removing part of the first dielectric layer on the top to increase the diameter width corresponding to the exposed side wall part; and when the first etching is carried out, the etching speed of the etching substance to the first dielectric layer is higher than that to the first sacrificial layer. In the embodiment of the invention, the final channel hole formed by the manufacturing method of sub-channel hole superposition is adopted, and specifically, after the first sub-channel hole close to the substrate is formed, the top of the first sub-channel hole is subjected to reaming treatment, so that the aligned process window is enlarged when the second sub-channel hole located above the first sub-channel hole is formed subsequently.
Drawings
FIG. 1 is a flow chart illustrating a method for fabricating a three-dimensional memory according to the present invention;
FIGS. 2a-2g are schematic views illustrating a three-dimensional memory manufacturing process according to an embodiment of the invention;
FIGS. 3a-3c are schematic views illustrating a process of fabricating a first sacrificial layer according to an embodiment of the invention;
FIGS. 4a-4c are schematic views illustrating a process of fabricating a second sacrificial layer according to an embodiment of the present invention;
FIGS. 5a-5e are schematic views illustrating the fabrication process of a three-dimensional memory according to another embodiment of the present invention;
fig. 6a-6e are schematic views illustrating a process of manufacturing a three-dimensional memory according to still another embodiment of the invention.
Description of reference numerals:
100-a substrate; 110-a first sub-stack structure; 111-a first dielectric layer; 111 a-the layer of the first dielectric layer on top of the first sub-stack 110; 111 b-the remaining first dielectric layers of the first sub-stack 110 except the top one; 112-a second dielectric layer; 113-a third dielectric layer; 120-a first sub-channel hole; 121-a first material layer; 122-a second material layer; 130-a first sacrificial layer; 140-a second sacrificial layer; 210-a second sub-stack structure; 220-second sub-channel hole.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following describes specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.
In the three-dimensional NAND memory, the memory capacity is increased by adopting a manufacturing method of overlapping sub-channel holes in order to simplify the complexity of the manufacturing process. This presents a problem: how to realize the accurate butt joint among the sub-channel holes of each layer.
In the embodiment of the invention, the final channel hole formed by the manufacturing method of sub-channel hole superposition is adopted, and specifically, after the first sub-channel hole close to the substrate is formed, the top of the first sub-channel hole is subjected to reaming treatment, so that the aligned process window is enlarged when the second sub-channel hole positioned above the first sub-channel hole is formed subsequently.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present invention. As shown in fig. 1, the method comprises the steps of:
step 101: providing a first sub-stack structure stacked on a substrate; the first sub-stacking structure comprises a plurality of first dielectric layers and a plurality of second dielectric layers which are arranged at intervals; a first sub-channel hole passes through the first sub-stacking structure;
step 102: forming a first sacrificial layer in the first sub-channel hole; after the first sacrificial layer is formed, part of the first dielectric layer on the top of the first sub-stacked structure in the side wall of the first sub-channel hole is exposed, and the other parts of the first dielectric layer except the first dielectric layer on the top in the first sub-stacked structure are not exposed;
step 103: performing first etching on the first dielectric layer on the top, and removing part of the first dielectric layer on the top to increase the diameter width corresponding to the exposed side wall part; and when the first etching is carried out, the etching speed of the etching substance to the first dielectric layer is higher than that to the first sacrificial layer.
FIGS. 2a-2g are schematic views illustrating a three-dimensional memory manufacturing process according to an embodiment of the invention. The formation process of the three-dimensional memory of the present embodiment is described below with reference to fig. 2a to 2 g.
In step 101, referring to fig. 2a, a structure is provided that at least includes the first sub-stack structure 110 and the first sub-channel hole 120.
In practical application, before step 101, the method further comprises the steps of:
step 101 a: forming a first sub-stack structure 110 on the substrate 100;
step 101 b: a plurality of first sub-channel holes 120 are formed through the first sub-stacked structure 110.
In step 101a, the substrate 100 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one organic semiconductor material, or other semiconductor materials known in the art.
The first sub-stack structure 110 includes a plurality of first dielectric layers 111 and second dielectric layers 112 arranged at intervals; in this embodiment, a first dielectric layer is located on top of the first sub-stack structure. In practical applications, the first dielectric layer 111 may also be referred to as a dielectric layer, and the material of the first dielectric layer 111 includes, but is not limited to, one or more of a silicon oxide layer and a silicon carbide layer; the second dielectric layer 112 may also be referred to as a dummy gate layer or a sacrificial layer, and the material of the second dielectric layer 112 includes, but is not limited to, one or more of a silicon nitride layer and a silicon oxynitride; in a subsequent process, the second dielectric layer 112 may be removed and filled with a gate material (e.g., metal tungsten (W)) at the removed position, and after the gate material is filled, the corresponding position of the second dielectric layer is referred to as a gate layer (this process is also referred to as a gate last process). In some embodiments, the first dielectric layer 111 may be made of silicon oxide (SiO)2) Forming; the second dielectric layer 112 may be formed of silicon nitride (SiN), thereby forming the first sub-stack structure 110 as a nitride-oxide (NO) stack. In practical applications, the first dielectric Layer 111 and the second dielectric Layer 112 may be formed by a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD); wherein the first dielectric layer 111 and the second dielectric layerThe layers 112 may have the same thickness or different thicknesses.
In step 101b, the first sub-channel hole 120 may be formed by a dry etching process in practical use. In some embodiments, the dry etching may be plasma etching, and the etching gas may be CF4Etc., or other etching gases known in the art that may be used to etch first dielectric layer 111 and second dielectric layer 112.
In practical applications, the method further includes forming an epitaxial layer at the bottom of the first sub-channel hole 120; the epitaxial layer is used for electrically connecting the channel layer in the channel hole with the well region in the substrate. In practical applications, the epitaxial layer may be formed by means of epitaxial growth.
It should be noted that only the case where the structure provided includes one layer of sub-channel holes is described here. In practical applications, the provided structure may further include a plurality of sub-channel holes, and when the number of the sub-channel holes is greater than two, other sub-stack structures and sub-channel holes stacked below the first sub-stack structure 110 and the first sub-channel hole 120 exist.
In step 102, referring to fig. 2b, a first sacrificial layer 130 is formed in the first sub-channel hole 120.
It should be noted that, for clarity and simplicity of description, in the present embodiment, the first dielectric layers 111 generally refer to all the first dielectric layers in the first sub-stack structure 110; the first dielectric layer on top of the first sub-stack structure 110 is defined as 111a, and the remaining first dielectric layers of the first sub-stack structure 110 except the top first dielectric layer are defined as 111 b.
Here, in order to etch only the first dielectric layer 111a located on top of the first sub-stacked structure 110 in the subsequent first etching process, the remaining first dielectric layers 111b of the first sub-stacked structure 110 except the top first dielectric layer are not etched. The height of the first sacrificial layer 130 in the first sub-channel hole 120 needs to satisfy: after the first sacrificial layer 130 is formed, a portion of the sidewall of the first sub-channel hole 120 corresponding to the first dielectric layer 111a on the top of the first sub-stacked structure 110 is exposed, and a portion of the sidewall corresponding to the remaining first dielectric layer 111b except the top first dielectric layer in the first sub-stacked structure is not exposed. It is understood that, when the above height condition is satisfied, the first sacrificial layer 130 may protect the remaining first dielectric layer 111b of the first sub-stack structure 110 except the top first dielectric layer from being etched when the subsequent first etching is performed.
With respect to the height requirement, it is understood that the top surface of the first sacrificial layer 130 may be located at the highest position in the middle of the first dielectric layer 111a on the top of the first sub-stacked structure 110, and the bottom surface of the first sacrificial layer 130 may be located at the bottom of the second dielectric layer below the first dielectric layer 111a on the top of the first sub-stacked structure 110. In an embodiment, a portion of the first dielectric layer 111a on the top of the first sub-stacked structure in the sidewall of the first sub-channel hole 120 is exposed, and a portion of the second dielectric layer 112 in contact with the top first dielectric layer is not exposed. In this embodiment, the top surface of the first sacrificial layer 130 is located at the intersection of the first dielectric layer 111a on the top of the first sub-stacked structure 110 and the second dielectric layer located below the first dielectric layer 111a on the top of the first sub-stacked structure 110.
In practical applications, the method for manufacturing the first sacrificial layer 130 in the implementation of the present invention may include the following steps:
step 102 a: filling a first material in the first sub-channel hole 120 to form a first material layer 121;
step 102 b: and performing second etching on the first material layer 121, and removing a part of the first material layer 121 to form the first sacrificial layer 130.
Fig. 3a-3c are schematic views illustrating a process of fabricating the first sacrificial layer 130 according to an embodiment of the invention. The formation process of the first sacrificial layer 130 of the present embodiment is described below with reference to fig. 3a to 3 c.
First, referring to fig. 3a, fig. 3a shows the structure provided.
Next, in step 102a, referring to fig. 3b, a first material is deposited in the first sub-channel hole 120, forming a first material layer 121. The first material may be deposited by a process such as CVD or ALD. In some embodiments, the first material, i.e., the material of the first sacrificial layer 130, may include carbon or tungsten. Preferably, the first material, i.e., the material of the first sacrificial layer 130, may include carbon.
Next, in step 102b, referring to fig. 3c, a second etching is performed on the first material layer 121, so that the height of the first material layer 121 in the first sub-channel hole satisfies the aforementioned condition, thereby obtaining a first sacrificial layer. During the second etching, the etching speed of the etching substance to the first material layer 121 is greater than the etching speed to the first dielectric layer 111.
In practical applications, the first sacrificial layer 130 may be formed by a dry etching process. In some embodiments, the dry etching may be particularly a plasma etching, wherein the dry etching process is performed at a high temperature using an etching gas containing an oxygen source, more particularly using oxygen in the etching gas.
It should be noted that, in the embodiment of the present invention, the requirement on the stop position of the second etching is higher, and in practical applications, the etching time may be reasonably controlled or the thickness of the first dielectric layer 111a on the top of the first sub-stacked structure 110 and the thickness of the second dielectric layer below the first dielectric layer 111a on the top of the first sub-stacked structure 110 may be appropriately increased (the range of the stop position of the second etching is increased).
In step 103, referring to fig. 2c, the top of the first sub-channel hole 120 is mainly reamed, and other processes are not affected during the reaming process.
In practical application, in order to etch only the first dielectric layer 111a located at the top of the first sub-stacked structure 110 and not etch the remaining first dielectric layers 111b of the first sub-stacked structure 110 except the top first dielectric layer in the subsequent first etching process, it is further required to satisfy: the etching speed of the etching substance to the first dielectric layer 111 is greater than the etching speed to the first sacrificial layer 130. Further, the etching speed of the etching substance on the first dielectric layer 111 is also greater than that on the second dielectric layer 112.
In practical applications, in some embodiments, the material of the first dielectric layer includes silicon oxide, the material of the second dielectric layer includes silicon nitride, and the material of the first sacrificial layer includes carbon.
In practical applications, in some embodiments, when the material of the first dielectric layer comprises silicon oxide, the material of the second dielectric layer comprises silicon nitride, the material of the first sacrificial layer comprises carbon,
wet etching is used in the step of carrying out first etching on the first dielectric layer on the top; the wet etching is performed using hydrofluoric acid.
In practical applications, the hydrofluoric acid may be diluted hydrofluoric acid (DHF).
It should be noted that, during the first etching, an etching substance may etch both the top surface and the side surface of the first dielectric layer 111a at the top of the first sub-stacked structure 110 (where, the side surface is a partial sidewall of the first sub-channel hole), so that, in order to ensure the thickness of the remaining first dielectric layer 111a at the top of the first sub-stacked structure 110 after the etching, the first dielectric layer 111a at the top of the first sub-stacked structure 110 needs to be grown thicker when the provided structure is manufactured, so as to reserve the thickness of the top surface that is etched.
In practical applications, a second stack structure and a second sub-channel hole are formed on the first stack structure 110 in a subsequent process.
Based on this, in an embodiment, the method further comprises:
step a: forming a second sacrificial layer 140 on the first sacrificial layer 130;
step b: forming a second sub-stack structure 210 and a second sub-channel hole 220 passing through the second sub-stack structure 210 on the substrate 100 on which the second sacrificial layer 140 is formed; wherein the second sub-channel hole 220 extends into the first sub-channel hole.
In step a, referring to fig. 2d, a second sacrificial layer 140 is formed on the first sacrificial layer 130, and a top surface of the second sacrificial layer 140 is flush with a top surface of the first stacked structure.
In practical applications, the method for manufacturing the second sacrificial layer 140 in the implementation of the present invention may include the following steps:
step a 1: filling a second material in the first sub-channel hole 120 to form a second material layer 122 on the first sacrificial layer 130;
step a 2: polishing the top surface of the second material layer 122 to obtain a second sacrificial layer 140; wherein a top surface of the second sacrificial layer 140 is flush with a top surface of the first sub-stack structure.
Fig. 4a-4c are schematic views illustrating a process of fabricating the second sacrificial layer 140 according to an embodiment of the invention. The formation process of the second sacrificial layer 140 of the present embodiment is described below with reference to fig. 4a to 4 c.
First, referring to fig. 4a, fig. 4a shows a first trench hole structure after a first etching is performed.
Next, in step a1, referring to fig. 4b, a second material is deposited on the first sacrificial layer 130, forming a second material layer 122. The second material may be deposited by a process such as CVD or ALD. In some embodiments, the second material, i.e., the material of the second sacrificial layer, may be the same as or different from the material of the first material, i.e., the first sacrificial layer. When the second material is the same as the first material, the subsequent removal of the first sacrificial layer 130 and the second sacrificial layer 140 may employ the same process, so that the removal is more concise and convenient. Based on this, the second material may specifically also comprise carbon or tungsten.
Next, in step a2, referring to fig. 4c, the top surface of the second material layer 122 needs to be polished to make the top surface of the second sacrificial layer 140 flush with the surface of the first sub-stacked structure 110. In practical applications, the top surface of the second material layer 122 may be polished by Chemical Mechanical Polishing (CMP).
In step b, referring to fig. 2e, forming a second sub-stacked structure 210 and a plurality of second sub-channel holes 220 passing through the second sub-stacked structure 210; each of the plurality of second sub-channel holes 220 extends into the corresponding first sub-channel hole 120, i.e., is in communication with the corresponding first sub-channel hole 120. In practical applications, the process of forming the second sub-stack structure 210 is similar to the process of forming the first sub-stack structure 110 on the substrate in step 101 a; the process of forming the second sub-channel hole 220 is similar to the process of forming the first sub-channel hole 120 in the first sub-stack structure 110 in step 101b, and is not described herein again. The composition, material, forming process, etc. of the second sub-stacked structure 210 are the same as those of the first sub-stacked structure 110.
In practice, when depositing the first and second materials, there may be some adhesion of the first and second materials to the sides and back of the substrate 100. In order to avoid damage to the side or bottom of the substrate 100 caused by the first and second materials (e.g., when both the first and second materials are carbon), the first and second materials attached to the side and back of the substrate 100 need to be removed.
Based on this, in some embodiments, the first sub-stack structure 110 is formed on the front surface of the substrate 100, and the first material for forming the first sacrificial layer 130 and the second material for forming the second sacrificial layer 140 are attached to both the side surface and the back surface of the substrate 100;
removing the first material and the second material from the side of the substrate 100;
the first material and the second material are removed from the backside of the substrate 100.
Here, the respective materials may include a first material and a second material, such as carbon, attached to the side and the rear of the substrate 100. In practical applications, when removing the corresponding material on the side surface of the substrate 100, the front surface of the substrate 100 may be masked, and then the corresponding material on the side surface of the substrate 100 may be removed by using an etching gas containing an oxygen source.
In practical applications, the substrate 100 is generally disposed on the carrier in a right-side-up direction, so that when the corresponding material on the back side of the substrate 100 is removed, the corresponding material on the back side of the substrate 100 needs to be removed by using an etching gas containing an oxygen source after the substrate 100 is lifted up.
After step b, the method further comprises:
step c: removing the first sacrificial layer 130 and the second sacrificial layer 140;
step d: a storage function layer is formed in the first sub-channel hole 120 and the second sub-channel hole 220 which are communicated.
In step c, referring to fig. 2f, in practical application, when the first sacrificial layer and the second sacrificial layer 140 include carbon, the first sacrificial layer 130 and the second sacrificial layer 140 may be removed by wet etching. Here, the second wet etching may be performed using a developer, for example, tetramethylammonium hydroxide (TMAH).
In practical applications, in some embodiments, a mask layer for forming the second sub-channel hole 220 exists on the second sub-stack structure 210;
the method further comprises the following steps:
when the mask layer is removed, the first sacrificial layer 130 and the second sacrificial layer 140 are simultaneously removed.
Here, it is understood that carbon may also be used as a mask layer for forming the second sub-channel hole 220, and after the second sub-channel hole 220 is formed by using the mask layer, the mask layer needs to be removed, in this case, when the mask layer is removed, the first sacrificial layer 130 and the second sacrificial layer 140 may be removed at the same time, and the removing method may also be the above-mentioned wet etching.
In step d, referring to fig. 2g, in practical applications, a memory function layer is also formed in the connected first sub-channel hole 120 and the second sub-channel hole 220 in a subsequent process. Here, the forming process of the storage function layer specifically includes: along the radial direction of the first sub-channel hole 120 and the second sub-channel hole 220, a blocking layer, a charge trapping layer, a tunneling layer and a channel layer are sequentially formed from outside to inside, wherein the blocking layer covers the surface of the side wall of the first channel hole and the surface of the side wall of the second channel hole, the charge trapping layer covers the surface of the blocking layer, the tunneling layer covers the surface of the charge trapping layer, and the channel layer covers the surface of the tunneling layer to form an ONOP structure, so that a storage unit is formed. The blocking layer is used for blocking the outflow of charges in the storage layer; the charge trapping layer is used for trapping and storing charges; the tunneling layer is used for generating charges; the channel layer is used for supporting.
It can be understood that, when the material of the first dielectric layer is silicon oxide, the material of the second dielectric layer is silicon nitride, the material of the first sacrificial layer is carbon, and the etching substance of the first etching is DHF, the embodiment of the present invention adopts carbon to fill the lower sub-channel hole (the first sub-channel hole), and selectively removes part of unnecessary carbon through deposition and etching steps of the filled carbon, so that the carbon stays at the preset height of the lower sub-channel hole, and then uses the difference of different selection ratios of DHF to carbon, silicon oxide, and silicon nitride to achieve the purpose of reaming the lower sub-channel hole, and finally fills carbon twice to complete full filling of the lower sub-channel hole, thereby effectively reducing the alignment difficulty of the upper sub-channel hole (the first sub-channel hole) and the lower sub-channel hole (the second sub-channel hole).
The manufacturing method of the three-dimensional memory provided by the embodiment of the invention comprises the steps of providing a first sub-stacking structure stacked on a substrate; the first sub-stacking structure comprises a plurality of first dielectric layers and a plurality of second dielectric layers which are arranged at intervals; a first sub-channel hole passes through the first sub-stacking structure; forming a first sacrificial layer in the first sub-channel hole; after the first sacrificial layer is formed, part of the first dielectric layer on the top of the first sub-stacked structure in the side wall of the first sub-channel hole is exposed, and the other parts of the first dielectric layer except the first dielectric layer on the top in the first sub-stacked structure are not exposed; performing first etching on the first dielectric layer on the top, and removing part of the first dielectric layer on the top to increase the diameter width corresponding to the exposed side wall part; and when the first etching is carried out, the etching speed of the etching substance to the first dielectric layer is higher than that to the first sacrificial layer. In the embodiment of the invention, the final channel hole formed by the manufacturing method of sub-channel hole superposition is adopted, and specifically, after the first sub-channel hole close to the substrate is formed, the top of the first sub-channel hole is subjected to reaming treatment, so that the aligned process window is enlarged when the second sub-channel hole located above the first sub-channel hole is formed subsequently.
As mentioned above, the formation method of the first sacrificial layer 130 and the height requirement of the first sacrificial layer 130 in the first sub-channel hole are described. In practical applications, the first sacrificial layer 130 may also be located on top of the first sub-stack structure. Specifically, the method comprises the following steps:
in some embodiments, the forming of the first sacrificial layer 130 in the first sub-channel hole 120 includes:
the first sacrificial layer 130 is formed in the first sub-channel hole 120 and on top of the first sub-stack structure 110.
Here, fig. 5a to 5e are schematic views illustrating a process of manufacturing a three-dimensional memory according to still another embodiment of the present invention. The formation process of the three-dimensional memory of the present embodiment is described below with reference to fig. 5a to 5 e.
First, referring to fig. 5a, fig. 5a shows the structure provided.
Next, referring to fig. 5b, 5c, when the first sacrificial layer 130 is formed, the first sacrificial layer 130 is formed in the first sub-channel hole 120 and on top of the first sub-stacked structure 110. As can be understood in connection with the manufacturing process of the first sacrificial layer 130, when the first sacrificial layer 130 is formed, a first material is filled into the first sub-channel hole 120, and then the filled first material is etched to obtain a first sacrificial layer satisfying a height requirement. In this embodiment, after the first material is etched, some remaining first material (i.e., the first sacrificial layer 130 on the top of the first sub-stacked structure 110) still exists on the top of the first sub-stacked structure 110, and it can be understood that, in the subsequent first etching process, the remaining first material on the top of the first sub-stacked structure 110 can be used to protect the top surface of the first dielectric layer 111a on the top of the first sub-stacked structure 110, so that the thickness of the widened portion in the first sub-channel hole 120 can be ensured, and the first sub-channel hole can be prevented from being damaged by over-etching of the second sub-channel hole.
And, in the subsequent process, the second material is filled to form a second material layer 122 (refer to fig. 5 d). The remaining second material still existing on the top of the first sub-stack structure 110 may be removed at the same time when the second material layer is polished, thereby forming a second sacrificial layer 140 (refer to fig. 5 e). Forming a second sub-stacking structure and a second sub-channel hole on the substrate with the second sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; and forming a storage function layer in the communicated first sub-channel hole and the second sub-channel hole.
In practical applications, a third dielectric layer located on the first sub-stacked structure may be further formed on the substrate, where the third dielectric layer includes silicon nitride, that is, in this embodiment, the top surface of the first sub-stacked structure is a silicon nitride layer, and a next layer of the silicon nitride layer is a silicon oxide layer.
In some embodiments, a third dielectric layer 113 is further formed on the substrate 100 and located on the first sub-stacked structure 110, and the first sub-channel hole passes through the third dielectric layer 113 and the first sub-stacked structure 110;
the forming of the first sacrificial layer 130 in the first sub-channel hole 120 includes: after the first sacrificial layer 130 is formed, the third dielectric layer 113 and a portion of the first dielectric layer 111a in contact with the third dielectric layer 113 in the sidewall of the first sub-channel hole 120 are exposed, and the remaining portions of the first dielectric layer 111b in the first sub-stacked structure 110, except the portion of the first dielectric layer 111a in contact with the third dielectric layer 113, are not exposed;
when the first etching is performed on the first dielectric layer 111a on the top, the method includes: the third dielectric layer 113 is removed at the same time as a portion of the first dielectric layer 111a is removed.
Here, fig. 6a to 6e are schematic views illustrating a process of manufacturing a three-dimensional memory according to still another embodiment of the present invention. The formation process of the three-dimensional memory of the present embodiment is described below with reference to fig. 6a to 6 e.
First, referring to fig. 6a, fig. 6a shows the structure provided.
Next, referring to fig. 6b, in forming the first sacrificial layer 130, in order to etch only the first dielectric layer 111a located on the top of the first sub-stacked structure 110 in the subsequent first etching process, the remaining first dielectric layers 111b of the first sub-stacked structure 110 except the top first dielectric layer are not etched. The height of the first sacrificial layer 130 in the first sub-channel hole 120 needs to satisfy: after the first sacrificial layer 130 is formed, the side wall of the first sub-channel hole 120 is exposed at a portion corresponding to the third dielectric layer 113 and the first dielectric layer 111a below the third dielectric layer 113, and is not exposed at a portion corresponding to the other first dielectric layers 111b of the first sub-stacked structure 110 except the first dielectric layer 111a below the third dielectric layer 113.
Next, referring to fig. 6c, when performing the first etching, since the contact surface between the third dielectric layer 113 and the etching substance is large, when etching the first dielectric layer 111a on the lower layer of the third dielectric layer 113 by using DHF, the third dielectric layer 113 is removed while removing a part of the first dielectric layer 111 a.
Next, referring to fig. 6d, a second material is filled to form a second material layer 122 (refer to fig. 6 d).
Next, referring to fig. 6e, the second material layer is polished to form a second sacrificial layer 140 (refer to fig. 6 e). Forming a second sub-stacking structure and a second sub-channel hole on the substrate with the second sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; and forming a storage function layer in the communicated first sub-channel hole and the second sub-channel hole.
Further, in some embodiments, structures are provided that include: the first sub-stacking structure, a third medium layer positioned on the first sub-stacking structure and a first sub-channel hole penetrating through the third medium layer and the first sub-stacking structure; the first sub-stacking structure comprises a plurality of first dielectric layers and a plurality of second dielectric layers which are arranged at intervals; the material of the first dielectric layer comprises silicon oxide, the material of the second dielectric layer comprises silicon nitride, and the material of the third dielectric layer comprises silicon nitride. At this time, a layer of polysilicon can be deposited in the third dielectric layer and the first sub-channel hole; then, etching the deposited polysilicon, the third dielectric layer and the first dielectric layer at the top of the first sub-stacking structure, and removing part of the polysilicon, part of the third dielectric layer and the first dielectric layer at the top of the first sub-stacking structure so as to increase the diameter width of the top of the first sub-channel hole (the third dielectric layer can protect the top surface of the first dielectric layer at the top of the first sub-stacking structure from being etched); removing the residual third dielectric layer; removing the residual polysilicon; forming a sacrificial layer in the first sub-channel hole by using polycrystalline silicon; forming a second sub-stack structure and a second sub-channel hole on the substrate on which the sacrificial layer is formed; removing the first sacrificial layer and the second sacrificial layer; and forming a storage function layer in the communicated first sub-channel hole and the second sub-channel hole.
It can be understood that the above-mentioned several methods of reaming can simplify the manufacturing process and reduce the cost compared to the method of reaming with polysilicon; specifically, the method comprises the following steps:
1. the sacrificial layer is made of polycrystalline silicon in a mode of reaming by using polycrystalline silicon, deposited polycrystalline silicon and etched polycrystalline silicon are different in gas introduction, and other process conditions such as temperature difference are large, so that the deposited polycrystalline silicon and the etched polycrystalline silicon cannot be finished on the same machine; in the above-mentioned several reaming methods, when the material of the first sacrificial layer is carbon, the deposited carbon and the etched carbon have different gases except the introduced gas, and other process conditions are similar, so that the carbon deposition and the carbon etching can be completed on one machine, and the process flow can be saved;
2. the sacrificial layer is made of polysilicon in a mode of reaming by utilizing the polysilicon, and the polysilicon is removed by utilizing an independent step; in the foregoing several hole-expanding methods, when the material of the first sacrificial layer is carbon, the first sacrificial layer and the mask (the material is also carbon) for forming the second sub-channel hole can be removed together, and no additional step is required to remove carbon, so that the process flow can be saved;
3. the sacrificial layer is made of polycrystalline silicon in a reaming mode by using the polycrystalline silicon, and the side face and the bottom of the substrate can be damaged when the polycrystalline silicon is removed, so that a protective layer is generally formed on the side face and the bottom of the substrate before the polycrystalline silicon is removed; in the foregoing several hole enlarging methods, when the first sacrificial layer is made of carbon, the side and the bottom of the substrate are not damaged when the carbon is removed, so that the process of forming the protective layer can be omitted.
Based on the manufacturing method of the three-dimensional memory, an embodiment of the present invention further provides a three-dimensional memory, where the three-dimensional memory includes:
the three-dimensional memory manufactured by the method provided by the embodiment of the invention.
In practical applications, the three-dimensional memory in the embodiment of the invention may be a three-dimensional NAND-type memory.
It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (14)
1. A method of fabricating a three-dimensional memory, the method comprising:
providing a first sub-stack structure stacked on a substrate; the first sub-stacking structure comprises a first dielectric layer and a second dielectric layer which are arranged at intervals; a first sub-channel hole passes through the first sub-stacking structure;
forming a first sacrificial layer in the first sub-channel hole; after the first sacrificial layer is formed, part of the first dielectric layer on the top of the first sub-stacked structure in the side wall of the first sub-channel hole is exposed, and the other parts of the first dielectric layer except the first dielectric layer on the top in the first sub-stacked structure are not exposed;
performing first etching on the first dielectric layer on the top, and removing part of the first dielectric layer on the top to increase the diameter width corresponding to the exposed side wall part; and when the first etching is carried out, the etching speed of the etching substance to the first dielectric layer is higher than that to the first sacrificial layer.
2. The method of claim 1, wherein the material of the first dielectric layer comprises silicon oxide, the material of the second dielectric layer comprises silicon nitride, and the material of the first sacrificial layer comprises carbon.
3. The method of claim 2, wherein the step of performing the first etching on the top first dielectric layer uses wet etching; the wet etching is performed using hydrofluoric acid.
4. The method of claim 1, wherein the forming a first sacrificial layer in the first sub-channel hole comprises:
filling a first material in the first sub-channel hole to form a first material layer;
and carrying out second etching on the first material layer, and removing part of the first material layer to form the first sacrificial layer.
5. The method of claim 1, further comprising:
forming a second sacrificial layer on the first sacrificial layer;
forming a second sub-stack structure and a second sub-channel hole penetrating the second sub-stack structure on the substrate on which the second sacrificial layer is formed; wherein the second sub-channel hole extends into the first sub-channel hole.
6. The method of claim 5, wherein the forming a second sacrificial layer on the first sacrificial layer comprises:
filling a second material in the first sub-channel hole to form a second material layer on the first sacrificial layer;
polishing the top surface of the second material layer to obtain a second sacrificial layer; wherein a top surface of the second sacrificial layer is flush with a top surface of the first sub-stack structure.
7. The method of claim 5, wherein the first sub-stack structure is formed on a front side of the substrate, and a first material for forming the first sacrificial layer and a second material for forming the second sacrificial layer are attached to both a side and a back side of the substrate;
removing the first material and the second material of the substrate side;
removing the first material and the second material from the back side of the substrate.
8. The method of claim 5, further comprising:
removing the first sacrificial layer and the second sacrificial layer;
and forming a storage function layer in the communicated first sub-channel hole and the second sub-channel hole.
9. The method of claim 8, wherein a mask layer for forming a second sub-channel hole is present on the second sub-stack structure;
the method further comprises the following steps:
and when the mask layer is removed, simultaneously removing the first sacrificial layer and the second sacrificial layer.
10. The method of claim 1, wherein a portion of the first dielectric layer on top of the first sub-stack structure in the sidewalls of the first sub-channel hole is exposed, and a portion of the second dielectric layer in contact with the top first dielectric layer is not exposed.
11. The method of claim 1, wherein the forming a first sacrificial layer in the first sub-channel hole comprises:
forming the first sacrificial layer in the first sub-channel hole and on top of the first sub-stack structure.
12. The method of claim 1, wherein a third dielectric layer is further formed on the substrate and on the first sub-stack structure, and the first sub-channel hole passes through the third dielectric layer and the first sub-stack structure;
the forming of the first sacrificial layer in the first sub-channel hole includes: after the first sacrificial layer is formed, the third dielectric layer and the part of the first dielectric layer in contact with the third dielectric layer in the side wall of the first sub-channel hole are exposed, and the parts of the rest first dielectric layers except the first dielectric layer in contact with the third dielectric layer in the first sub-stacking structure are not exposed;
when the first etching is carried out on the first dielectric layer on the top, the method comprises the following steps: the third dielectric layer is removed at the same time as a portion of the first dielectric layer is removed.
13. The method of claim 12, wherein the material of the third dielectric layer comprises silicon nitride.
14. A three-dimensional memory, comprising:
a three-dimensional memory fabricated by the method of any one of claims 1-13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110062459.4A CN112786612A (en) | 2021-01-18 | 2021-01-18 | Three-dimensional memory and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110062459.4A CN112786612A (en) | 2021-01-18 | 2021-01-18 | Three-dimensional memory and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112786612A true CN112786612A (en) | 2021-05-11 |
Family
ID=75756335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110062459.4A Pending CN112786612A (en) | 2021-01-18 | 2021-01-18 | Three-dimensional memory and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112786612A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113471209A (en) * | 2021-06-28 | 2021-10-01 | 长江存储科技有限责任公司 | Method for preparing three-dimensional memory |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150079743A1 (en) * | 2013-09-17 | 2015-03-19 | SanDisk Technologies, Inc. | Methods of fabricating a three-dimensional non-volatile memory device |
| US20170271261A1 (en) * | 2016-03-16 | 2017-09-21 | Sandisk Technologies Llc | Three-dimensional memory device containing annular etch-stop spacer and method of making thereof |
| CN111162082A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Semiconductor structure, preparation method thereof and three-dimensional memory device |
| CN111430357A (en) * | 2020-04-10 | 2020-07-17 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory |
-
2021
- 2021-01-18 CN CN202110062459.4A patent/CN112786612A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150079743A1 (en) * | 2013-09-17 | 2015-03-19 | SanDisk Technologies, Inc. | Methods of fabricating a three-dimensional non-volatile memory device |
| US20170271261A1 (en) * | 2016-03-16 | 2017-09-21 | Sandisk Technologies Llc | Three-dimensional memory device containing annular etch-stop spacer and method of making thereof |
| CN111162082A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Semiconductor structure, preparation method thereof and three-dimensional memory device |
| CN111430357A (en) * | 2020-04-10 | 2020-07-17 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113471209A (en) * | 2021-06-28 | 2021-10-01 | 长江存储科技有限责任公司 | Method for preparing three-dimensional memory |
| CN113471209B (en) * | 2021-06-28 | 2022-07-05 | 长江存储科技有限责任公司 | Method for preparing three-dimensional memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3286784B1 (en) | Method of making a multilevel memory stack structure using a cavity containing a sacrificial fill material | |
| CN108012567B (en) | Lateral stacks of cobalt and cobalt-semiconductor alloys for control gate electrodes in memory structures | |
| US9978768B2 (en) | Method of making three-dimensional semiconductor memory device having laterally undulating memory films | |
| US10381376B1 (en) | Three-dimensional flat NAND memory device including concave word lines and method of making the same | |
| US10930674B2 (en) | Three-dimensional flat NAND memory device having curved memory elements and methods of making the same | |
| EP3651204B1 (en) | Three-dimensional memory device containing non-epitaxial support pillars in the support openings | |
| US9601508B2 (en) | Blocking oxide in memory opening integration scheme for three-dimensional memory structure | |
| US20200286903A1 (en) | Three-dimensional flat nand memory device having curved memory elements and methods of making the same | |
| US9780034B1 (en) | Three-dimensional memory device containing annular etch-stop spacer and method of making thereof | |
| CN107996001B (en) | Cobalt-containing conductive layer for control gate electrode in memory structure | |
| US9780182B2 (en) | Molybdenum-containing conductive layers for control gate electrodes in a memory structure | |
| CN110211965B (en) | 3D NAND memory and forming method thereof | |
| CN109087916B (en) | Method for forming three-dimensional memory | |
| US10290652B1 (en) | Three-dimensional memory device with graded word lines and methods of making the same | |
| CN109256384B (en) | Through hole structure, preparation method thereof and three-dimensional memory | |
| WO2021225639A1 (en) | Three-dimensional memory device with a dielectric isolation spacer and methods of forming the same | |
| WO2021236168A1 (en) | Three-dimensional memory device including wrap around word lines and methods of forming the same | |
| CN110349967A (en) | A kind of forming method and three-dimensional storage of three-dimensional storage | |
| CN107591407B (en) | A kind of 3D nand memories and its manufacturing method | |
| CN109326600B (en) | Three-dimensional memory device and preparation method thereof | |
| CN111403403B (en) | Three-dimensional memory and method for manufacturing the same | |
| CN112786612A (en) | Three-dimensional memory and manufacturing method thereof | |
| CN111540749B (en) | Three-dimensional memory and forming method thereof | |
| CN112992910B (en) | Three-dimensional memory and preparation method thereof | |
| CN111415942B (en) | Forming method of three-dimensional memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210511 |