CN111146201B - Three-dimensional memory and preparation method thereof - Google Patents
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- CN111146201B CN111146201B CN202010043349.9A CN202010043349A CN111146201B CN 111146201 B CN111146201 B CN 111146201B CN 202010043349 A CN202010043349 A CN 202010043349A CN 111146201 B CN111146201 B CN 111146201B
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- 230000000149 penetrating effect Effects 0.000 claims abstract description 6
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- 229920000642 polymer Polymers 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
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- 229910052710 silicon Inorganic materials 0.000 description 6
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
The invention provides a three-dimensional memory and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor device, wherein the semiconductor device comprises a substrate, a stacking structure and a dielectric layer, the stacking structure and the dielectric layer are positioned on the substrate, the dielectric layer surrounds the stacking structure, a doped well is formed in the substrate, a contact hole penetrating through the dielectric layer is formed in the dielectric layer, the contact hole exposes the doped well, and the depth of the doped well is smaller than a preset depth; forming a protective layer on the semiconductor device to expose the contact hole; and etching the bottom of the doped well by taking the protective layer as a mask so as to enable the depth of the etched doped well to be more than or equal to the preset depth. The invention solves the technical problems that the doped well positioned at the periphery of the stacked structure is generally shallow, and impurities are usually formed in the doped well, so that the electrical property of the three-dimensional memory, such as the properties of reading, writing, programming or erasing, is influenced.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a three-dimensional memory and a preparation method thereof.
Background
Charge trapping three-dimensional memories (CTMs) are the mainstream structures of flash memories due to their high storage density, high stability and mature fabrication processes.
The three-dimensional memory is formed with a doped well on a substrate, wherein the doped well at the periphery of the stacked structure is generally shallow, and impurities are generally formed in the doped well, thereby affecting the electrical performance of the three-dimensional memory, such as reading, writing, programming or erasing.
Disclosure of Invention
The invention aims to provide a three-dimensional memory and a preparation method thereof, which aim to solve the technical problems that the electrical performance of the three-dimensional memory, such as reading, writing, programming or erasing, is influenced because a doped well positioned at the periphery of a stacked structure is generally shallow and impurities are usually formed in the doped well.
The invention provides a preparation method of a three-dimensional memory, which comprises the following steps:
providing a semiconductor device, wherein the semiconductor device comprises a substrate, a stacking structure and a dielectric layer, the stacking structure and the dielectric layer are positioned on the substrate, the dielectric layer surrounds the stacking structure, a doped well is formed in the substrate, a contact hole penetrating through the dielectric layer is formed in the dielectric layer, the contact hole exposes the doped well, and the depth of the doped well is smaller than a preset depth;
forming a protective layer on the semiconductor device to expose the contact hole;
and etching the bottom of the doped well by taking the protective layer as a mask so as to enable the depth of the etched doped well to be more than or equal to the preset depth.
A channel structure extending in a direction perpendicular to the substrate is formed in the stacked structure, and a first through hole exposing the top of the stacked structure is formed at the top end of the semiconductor device;
the forming method of the protective layer is deposition, and the first through hole is filled with the protective layer when the protective layer is deposited.
And the protective layer covers the top side wall of the contact hole when the protective layer is deposited.
The stacked structure comprises a step part and a core part, the step part is positioned at the edge of the stacked structure, and the first through hole is formed in the core part;
the stacked structure comprises gate layers and insulating layers which are alternately stacked;
the semiconductor device further comprises a plurality of second through holes penetrating through the step part and the dielectric layer, and the plurality of second through holes respectively expose the gate layers of different layers;
and exposing the second through hole by the protective layer when the protective layer is deposited.
And when the protective layer is deposited, the protective layer covers the top end side wall of the second through hole.
Wherein the aperture of the second through hole is larger than the aperture of the first through hole, and the preparation method further comprises:
and controlling the forming time of the protective layer so that the protective layer fills the first through hole and covers the top side wall of the second through hole.
And etching the doped trap by adopting chlorine-based gas.
And the depth difference between the etched doped trap and the etched doped trap is more than or equal to 40 nm.
Wherein, the material of the protective layer is polymer.
The invention provides a three-dimensional memory which is prepared by the preparation method.
To sum up, this application is through forming the polymer protective layer on semiconductor device to the polymer protective layer deepens as the further sculpture of mask to the doping well, makes the degree of depth of doping well reach and predetermines the degree of depth, and when other conducting structure were formed in the doping well in later stage, because the doping well is darker, can make the conducting structure who forms in the doping well contact well with the substrate well, and electric conductivity is good, has improved the electrical property of three-dimensional memory, and performance such as reading and writing, programming or erasing are all better.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1-2 are schematic structural views of a three-dimensional memory fabricated by a conventional fabrication method.
Fig. 3 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of the structure of fig. 3 for preparing a protective layer.
Fig. 5 is a schematic diagram of the structure of the etched doped well of fig. 3.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Before describing the embodiments of the present invention, the structure of the conventional three-dimensional memory 100 will be briefly described.
Referring to fig. 1, a semiconductor device 10 is first formed in a conventional three-dimensional memory 100, where the semiconductor device includes a substrate 101, a stack structure 106b on the substrate 101, and a dielectric layer 105c, the dielectric layer 105c surrounds the stack structure 106b, a doped well 101a is formed in the substrate 101, a contact hole 20 is formed in the dielectric layer and penetrates through the dielectric layer 105c, the contact hole 20 exposes the doped well 101a, and a depth of the doped well 101a is smaller than a predetermined depth. Furthermore, an impurity a, such as amorphous silicon, is usually formed in the doped well 101a, and the presence of the impurity a makes the depth of the doped well 101a smaller, which affects the electrical performance of the three-dimensional memory 100, such as the performance of reading, writing, programming or erasing.
Based on the above problems, the present invention provides a method for manufacturing a three-dimensional memory. Referring to fig. 3, fig. 3 is a method for manufacturing a three-dimensional memory according to the present invention. According to the three-dimensional memory 100, the polymer protection layer 30 is formed on the semiconductor device 10, the polymer protection layer 30 is used as a mask to further deepen the etching of the doped well 101a, the depth of the doped well 101a reaches the preset depth, and when a conductive structure is formed in the doped well 101a in the later period, the conductive structure formed in the doped well 101a can be well contacted with the substrate 101 due to the fact that the doped well 101a is deep, the conductivity is good, the electrical performance of the three-dimensional memory 100 is improved, and the performances such as reading, writing, programming or erasing are good.
The method of fabricating the three-dimensional memory is shown in fig. 3. As shown in fig. 3, the method can be broadly summarized as the following process: providing a semiconductor device 10(S1), forming a protective layer 30 exposing the contact hole 20 on the semiconductor device 10 (S2), and etching the bottom of the doped well 101a by using the protective layer as a mask so that the depth of the etched doped well 101a is greater than or equal to a preset depth (S3). As will be described separately below.
Referring to FIG. 3, the method first performs operations S1-S3:
s1, with continuing reference to fig. 1, a semiconductor device 10 is provided, which includes a substrate 101, a stack structure 106b on the substrate 101, and a dielectric layer 105c, the dielectric layer 105c surrounds the stack structure 106b, a doped well 101a is formed in the substrate, a contact hole 20 is formed in the dielectric layer and penetrates through the dielectric layer, the contact hole 20 exposes the doped well 101a, and a depth of the doped well 101a is smaller than a predetermined depth. Specifically, the contact hole 20 is provided at an edge position of the semiconductor device, and the contact hole 20 penetrates only the top of the semiconductor device. The edge position of the semiconductor device is provided with a peripheral circuit. The depth of the doped well 101a being less than the predetermined depth may be expressed as: the depth of the doped well 101a itself is smaller than the preset depth, or the depth of the doped well 101a is smaller than the preset depth due to the filling of the impurity a, such as the filling of amorphous silicon, in the doped well 101 a; or the depth of the doped well 101a itself is less than the predetermined depth, and the doped well 101a is further filled with the impurity a.
S2, referring to fig. 4, a protection layer 30 exposing the contact hole 20 is formed on the semiconductor device 10. In one embodiment, the material of the protection layer 30 is a polymer. Protective layer 30 may be formed by depositing a polymer on semiconductor device 10. The polymer may be formed by deposition directly on top of the semiconductor device 10 in a simple and short time.
S3, referring to fig. 5, the bottom of the doped well 101a is etched using the protection layer 30 as a mask, so that the depth of the etched doped well 101a is greater than or equal to a predetermined depth. Specifically, the etched doped well 101a extends downward into the substrate 101, so that a portion of the substrate 101 is etched, i.e., the etching process is to etch the substrate 101, and the silicon substrate 101 can be etched by selecting the etchant. The substrate 101 is made of Silicon, for example, but may also be other Silicon-containing substrates 101, such as Silicon On Insulator (SOI), SiGe, Si: C, etc., and p-type/n-type or deep or shallow wells required for the device may be formed in the substrate 101 through ion implantation, etc. In a specific embodiment, the difference between the depth of the contact hole 20 after etching and the depth of the contact hole before etching is greater than or equal to 40 nm. The depth of the contact hole 20 is 10nm before etching, and the depth of the contact hole 20 after etching is at least 50 nm.
In this step, in the etching process of the contact hole 20, since the protective layer 30 is used as a mask, the pattern structure of the existing semiconductor device 10 is not damaged, so that the cost is saved, when the impurity a, such as amorphous silicon, exists in the doped well 101a, the impurity a may be etched first, then the bottom of the doped well 101a is further etched, and when the impurity a does not exist in the doped well 101a, the bottom of the doped well 101a is directly etched. The depth of the etched doped well 101a at least reaches a predetermined depth. And the protective layer 30 may be removed when the depth of the doped well 101a reaches at least a predetermined depth. The method of removing the polymer protective layer 30 may be to peel off the protective layer 30 directly or to dissolve the polymer protective layer 30 with a related agent, but the agent does not affect the structure of the semiconductor device 10, such as with an organic solvent.
Therefore, according to the present application, the polymer protection layer 30 is formed on the semiconductor device 10, and the polymer protection layer 30 is used as a mask to further deepen the etching of the doped well 101a, so that the depth of the doped well 101a reaches a preset depth, and when other conductive structures are formed in the doped well 101a in a later stage, due to the deeper doped well 101a, the conductive structure formed in the doped well 101a can be in good contact with the substrate 101, and the conductivity is good, so that the electrical performance of the three-dimensional memory 100 is improved, and the performance such as reading, writing, programming or erasing is good.
Meanwhile, as the polymer protective layer 30 is used as a mask to further deepen etching of the doped well 101a, the deposition forming speed of the polymer is high, and the polymer is directly deposited and formed on the graph structure of the semiconductor device 10, the polymer formed by deposition naturally exposes the doped well 101a, the preparation of the traditional mask photomask 80 (figure 2) is omitted, the opening 801 arranged at the position corresponding to the contact hole 20 on the mask photomask 80 is also omitted, and manpower and material resources for arranging the mask photomask 80 and the opening 801 are also omitted. The preparation method of the three-dimensional memory saves manpower and material resources, and is low in manufacturing cost and high in efficiency. Compared with the traditional preparation method of the three-dimensional memory, the preparation method of the three-dimensional memory has the advantage that the efficiency is improved by at least 50%.
In one embodiment, the protective layer 30 is deposited such that the protective layer 30 covers the top sidewalls of the contact holes 20. That is, the protection layer 30 of the present application includes a plurality of protection bodies 301, and the protection bodies 301 are not only disposed on the top surface of the semiconductor device 10, but also surround the sidewalls of the contact hole 20, so that the sidewalls of the contact hole 20 are not damaged when the doped well 101a is etched. Therefore, only the bottom of the doped well 101a is etched when the semiconductor device 10 is etched under the protection of the protective layer 30.
In a specific embodiment, a channel structure extending in a direction perpendicular to the substrate 101 is formed in the stacked structure 106b, and a first via 106a exposing the top of the stacked structure 106b is formed on the top of the semiconductor device 10;
the formation method of the protection layer 30 is deposition, and the first via hole 106a is filled with the protection layer 30 when the protection layer 30 is deposited.
Specifically, the semiconductor device 10 of the present application first forms the channel hole 106a on the stacked structure, forms the epitaxial structure 50 in the channel hole 106a after forming the channel hole 106a, forms the channel structure on the epitaxial structure 50 and the sidewall of the channel hole, the channel structure extends along the direction perpendicular to the substrate 101, and then forms the plug opening on the channel structure. The first through hole 106a is a plug, and the material of the channel structure is generally selected to be polysilicon, which is substantially the same as the material of the substrate 101, so as to avoid etching the channel structure when etching the doped well 101a, the protective layer 30 of the present application covers the plug, i.e., the first through hole 106a, so as to avoid etching the channel structure when etching the doped well 101 a.
The stacked structure 106b will be described as follows.
The stacked structure 106b includes a step portion 105 and a core portion 106, the step portion 105 is located at an edge of the stacked structure 106b, and the first through hole 106a is formed on the core portion 106;
the stack structure 106b includes gate layers 105f and insulating layers 105e alternately stacked;
the semiconductor device 10 further includes a plurality of second vias 105a penetrating through the step portion 105 and the dielectric layer 105c, wherein the plurality of second vias 105a respectively expose the gate layer 105f of different layers;
the protective layer 30 is exposed from the second via hole 105a when the protective layer 30 is deposited.
Specifically, the second via hole 105a penetrates through the dielectric layer 105c and extends to the step 105. The step portion 105 includes a plurality of steps, and one second through hole 105a penetrates to one step. Each step is a stack of alternately stacked insulating layers 105e and gate sacrificial layers. Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable Deposition methods may be used to alternately deposit on the substrate 101 in sequence. The insulating layer 105e is made of, for example, silicon oxide, and the gate sacrificial layer is made of, for example, silicon nitride, which is replaced with metal in a subsequent process to serve as the gate layer 105 f. The insulating layer 105e may be silicon oxynitride, or the like, and the gate sacrificial layer may be amorphous silicon, polysilicon, aluminum oxide, or the like. In this application, each second via hole 105a of the step portion penetrates through the insulating layer 105e, and during the further etching process of the doped well 101a, the selective etchant does not etch the gate layer 105f and does not damage the sidewall of the second via hole 105a, but only selectively etches the bottom of the doped well 101 a.
The core portion 106 of the stacked structure 106b has a channel hole formed thereon, and the channel hole penetrates through the stacked structure 106b and extends to the substrate 101. The core portion 106 is a stack of insulating layers 105e and gate sacrificial layers alternately stacked. Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable Deposition methods may be used to alternately deposit on the substrate 101 in sequence. The insulating layer 105e is made of, for example, silicon oxide, and the gate sacrificial layer is made of, for example, silicon nitride, which is replaced with metal in a subsequent process to serve as the gate layer 105 f. The insulating layer 105e may be silicon oxynitride, or the like, and the gate sacrificial layer may be amorphous silicon, polysilicon, aluminum oxide, or the like.
In a specific embodiment, the doped well 101a is selectively etched such that the depth of the doped well 101a is greater than or equal to a predetermined depth. That is, in this step, although the protective layer 30 also exposes the second via hole 105a, the semiconductor device 10 is etched using a selective etchant, such as a chlorine-based gas, which etches only the doped well 101a without etching the second via hole 105a, so that the pattern structure of the semiconductor device 10 is not damaged during the etching of the contact hole 20. Meanwhile, during the etching process, the semiconductor device 10 may be protected by using a high carbon/fluorine ratio gas (C/F ratio) and/or a hydrocarbon gas (CHx) to prevent the etching gas from etching a portion of the semiconductor device 10 that does not need to be etched.
In a specific embodiment, the aperture of the second through hole 105a is larger than the aperture of the first through hole 106a, and the preparation method further includes:
the formation time of the protective layer is controlled so that the protective layer fills the first via hole 106a and covers the top sidewall of the second via hole 105 a.
That is, when the protection layer 30 completely fills the first through hole 106a, since the aperture of the second through hole 105a is larger than the aperture of the first through hole 106a, the protection layer 30 will not completely fill the second through hole 105a, and only the protection layer is formed on the sidewall of the second through hole, which saves materials, so that the material of the protection layer 30 will be greatly saved in a manner that the protection layer 30 only fills the first through hole 106a, and the etchant will not etch the second through hole 105a, which will not damage the pattern structure of the semiconductor device 10. Therefore, according to the present application, the protective layer 30 only fills the first through hole 106a, so that the contact hole 20 and the second through hole 105a are exposed, and when the etchant etches the doping well 101a of the semiconductor device 10, the pattern structure of the semiconductor device 10 is not damaged, and the material of the protective layer 30 is saved.
Meanwhile, the protection layer 30 of the present application includes a plurality of protection bodies 301, and the protection bodies 301 are not only disposed on the top surface of the semiconductor device 10, but also surround the sidewalls of the second through holes 106a, so that the side surfaces of the contact holes 20 are not damaged when the doped wells 101a are etched. Therefore, only the bottom of the doped well 101a is etched when the semiconductor device 10 is etched under the protection of the protective layer 30.
The semiconductor device 10 further includes a planarization layer 60, the planarization layer 60 is formed on the stacked structure 106b and the dielectric layer 105c, and the contact hole 20, the second via hole 105a, and the first via hole 106a all penetrate through the dielectric layer 60.
Referring to fig. 5, in addition to the above-mentioned method for fabricating a three-dimensional memory, an embodiment of the invention further provides a three-dimensional memory 100. The three-dimensional memory 100 and the method for manufacturing the three-dimensional memory according to the embodiments of the present invention can achieve the advantages of the present invention, and the two can be used together or separately, which is not particularly limited by the present invention. In a specific embodiment, the three-dimensional memory 100 is formed by the above-mentioned method for manufacturing the three-dimensional memory 100.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. A method for preparing a three-dimensional memory is characterized by comprising the following steps:
providing a semiconductor device, wherein the semiconductor device comprises a substrate, a stacking structure and a dielectric layer, the stacking structure and the dielectric layer are positioned on the substrate, the dielectric layer surrounds the stacking structure, a doped well is formed in the substrate, a contact hole penetrating through the dielectric layer is formed in the dielectric layer, the contact hole exposes the doped well, and the depth of the doped well is smaller than a preset depth; a first through hole exposing the top of the stacked structure is formed at the top end of the semiconductor device;
forming a protective layer on the semiconductor device to expose the contact hole; the forming method of the protective layer is deposition, and the first through hole is filled with the protective layer when the protective layer is deposited;
and etching the bottom of the doped well by taking the protective layer as a mask so as to enable the depth of the etched doped well to be more than or equal to the preset depth.
2. The method according to claim 1, wherein a channel structure extending in a direction perpendicular to the substrate is formed in the stacked structure.
3. The method of claim 2, wherein the protective layer is deposited while covering top sidewalls of the contact hole.
4. The production method according to claim 2, wherein the stacked structure includes a stepped portion and a core portion, the stepped portion is located at an edge of the stacked structure, and the first through-hole is formed on the core portion;
the stacked structure comprises gate layers and insulating layers which are alternately stacked;
the semiconductor device further comprises a plurality of second through holes penetrating through the step part and the dielectric layer, and the plurality of second through holes respectively expose the gate layers of different layers;
and exposing the second through hole by the protective layer when the protective layer is deposited.
5. The method of claim 4, wherein the protective layer is deposited while covering a top sidewall of the second via.
6. The production method according to claim 4, wherein an aperture of the second through-hole is larger than an aperture of the first through-hole, the production method further comprising:
and controlling the forming time of the protective layer so that the protective layer fills the first through hole and covers the top side wall of the second through hole.
7. The method of claim 1, wherein the doped well is etched using a chlorine-based gas.
8. The method of claim 1, wherein the depth difference between the doped well after etching and the doped well before etching is greater than or equal to 40 nm.
9. The method according to claim 1, wherein the protective layer is made of a polymer.
10. A three-dimensional memory, characterized in that it is produced by the production method according to any one of claims 1 to 9.
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