CN109755254A - Three-dimensional storage and preparation method thereof - Google Patents
Three-dimensional storage and preparation method thereof Download PDFInfo
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- CN109755254A CN109755254A CN201910149876.5A CN201910149876A CN109755254A CN 109755254 A CN109755254 A CN 109755254A CN 201910149876 A CN201910149876 A CN 201910149876A CN 109755254 A CN109755254 A CN 109755254A
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Abstract
The present invention relates to semiconductor design and manufacturing fields, and more particularly to a kind of three-dimensional storage and preparation method thereof, three-dimensional storage includes semiconductor structure and stacked structure, and wherein semiconductor structure has peripheral circuit；Stacked structure is located on peripheral circuit, stacked structure includes core space and wordline bonding pad, core space has channel hole, memory film and channel layer are formed in channel hole, wordline bonding pad has the contact hole through wordline bonding pad, insulative sidewall and conductive supporting column are formed in contact hole, conductive supporting column connects peripheral circuit.The present invention can efficiently use the area of wordline bonding pad, reduce the area of the peripheral region occupied needed for peripheral circuit is drawn, improve the integrated level and performance of three-dimensional storage, simultaneously, the present invention can avoid the short circuit or electric leakage that contact hole bottom inserts polysilicon and causes device, improve the electrical stability and yield of three-dimensional storage.
Description
Technical field
The invention belongs to semiconductor design and manufacturing fields, more particularly to a kind of three-dimensional storage and preparation method thereof.
Background technique
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges: physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty that encounters of planar flash memory and pursue being produced into for lower unit storage unit
This, three-dimensional memory structure comes into being, and three-dimensional memory structure can make each memory die in memory device
Memory cell with greater number.
In the nonvolatile memory, such as nand memory, increase memory density a kind of mode be by using
Vertical memory array, i.e. 3D nand memory, and CTF (Charge Trap Flash, charge-trapping flash memory) type 3D NAND
Memory is current more forward position and memory technology with development potential.
In CTF type 3D nand memory, has and the stacked structure formed, institute are alternately stacked by dielectric layer and grid layer
Stating stacked structure includes core space and wordline bonding pad.The core space, the storage for information；The wordline bonding pad, position
In the end of the stacked structure, for transmitting control information to the core space, to realize information in the reading of the core space
It writes.Wherein, there is the support column through the stacked structure to keep away for being supported to the stacked structure for the stepped region
Exempt from the stacked structure to collapse.
But existing support column bottom would generally be received in conductive semiconductor material, be easy to cause the electric leakage of memory,
Meanwhile support column needs additionally to account for memory-aided space, and the volume of memory is caused to become larger.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of three-dimensional storage and its production
Method would generally be received in conductive semiconductor material for solving support column bottom in the prior art, be easy to cause memory
Electric leakage, meanwhile, support column needs the problem of additionally accounting for memory-aided space, the volume of memory is caused to become larger.
In order to achieve the above objects and other related objects, the present invention provides a kind of three-dimensional storage, comprising: semiconductor junction
Structure, the semiconductor structure include peripheral circuit；Stacked structure is located on the peripheral circuit, and the stacked structure includes core
Heart district and wordline bonding pad, the core space has channel hole, is formed with memory film and channel layer in the channel hole, described
Wordline bonding pad has the contact hole through the wordline bonding pad, is formed with insulative sidewall and conductive supporting in the contact hole
Column, the conductive supporting column connect the peripheral circuit.
Optionally, the stacked structure includes alternately stacked grid layer and dielectric layer, described in the insulative sidewall isolation
Conductive supporting column and the grid layer.
Optionally, the wordline bonding pad includes hierarchic structure, and insulating layer, the insulation are covered in the hierarchic structure
There is wordline through-hole in layer, be filled with wordline conductive layer, the wordline conductive layer and the hierarchic structure in the wordline through-hole
In the grid layer connection.
Optionally, the insulative sidewall in the contact hole includes silicon dioxide layer, and described in the contact hole is led
Electric support column includes tungsten.
Optionally, the memory film includes barrier layer, electric charge capture layer and tunnel layer, wherein the barrier layer is located at
The sidewall surfaces in the channel hole, the electric charge capture layer are located at the surface on the barrier layer, and the tunnel layer is located at the electricity
The surface of lotus trapping layer, the channel layer are located at the surface of the tunnel layer.
Optionally, be formed with common source line layer between the peripheral circuit and the core space, the common source line layer with
The peripheral circuit connection.
Optionally, the common source line layer includes metal layer and the doping semiconductor layer on the metal layer, described
Doping semiconductor layer and the metal layer form Ohmic contact.
Optionally, the bottom in the channel hole is formed with doped polysilicon layer, the channel layer and the DOPOS doped polycrystalline silicon
Layer connection, the doped polysilicon layer are connect with the common source line layer.
Optionally, the core space is also formed with grid line separate slot, and the side wall of the grid line separate slot is formed with separation layer, described
Conductive material layer is filled in grid line separate slot, the conductive material layer is connect with the common source line layer.
Optionally, further include peripheral region, be located at outside the wordline bonding pad, the peripheral region has peripheral contact hole, institute
It states and is formed with insulation division and conductive part in peripheral contact hole, the conductive part connects the peripheral circuit.
Optionally, the peripheral circuit includes circuit layer and the wiring layer on the circuit layer.
The present invention also provides a kind of production methods of three-dimensional storage, comprising the following steps: semiconductor structure is provided, it is described
Semiconductor structure has peripheral circuit；Laminated construction is formed on the semiconductor structure, and the laminated construction includes core space
And wordline bonding pad；Channel hole is formed in the core space；Memory film and channel layer are formed in the channel hole；Described
Wordline bonding pad forms contact hole, and the contact hole appears the peripheral circuit；In the contact hole formed insulative sidewall and
Conductive supporting column is filled, the conductive supporting column connects the peripheral circuit.
Optionally, memory film and channel layer are formed in the channel hole comprising steps of side wall in the channel hole
Upper formation barrier layer；Electric charge capture layer is formed on the barrier layer；Tunnel layer is formed on the electric charge capture layer；Described
The channel layer is formed on tunnel layer.
Optionally, the production method, which is further comprised the steps of:, forms common source between the peripheral circuit and the core space
Polar curve layer, the common source line layer are connect with the peripheral circuit.
Optionally, the common source line layer is formed comprising steps of forming metal layer on the peripheral circuit；In the gold
Belong to and form doping semiconductor layer on layer, the doping semiconductor layer and the metal layer form Ohmic contact.Optionally, further include
Step: doped polysilicon layer, and the channel layer being subsequently formed and the doped polycrystalline are formed in the bottom in the channel hole
Silicon layer contacts.
Optionally, the laminated construction includes alternately stacked dielectric layer and sacrificial layer, and the production method further includes step
It is rapid: to remove the sacrificial layer of the laminated construction, form gap between the adjacent dielectric layer；It fills out in the gap
Fill grid layer.
Optionally, the sacrificial layer is removed comprising steps of the core space in the laminated construction forms grid line separate slot；
By the grid line separate slot, the sacrificial layer is removed using wet corrosion technique.
Optionally, the side wall further comprised the steps of: in the grid line separate slot forms separation layer；It is filled in the grid line separate slot
Conductive material layer.
Optionally, the dielectric layer of the laminated construction includes silicon dioxide layer, the sacrifice of the laminated construction
Layer includes silicon nitride layer, and the insulative sidewall in the contact hole includes silicon dioxide layer, and described in the contact hole is led
Electric support column includes tungsten.
Optionally, the semiconductor structure also has the peripheral region except the laminated construction, the production method
It further comprises the steps of: when the wordline bonding pad forms the contact hole, forms peripheral contact hole in the peripheral region；Described
Formed in contact hole the insulative sidewall and fill the conductive supporting column when, in the peripheral contact hole formed insulation division and
Conductive part is filled, the conductive part connects the peripheral circuit.
Optionally, the peripheral circuit includes circuit layer and the wiring layer on the circuit layer.
As described above, three-dimensional storage and preparation method thereof of the invention, has the advantages that
Three-dimensional storage provided by the invention and its manufacturing method, in wordline bonding pad using conductive supporting column come to lamination
Structure is supported, and conductive supporting column is used for the electrical of peripheral circuit simultaneously and draws, compared to traditional in wordline bonding pad
Using the support construction of no electrical functionality, the present invention can efficiently use the area of wordline bonding pad, reduce peripheral circuit and draw institute
The area for the peripheral region that need to be occupied improves three-dimensional storage while the cost of manufacture that three-dimensional storage is effectively reduced
Integrated level and performance.
The non-concurrent production of contact hole in the channel hole and wordline bonding pad in core of the invention area, can effectively avoid channel hole
The polysilicon of out-of-flatness is inserted to contact hole while filling polysilicon, to avoid contact with hole bottom filling polysilicon and cause
Short circuit or electric leakage between the structures such as bottom grid layer and dummy word line improve the electrical stability and yield of three-dimensional storage.
Detailed description of the invention
Fig. 1 is shown as a kind of structural schematic diagram of three-dimensional storage.
Fig. 2 is shown as a kind of structural schematic diagram of three-dimensional storage of the embodiment of the present invention.
Fig. 3 is shown as a kind of process flow chart of the production method of three-dimensional storage of the embodiment of the present invention.
Fig. 4~Figure 15 is shown as the knot that a kind of each step of production method of three-dimensional storage of the embodiment of the present invention is presented
Structure schematic diagram.
Component label instructions
111 channel holes
112 supported holes
113 first silicon layers
114 second silicon layers
115,116 dielectric
101 substrates
102 N-shaped deep-well regions
103 p-type high-pressure trap areas
201 gate structures
202 source electrodes
203 drain electrodes
30 wiring layers
301 interconnection metals
302 interlayer insulating films
401 metal layers
402 doping semiconductor layers
11 core spaces
12 wordline bonding pads
13 peripheral regions
50a laminated construction
50b stacked structure
501 sacrificial layers
502 dielectric layers
503 insulating layers
504 channel holes
505 doped polysilicon layers
506 gaps
507 grid layers
53 memory films
531 barrier layers
532 electric charge capture layers
533 tunnel layers
54 channel layers
601 contact holes
602 insulative sidewalls
603 conductive supporting columns
701 peripheral contact holes
702 insulation divisions
703 conductive parts
801 grid line separate slots
802 separation layers
803 conductive material layers
901 wordline conductive layers
S11~S16 step
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Such as when describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion
Make partial enlargement, and the schematic diagram is example, the scope of protection of the invention should not be limited herein.In addition, in reality
It should include the three-dimensional space of length, width and depth in production.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Deng spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will be understood that
Arrive, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.In addition, when one layer be referred to as two layers " between " when, it can be only layer, Huo Zheye between described two layers
There may be one or more intervenient layers.
In the context of this application, described fisrt feature second feature " on " structure may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
It should be noted that the basic conception that only the invention is illustrated in a schematic way is illustrated provided in the present embodiment,
Then only shown in diagram with it is of the invention in related component rather than component count, shape and size when according to actual implementation draw
System, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout kenel can also
It can be increasingly complex.
As shown in Figure 1, forming Jie being alternately stacked on a semiconductor substrate first in the manufacturing process of three-dimensional storage
The laminated construction of matter layer and sacrificial layer, the laminated construction include core space and wordline bonding pad, and the core space is for information
Storage；The wordline bonding pad is located at the end of the laminated construction, for transmitting control information to the core space, to realize
Read-write of the information in the core space；Then in same processing step, channel hole 111 is formed in core space, while in wordline
Bonding pad formed supported hole 112, and using selective epitaxial growth (Selective Epitaxy Growth, SEG) technology in
One layer of first silicon layer 113 of channel hole bottom grown, the first silicon layer 113 can be inserted while production in the supported hole
Second silicon layer 114, since the arrangement density of the supported hole in the channel hole and wordline bonding pad of core space has biggish difference, because
This, the pattern of the second silicon layer 114 is difficult to control in the supported hole of wordline bonding pad, causes the second silicon layer 114 easy and bottom gate
It connects between the structures such as pole layer and dummy word line and causes short circuit or electric leakage.Finally, need to remove the sacrificial layer in stacked structure, with
Gap is formed between adjacent dielectric；Then grid layer is filled in the gap.In this course, in order to avoid in shape
It collapses at laminated construction described behind gap, it usually needs formed in the wordline bonding pad through the laminated construction
Support column, and dielectric 115 is filled in these support columns, and dielectric 116 is filled in channel hole 111, wherein absolutely
The material of edge medium 115 and dielectric 116 can be identical or different, and the support column after filling dielectric 115 does not have electricity
Sexual function occupies wordline bonding pad area.In addition, three-dimensional storage usually requires to carry out peripheral circuit in peripheral region
It draws, leads to the increase of device volume.
As shown in Fig. 2, to solve the above-mentioned problems, the present embodiment provides a kind of three-dimensional storages, which can
Think 3D nand memory.The three-dimensional storage includes semiconductor structure and stacked structure 50b, the stacked structure 50b packet
Include core space 11, wordline bonding pad 12.
The semiconductor structure includes substrate 101 and multiple peripheral components for being formed on substrate 101, such as field-effect crystalline substance
Body pipe, capacitor, inductance and/or pn-junction diode etc., for example, the semiconductor structure includes substrate 101, in the substrate 101
With N-shaped deep-well region 102 and p-type high-pressure trap area 103, and p-type high-pressure trap area 103 is surrounded by N-shaped deep-well region 102.Described half
Conductor structure has peripheral circuit, which is formed in 101 surface of substrate, for example, peripheral circuit includes circuit layer, circuit
For example including gate structure 201, which is formed on p-type high-pressure trap area 103 layer.Example in p-type high-pressure trap area 103
Source 202 and drain electrode 203 are such as formed, constitutes the peripheral components such as CMOS transistor, MOS transistor with gate structure 201.This
A little peripheral components are used as the different function device, such as buffer, amplifier, decoder etc. of memory.
Above-mentioned substrate 101 can be monocrystalline silicon layer.The substrate 101 can also be by other materials system in some embodiments
At such as, but not limited to SiGe, germanium, silicon on insulator (SOI).In other embodiments, the substrate 101 can also be
Substrate, such as GaAs, indium phosphide or silicon carbide including other elements semiconductor or compound semiconductor etc. can also be folded
Layer structure 50a, such as silicon/germanium silicon lamination etc..Above-mentioned p-type high-pressure trap area 103 and N-shaped deep-well region 102 can be infused by such as ion
Enter and/or thermal diffusion process obtains.
The peripheral circuit further includes wiring layer 30, and wiring layer 30 is for example including interconnection metal 301 and interlayer insulating film
302, interconnection metal 301 is connected to source electrode 202 and drain electrode 203, and to carry out electric signal conduction, interconnection metal 301 includes but unlimited
In tungsten, cobalt, copper and/or aluminium, interlayer insulating film 302 is made of insulating material, including but not limited to silica, silicon nitride, nitrogen oxygen
SiClx, and/or doped silicon oxide.
Peripheral circuit region corresponding with the core space 11 is formed with common source line layer, the common source line layer with
The peripheral circuit connection.The common source line layer includes metal layer 401 and the doped semiconductor on the metal layer 401
Layer 402, the doping semiconductor layer 402 form Ohmic contact with the metal layer 401, for example, the metal layer 401 include but
It is not limited to tungsten, cobalt, copper, aluminium and/or metal silicide, the doping semiconductor layer 402 includes but is not limited to DOPOS doped polycrystalline silicon etc..
The stacked structure 50b is located on the peripheral circuit, for example, the stacked structure 50b includes alternately stacked
Grid layer 507 and dielectric layer 502, the dielectric layer 502 include but is not limited to silica, and the grid layer 507 includes but not
It is limited to tungsten, copper or/and aluminium.
The stacked structure 50b includes core space 11 and wordline bonding pad 12, and the core space 11 has channel hole 504,
It is formed with memory film 53 and channel layer 54 in the channel hole 504 (from the point of view of Fig. 9), wherein channel layer 54 is led as electrical
Communication channel, the data storage layer for the charge that memory film 53 is injected as storage from channel layer 54, above-mentioned 507 conduct of grid layer
Grid is controlled, channel layer 54, memory film 53 and grid layer 507 form storage unit.The memory film 53 includes barrier layer
531, electric charge capture layer 532 and tunnel layer 533 (from the point of view of Figure 10 b), wherein the barrier layer 531 is located at the channel hole
504 sidewall surfaces, the electric charge capture layer 532 are located at the surface on the barrier layer 531, and the tunnel layer 533 is located at described
The surface of electric charge capture layer 532, the channel layer 54 are located at the surface of the tunnel layer 533.The material packet on the barrier layer 531
Include but be not limited to silica, the material of the electric charge capture layer 532 includes but unlimited silicon nitride the material of the tunnel layer 533
Matter includes but is not limited to silica, and the material of the channel layer 54 includes but is not limited to the polysilicon of p-type doping.
Further, the bottom in the channel hole 504 is formed with doped polysilicon layer 505, the channel layer 54 and institute
The connection of doped polysilicon layer 505 is stated, the doped polysilicon layer 505 is connect with the common source line layer, the DOPOS doped polycrystalline silicon
Layer 505 can effectively reduce the resistance between channel layer 54 and common source line layer.
From the point of view of Figure 13 and Figure 14, the core space 11 is also formed with grid line separate slot 801, the grid line separate slot 801
Side wall is formed with separation layer 802, is filled with conductive material layer 803 in the grid line separate slot 801, the conductive material layer 803 with
The common source line layer connection.For example, the material of the separation layer 802 can be silica etc., the conductive material layer 803
Material can be for tungsten etc..Multiple storage units can be divided into memory block (block) by 801 one side of grid line separate slot,
On the other hand, the circuit that common source line layer can be led to top, can increase the flexibility of circuit design and layout.
From the point of view of Figure 11 and Figure 12, the wordline bonding pad 12 has the contact hole through the wordline bonding pad 12
601, insulative sidewall 602 and conductive supporting column 603 are formed in the contact hole 601, the conductive supporting column 603 connects described
The conductive supporting column 603 and the grid layer 507 is isolated in peripheral circuit, the insulative sidewall 602.For example, the contact hole
The insulative sidewall 602 in 601 includes silicon dioxide layer, and the conductive supporting column 603 in the contact hole 601 includes
Tungsten, titanium or titanium nitride.603 one side of conductive supporting column can be supported stacked structure 50b, on the other hand can be used for
The electrical of peripheral circuit is drawn, and uses the support construction without electrical functionality in wordline bonding pad 12 compared to traditional, can be effective
Using the area of wordline bonding pad 12, reduce the area of the peripheral region 13 occupied needed for peripheral circuit is drawn, improves three-dimensional storage
The integrated level and performance of device.Further, 601 bottom of contact hole will not insert polysilicon and cause bottom grid layer 507 and puppet
Short circuit or electric leakage between the structures such as wordline, can be improved the electrical stability of three-dimensional storage.
From the point of view of Fig. 7, the wordline bonding pad 12 can be set to hierarchic structure, in order to the extraction of grid layer 507,
It is covered with insulating layer 503 in the hierarchic structure, there is wordline through-hole in the insulating layer 503, filled in the wordline through-hole
There is wordline conductive layer 901, the wordline conductive layer 901 is connect with the grid layer 507 in the hierarchic structure.
From the point of view of Figure 11 and Figure 12, the three-dimensional storage can also include peripheral region 13, and peripheral region 13 is located at described
Outside wordline bonding pad 12, the peripheral region 13 has peripheral contact hole 701, is formed with insulation division in the peripheral contact hole 701
702 and conductive part 703, the conductive part 703 connect the peripheral circuit.
It should be noted that the contact hole 601 that has of wordline bonding pad 12 is enough and it can be completely achieved peripheral circuit
When extraction, the three-dimensional storage can be not provided with peripheral region 13, so as to greatly reduce the volume of device.
As shown in Fig. 3~Figure 15, the present embodiment also provides a kind of production method of three-dimensional storage, comprising the following steps:
As shown in Fig. 3, Fig. 4 and Fig. 5, progress step 1) S11 first provides semiconductor structure, the semiconductor structure tool
There is peripheral circuit.
The semiconductor structure includes substrate 101 and multiple peripheral components for being formed on substrate 101, such as field-effect crystalline substance
Body pipe, capacitor, inductance and/or pn-junction diode etc., for example, as shown in figure 4, the semiconductor structure includes substrate 101, it is described
There is N-shaped deep-well region 102 and p-type high-pressure trap area 103, and p-type high-pressure trap area 103 is wrapped by N-shaped deep-well region 102 in substrate 101
It encloses.The semiconductor structure has peripheral circuit, which is formed in 101 surface of substrate, for example, peripheral circuit includes electricity
Road floor, circuit layer are formed on p-type high-pressure trap area 103 for example including gate structure 201, the gate structure 201.P-type high pressure trap
Source 202 and drain electrode 203 are for example formed in area 103, it is outer to constitute CMOS transistor, MOS transistor etc. with gate structure 201
Peripheral device.These peripheral components are used as the different function device, such as buffer, amplifier, decoder etc. of memory.
Above-mentioned substrate 101 can be monocrystalline silicon layer.The substrate 101 can also be by other materials system in some embodiments
At such as, but not limited to SiGe, germanium, silicon on insulator (SOI).In other embodiments, the substrate 101 can also be
Substrate, such as GaAs, indium phosphide or silicon carbide including other elements semiconductor or compound semiconductor etc. can also be folded
Layer structure 50a, such as silicon/germanium silicon lamination etc..Above-mentioned p-type high-pressure trap area 103 and N-shaped deep-well region 102 can be infused by such as ion
Enter and/or thermal diffusion process obtains.
The peripheral circuit further includes wiring layer 30, and wiring layer 30 is for example including interconnection metal 301 and interlayer insulating film
302, interconnection metal 301 is connected to source electrode 202 and drain electrode 203, and to carry out electric signal conduction, interconnection metal 301 includes but unlimited
In tungsten, cobalt, copper and/or aluminium, interlayer insulating film 302 is made of insulating material, including but not limited to silica, silicon nitride, nitrogen oxygen
SiClx, and/or doped silicon oxide.301 formation process of interconnection metal can use thin film deposition technique, including but not limited to
Chemical vapour deposition technique (CVD), physical vaporous deposition (PVD), atomic layer deposition method (ALD) or electroplating technology, can also make
With photoetching, chemical-mechanical planarization, dry/wet etching.The formation process of interlayer insulating film 302 can use thin film deposition work
Skill, including but not limited to chemical vapour deposition technique (CVD), physical vaporous deposition (PVD) or atomic layer deposition method (ALD).
Although there has been described the exemplary constructive methods of semiconductor structure, it is to be understood that, one or more features can
To be omitted, substitute or increase in this semiconductor structure from this semiconductor structure.
As shown in FIG. 6 and 7, step 2) S12 is then carried out, forms laminated construction 50a, institute on the semiconductor structure
Stating laminated construction 50a includes core space 11 and wordline bonding pad 12, and wordline bonding pad 12 is located at the end of the laminated construction 50a
Region.
For example, can be using such as chemical vapour deposition technique (CVD), physical vaporous deposition (PVD) or atomic layer deposition method
(ALD) etc. the laminated construction 50a is formed, the laminated construction 50a includes alternately stacked dielectric layer 502 and sacrificial layer 501,
The dielectric layer 502 of the laminated construction 50a includes but is not limited to silicon dioxide layer, and the laminated construction 50a's is described sacrificial
Domestic animal layer 501 includes but is not limited to silicon nitride layer, and the dielectric layer 502 is with the sacrificial layer 501 in same etching/etching process
With certain selection ratio.
The wordline bonding pad 12 is etched to form step structure and in the wordline bonding pad 12 as shown in fig. 7, connecting
Upper covering insulating layer 503, which can be conducive to the extraction of subsequent gate layer 507.
Before forming the laminated construction 50a, common source first can be formed between the peripheral circuit and the core space 11
Polar curve layer, the common source line layer are connect with the peripheral circuit, as shown in Figure 6.For example, forming the common source line layer and including
Step: metal layer 401 is formed on the peripheral circuit；Doping semiconductor layer 402 is formed on the metal layer 401, it is described
Doping semiconductor layer 402 and the metal layer 401 form Ohmic contact, and the common source line layer is connect with the peripheral circuit.
For example, the metal layer 401 includes but is not limited to tungsten, cobalt, copper aluminium and/or metal silicide, the doping semiconductor layer 402 is wrapped
Include but be not limited to DOPOS doped polycrystalline silicon etc..
As shown in figure 8, then carrying out step 3) S13, channel hole 504 is formed in the core space 11.
For example, channel hole 504, the channel hole can be formed in the core space 11 using photoetching process and etching technics
504 are through to the common source line layer.When forming the channel hole 504, keeps the wordline bonding pad 12 to be in and block shape
State, the wordline bonding pad 12 as described in being blocked using photoresist and/or hard exposure mask, so that branch is not formed in the wordline bonding pad 12
Support hole.
It is then also possible to form doped polycrystalline in the bottom in the channel hole 504 using the methods of selective epitaxial growth
Silicon layer 505, and the channel layer 54 being subsequently formed is contacted with the doped polysilicon layer 505, the doped polysilicon layer 505
It can effectively reduce the resistance between channel layer 54 and common source line layer, as shown in Figure 9.Due to being not formed in wordline bonding pad 12
Supported hole can insert the generation for causing subsequent device to be leaked electricity in the supported hole of wordline bonding pad 12 to avoid DOPOS doped polycrystalline silicon.
As shown in Figure 10 a and Figure 10 b, wherein Figure 10 b is shown as the enlarged structure schematic diagram at Figure 10 a dotted line frame, then
Step 4) S14 is carried out, forms memory film 53 and channel layer 54 in the channel hole 504.
For example, forming memory film 53 and channel layer 54 in the channel hole 504 comprising steps of in the channel hole
Barrier layer 531 is formed on 504 side wall；Electric charge capture layer 532 is formed on the barrier layer 531；In the electric charge capture layer
Tunnel layer 533 is formed on 532；The channel layer 54 is formed on the tunnel layer 533, the channel layer 54 and the doping are more
Crystal silicon layer 505 contacts.The material on the barrier layer 531 includes but is not limited to silica, the material of the electric charge capture layer 532
Including but unlimited silicon nitride, the material of the tunnel layer 533 includes but is not limited to silica, the material packet of the channel layer 54
Include but be not limited to the polysilicon of p-type doping.
In order to further decrease the channel layer 54 electricity of the contact with the doped polysilicon layer 505 of channel hole bottom
Resistance, this example can the surface first to the doped polysilicon layer 505 perform etching, the memory film 53 on its surface is gone
It removes, re-forms the channel layer 54, to improve the contact area of channel layer 54 Yu doped polysilicon layer 505, reduce contact electricity
Resistance.
As shown in figure 11, step 5) S15 is then carried out, forms contact hole 601, the contact in the wordline bonding pad 12
Hole 601 appears the peripheral circuit.
For example, contact hole 601 can be formed in the wordline bonding pad 12 using photoetching process and etching technics, work is etched
Skill stops on the interconnection metal 301 of the wiring layer 30, so that the bottom of the contact hole 601 appears the interconnection metal
301。
In one embodiment, the semiconductor structure also has the peripheral region except the laminated construction 50a
13, when the wordline bonding pad 12 forms the contact hole 601, peripheral contact hole also is formed in the peripheral region 13 simultaneously
701, the bottom in the peripheral contact hole 701 appears the interconnection metal 301.
As shown in figure 12, step 6) S16 is then carried out, insulative sidewall 602 is formed in the contact hole 601 and filling is led
Electric support column 603, the conductive supporting column 603 connect the peripheral circuit, meanwhile, it is formed in the peripheral contact hole 701
Insulation division 702 and filling conductive part 703, the conductive part 703 connect the peripheral circuit.
For example, can be using such as chemical vapour deposition technique (CVD), physical vaporous deposition (PVD) or atomic layer deposition method
(ALD) etc. insulative sidewall 602 is formed in the contact hole 601, then opens 601 bottom of contact hole with dry etching method, is used
Such as physical vaporous deposition (PVD), chemical vapour deposition technique (CVD), atomic layer deposition method (ALD), galvanoplastic etc. connect described
Conductive supporting column 603 is filled in contact hole 601.The insulative sidewall 602 in the contact hole 601 includes silicon dioxide layer, institute
Stating the conductive supporting column 603 in contact hole 601 includes tungsten, titanium or titanium nitride.The conductive supporting column 603 on the one hand can be with
During subsequent removal sacrificial layer 501, laminated construction 50a is supported, and on the other hand can be used for the electrical property of peripheral circuit
It draws, uses the support construction without electrical functionality in wordline bonding pad 12 compared to traditional, wordline bonding pad can be efficiently used
12 area reduces the peripheral region 13 occupied needed for peripheral circuit is drawn, improves the integrated level and performance of three-dimensional storage.Into one
Step ground, 601 bottom of contact hole will not insert polysilicon and cause short circuit between the structures such as bottom grid layer 507 and dummy word line or
Electric leakage, can be improved the electrical stability of three-dimensional storage.
As shown in FIG. 13 and 14, step 7) is then carried out, the sacrificial layer 501 of the laminated construction 50a is removed,
Gap 506 is formed between the adjacent dielectric layer 502 and grid layer 507 is filled in the gap 506.
For example, removing the sacrificial layer 501 comprising steps of the core space 11 in the laminated construction 50a forms grid
Line separate slot 801 removes the sacrificial layer 501 using wet corrosion technique then by the grid line separate slot 801.In addition, one
In embodiment, the side wall further comprised the steps of: in the grid line separate slot 801 forms separation layer 802 and in the grid line separate slot 801
Middle filling conductive material layer 803.Multiple storage units can be divided into memory block by 801 one side of grid line separate slot
(block), on the other hand, circuit that common source line layer can be led to top can increase the flexible of circuit design and layout
Property.
As shown in figure 15, step 8) is finally carried out, forms wordline through-hole in the insulating layer 503, and in the wordline
Wordline conductive layer 901 is filled in through-hole, the wordline conductive layer 901 is connect with the grid layer 507 in the hierarchic structure,
To realize the extraction of the grid layer 507.
It should be noted that being first to be formed in channel hole 504 and channel hole 504 to tie in core space 11 in the examples described above
Then structure prepares structure in the contact hole 601 and contact hole 601 of wordline bonding pad 12 again.However, in other examples, it can also
Structure in contact hole 601 and contact hole 601 is formed in word line contact area with elder generation, then prepares channel hole 504 and the ditch of core space 11
Structure in road hole 504, the change of these order should be covered within scope of the present invention.
As described above, three-dimensional storage and preparation method thereof of the invention, has the advantages that
Three-dimensional storage provided by the invention and its manufacturing method, wordline bonding pad 12 using conductive supporting column 603 come
Laminated construction 50a is supported, and conductive supporting column 603 is drawn for the electrical of peripheral circuit simultaneously, compared to traditional
The support construction without electrical functionality is used in wordline bonding pad 12, the present invention can efficiently use the area of wordline bonding pad 12, subtract
The area for the peripheral region 13 that small peripheral circuit occupies needed for drawing, while the cost of manufacture that three-dimensional storage is effectively reduced,
Improve the integrated level and performance of three-dimensional storage.
The non-concurrent production of contact hole 601 in the channel hole 504 and wordline bonding pad 12 in core of the invention area 11, can be effective
Channel hole 504 is avoided to insert the polysilicon of out-of-flatness while filling polysilicon to contact hole 601, to avoid contact with hole 601
Bottom inserts polysilicon and causes the short circuit or electric leakage between the structures such as bottom grid layer 507 and dummy word line, improves three-dimensional storage
The electrical stability and yield of device.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (22)
1. a kind of three-dimensional storage characterized by comprising
Semiconductor structure, the semiconductor structure include peripheral circuit；
Stacked structure is located on the peripheral circuit, and the stacked structure includes core space and wordline bonding pad, the core space
With channel hole, memory film and channel layer are formed in the channel hole, the wordline bonding pad, which has, runs through the wordline
The contact hole of bonding pad, is formed with insulative sidewall and conductive supporting column in the contact hole, described in the conductive supporting column connection
Peripheral circuit.
2. three-dimensional storage according to claim 1, it is characterised in that: the stacked structure includes alternately stacked grid
The conductive supporting column and the grid layer is isolated in layer and dielectric layer, the insulative sidewall.
3. three-dimensional storage according to claim 2, it is characterised in that: the wordline bonding pad includes hierarchic structure, institute
It states and is covered with insulating layer in hierarchic structure, there is wordline through-hole in the insulating layer, led in the wordline through-hole filled with wordline
Electric layer, the wordline conductive layer are connect with the grid layer in the hierarchic structure.
4. three-dimensional storage according to claim 1, it is characterised in that: the insulative sidewall in the contact hole includes
Silicon dioxide layer, the conductive supporting column in the contact hole includes tungsten.
5. three-dimensional storage according to claim 1, it is characterised in that: the memory film includes that barrier layer, charge are caught
Obtain layer and tunnel layer, wherein the barrier layer is located at the sidewall surfaces in the channel hole, and the electric charge capture layer is located at the resistance
The surface of barrier, the tunnel layer are located at the surface of the electric charge capture layer, and the channel layer is located at the surface of the tunnel layer.
6. three-dimensional storage according to claim 1, it is characterised in that: shape between the peripheral circuit and the core space
At there is common source line layer, the common source line layer is connect with the peripheral circuit.
7. three-dimensional storage according to claim 6, it is characterised in that: the common source line layer includes metal layer and is located at
Doping semiconductor layer on the metal layer, the doping semiconductor layer and the metal layer form Ohmic contact.
8. three-dimensional storage according to claim 6, it is characterised in that: the bottom in the channel hole is formed with doped polycrystalline
Silicon layer, the channel layer are connect with the doped polysilicon layer, and the doped polysilicon layer is connect with the common source line layer.
9. three-dimensional storage according to claim 1, it is characterised in that: the core space is also formed with grid line separate slot, institute
The side wall for stating grid line separate slot is formed with separation layer, is filled with conductive material layer in the grid line separate slot, the conductive material layer with
The common source line layer connection.
10. three-dimensional storage according to claim 1, it is characterised in that: further include peripheral region, be located at the wordline and connect
Outside area, the peripheral region has peripheral contact hole, is formed with insulation division and conductive part, the conductive part in the peripheral contact hole
Connect the peripheral circuit.
11. three-dimensional storage according to claim 1, it is characterised in that: the peripheral circuit includes circuit layer and position
Wiring layer on the circuit layer.
12. a kind of production method of three-dimensional storage, which comprises the following steps:
Semiconductor structure is provided, the semiconductor structure has peripheral circuit；
Laminated construction is formed on the semiconductor structure, and the laminated construction includes core space and wordline bonding pad；
Channel hole is formed in the core space；
Memory film and channel layer are formed in the channel hole；
Contact hole is formed in the wordline bonding pad, the contact hole appears the peripheral circuit；
Insulative sidewall and filling conductive supporting column, the conductive supporting column connection periphery electricity are formed in the contact hole
Road.
13. the production method of three-dimensional storage according to claim 12, it is characterised in that: formed in the channel hole
Memory film and channel layer comprising steps of
Barrier layer is formed on the side wall in the channel hole；
Electric charge capture layer is formed on the barrier layer；
Tunnel layer is formed on the electric charge capture layer；
The channel layer is formed on the tunnel layer.
14. the production method of three-dimensional storage according to claim 12, it is characterised in that: further comprise the steps of:
Common source line layer, the common source line layer and the peripheral circuit are formed between the peripheral circuit and the core space
Connection.
15. the production method of three-dimensional storage according to claim 14, which is characterized in that form the common source line layer
Comprising steps of
Metal layer is formed on the peripheral circuit；
Doping semiconductor layer is formed on the metal layer, and the doping semiconductor layer and the metal layer form Ohmic contact.
16. the production method of three-dimensional storage according to claim 12, it is characterised in that: further comprise the steps of:
Doped polysilicon layer, and the channel layer being subsequently formed and the DOPOS doped polycrystalline silicon are formed in the bottom in the channel hole
Layer contact.
17. the production method of three-dimensional storage according to claim 12, it is characterised in that: the laminated construction includes handing over
For the dielectric layer and sacrificial layer of stacking, the production method is further comprised the steps of:
The sacrificial layer for removing the laminated construction forms gap between the adjacent dielectric layer；
Grid layer is filled in the gap.
18. the production method of three-dimensional storage according to claim 17, it is characterised in that: removing the sacrificial layer includes
Step:
Grid line separate slot is formed in the core space of the laminated construction；
By the grid line separate slot, the sacrificial layer is removed using wet corrosion technique.
19. the production method of three-dimensional storage according to claim 18, it is characterised in that: further comprise the steps of:
Separation layer is formed in the side wall of the grid line separate slot；
Conductive material layer is filled in the grid line separate slot.
20. the production method of three-dimensional storage according to claim 12, it is characterised in that: the laminated construction it is described
Dielectric layer includes silicon dioxide layer, and the sacrificial layer of the laminated construction includes silicon nitride layer, described in the contact hole
Insulative sidewall includes silicon dioxide layer, and the conductive supporting column in the contact hole includes tungsten.
21. the production method of three-dimensional storage according to claim 12, it is characterised in that: the semiconductor structure also has
There is the peripheral region being located at except the laminated construction, the production method further comprises the steps of:
When the wordline bonding pad forms the contact hole, peripheral contact hole is formed in the peripheral region；
When forming the insulative sidewall in the contact hole and filling the conductive supporting column, the shape in the peripheral contact hole
The peripheral circuit is connected at insulation division and filling conductive part, the conductive part.
22. the production method of three-dimensional storage according to claim 12, it is characterised in that: the peripheral circuit includes electricity
Road floor and the wiring layer on the circuit layer.
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Application publication date: 20190514 |