CN111952318A - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN111952318A CN111952318A CN202010842239.9A CN202010842239A CN111952318A CN 111952318 A CN111952318 A CN 111952318A CN 202010842239 A CN202010842239 A CN 202010842239A CN 111952318 A CN111952318 A CN 111952318A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Abstract
The invention provides a three-dimensional memory and a manufacturing method thereof. The manufacturing method of the three-dimensional memory comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, and an insulating layer, a conductor layer and a stacking layer which are sequentially arranged on the substrate, and the conductor layer is provided with a peripheral area which is not covered by the stacking layer; forming a first via hole vertically penetrating the conductor layer to the insulating layer; forming a spacer in the first via; and forming a first conductive portion in the first through hole, the spacer being provided between the conductor layer and the first conductive portion. The method can realize the isolation of the conductor layer and the conductive part without additional mask plates.
Description
Technical Field
The invention mainly relates to the field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.
Background
With the continuous improvement of the storage density requirement of the market, the key size reduction of the two-dimensional memory reaches the limit of the mass production technology, and in order to further improve the storage capacity and reduce the cost, the memory with the three-dimensional structure is provided.
To increase memory density, it is common to increase the number of stacked layers in a three-dimensional memory. In the currently mainstream three-dimensional memory device of the 3D NAND flash memory, as the number of stacked layers of the memory array structure is continuously increased, the difficulty of performing a silicon-Oxide-Nitride-Oxide (Si, Oxide, Nitride, Oxide, SONO) etching process on the bottom of a channel hole in the stacked layers is increased.
Some improved solutions use alternative structures, such as SWNN (Side Wall N-poly/N-Sub) structures to avoid SONO etching processes. The SWNN structure includes a conductive layer, and when a peripheral contact portion in the stacked layers passes through the conductive layer, a short circuit is generated, and thus, it is necessary to isolate the conductive portion. It is conventional to form a via hole in a conductor layer and fill an insulating layer in advance through additional steps. This requires additional etching and masking, which increases costs.
Disclosure of Invention
The invention provides a three-dimensional memory and a manufacturing method thereof, which can realize the isolation of a conductor layer and a conductive part under the condition of not needing an additional mask plate.
In order to solve the above technical problem, the present invention provides a method for manufacturing a three-dimensional memory, comprising the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, and an insulating layer, a conductor layer and a stacking layer which are sequentially arranged on the substrate, and the conductor layer is provided with a peripheral area which is not covered by the stacking layer; forming a first via hole vertically penetrating the conductor layer to the insulating layer; forming a spacer in the first via; and forming a first conductive portion in the first through hole, the spacer being provided between the conductor layer and the first conductive portion.
In an embodiment of the invention, the insulating layer includes an etch stop layer, wherein the first via hole is formed to stop on the etch stop layer.
In an embodiment of the invention, the method further includes forming a second conductive portion vertically penetrating the insulating layer, wherein the second conductive portion is electrically connected to the first conductive portion.
In an embodiment of the invention, the step of forming the second conductive portion includes: removing the substrate and thinning the insulating layer; forming a protective layer on the insulating layer; forming a second through hole penetrating to the first conductive portion from the back surface of the protective layer; forming the second conductive portion in the second via hole.
In an embodiment of the present invention, the conductor layer includes a first sublayer, a second sublayer and a third sublayer, the second sublayer is located between the first sublayer and the third sublayer, the second sublayer is a sacrificial layer or a contact layer, and the contact layer is configured to contact a sidewall of a channel layer vertically passing through the stacked layer.
In an embodiment of the invention, the first sublayer and the third sublayer are doped polysilicon layers, the sacrificial layer is undoped polysilicon, and the contact layer is doped polysilicon.
In one embodiment of the present invention, the peripheral region is adjacent to the word line connection region of the stacked layers.
The invention also provides a three-dimensional memory, which comprises an insulating layer, a conductor layer, a stacked layer, a channel structure and a first through hole. The conductor layer is arranged on the insulating layer. The stack layer is disposed on the conductor layer, the stack layer having a core region, wherein the conductor layer has a peripheral region not covering the stack layer. The channel structure is disposed on the core region and through the stacked layers to the conductor layer. A first via vertically penetrates the conductor layer to reach the insulating layer, and a spacer and a first conductive portion are provided in the via.
In an embodiment of the invention, the three-dimensional memory further includes a second conductive portion vertically penetrating the insulating layer and electrically connected to the first conductive portion.
In an embodiment of the present invention, the conductor layer includes a first sublayer, a second sublayer and a third sublayer, the second sublayer is located between the first sublayer and the third sublayer, the second sublayer is a contact layer, and the contact layer is in contact with a sidewall of a channel layer of the channel structure.
In an embodiment of the invention, the first to third sublayers are doped polysilicon layers.
In an embodiment of the invention, the doping types of the first to third sublayers are the same.
In an embodiment of the invention, the first conductive part is electrically connected to a peripheral circuit.
Compared with the prior art, the invention can realize insulation by adding the clearance wall after the through hole is formed in the three-dimensional memory, thereby saving the extra step of forming isolation in the conductor layer and saving the corresponding mask.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the principle of the invention. In the drawings:
fig. 1 is a flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
Fig. 2A-2F are cross-sectional views of an exemplary fabrication process for a three-dimensional memory in an embodiment of the present application.
FIG. 3 is a partial schematic view of a three-dimensional memory according to an embodiment of the present application.
Fig. 4 is a partial schematic diagram of a three-dimensional memory as a comparison.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the scope of the present application; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.
Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.
Embodiments of the present disclosure describe a three-dimensional memory and a method of manufacturing the same that can achieve isolation of a conductor layer from a conductive portion without requiring an additional mask. Fig. 1 is a flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. Fig. 2A-2F are cross-sectional views of an exemplary fabrication process for a three-dimensional memory in an embodiment of the present application. The method of forming the three-dimensional memory of the present embodiment is described below with reference to fig. 1 to 2F.
At step 102, a semiconductor structure is provided.
Here, the semiconductor structure may include a substrate, and an insulating layer, a conductor layer, and a stacked layer sequentially provided on the substrate. The conductive layer has a peripheral region not covered by the stacked layers.
Referring to fig. 2A, a semiconductor structure 200 may include a substrate 201, an insulating layer 202, a conductor layer 204, and a stack layer 210. In the semiconductor structure, a core region (not shown), a word line connection region 205, and a peripheral region 206 may be defined on a substrate 201.
In an embodiment of the present application, the material of the substrate 201 is, for example, silicon. Various well regions may also be formed in the substrate 201 as desired. Further, for example, the substrate 201 may be another silicon-containing substrate, such as SOI (silicon on insulator), SiGe, Si: C, or the like.
The insulating layer 202 is located on the substrate 201 and functions to separate the substrate 201 from the conductive layer 204. The material of the insulating layer 202 is, for example, silicon oxide. In one embodiment, an etch stop layer 203 may be included in the insulating layer 202 for subsequent processing to stop the etch. Etch stop layer 203 is a material with a high etch selectivity to silicon oxide, such as silicon nitride.
A conductive layer 204 is located over the insulating layer 202. The conductive layer 204 is a part of an SWNN (Side Wall N-poly/N-Sub) structure. Typically, the conductor layer 204 includes a first sub-layer 204a, a second sub-layer 204b, and a third sub-layer 204 c. The second sublayer 204b is located between the first sublayer 204a and the third sublayer 204 c. The first sublayer 204a and the third sublayer 204c are etch stop layers. The second sub-layer 204b may be a sacrificial layer or a contact layer. In an embodiment of the present application, the first sub-layer 204a and the third sub-layer 204c are doped polysilicon layers. When the second sub-layer 204b is a sacrificial layer, an undoped polysilicon material may be selected. In one embodiment, the portion of the sacrificial layer 204b in the peripheral region 206 may be removed and replaced with doped polysilicon material to form a contact layer. In another embodiment, a portion of the sacrificial layer 204b in the peripheral region 206 may be left as an undoped polysilicon material.
When the second sub-layer 204b is a contact layer, a doped polysilicon material may be used. The first sub-layer 204a and the third sub-layer 204c are doped N-type with a doping concentration of 1 × 1018-1×1022/cm-3And 1X 1019-1×1022cm-3. When the second sub-layer 204b is a contact layer, the doping type is N-type doping with a doping concentration of 1 × 1019-1×1022/cm-3. In other words, the doping types of the first to third sublayers 204a to 204c are the same.
A stack layer 210 and a plurality of channel structures (not shown) vertically crossing the stack layer 210 are formed on the core region 205 and the word line connection regions 205. The peripheral region 206 is not covered by the stack 210 but is covered by the insulating layer 215. The peripheral region 206 is adjacent to the word line connection region 205. The word line connection region 205 may be a stepped structure as shown in fig. 2A.
In other embodiments, the word line connection region 205 may also be a planar structure.
The stack layer 210 may be a stack in which first material layers 211 and second material layers 212 are alternately stacked. The first material layer 211 may be a gate layer. The second material layer 212 is an insulating layer. The first material layer 211 includes, for example, a metal material such as tungsten (W), titanium (Ti), or platinum (Pt), or a non-metal conductive material such as doped polysilicon. The second material layer 212 is an insulating material such as silicon oxide or silicon oxynitride. It is understood that the stacked layers 210 herein may comprise a single or multiple stacks (deck). The gate layer in each step of the word line connection region 205 may be drawn out through the contact portion 213. The contact 213 may be a metal material such as tungsten. Before forming the contact 213, an adhesive layer 214 is preferably formed. The adhesive layer 213 may help the contact portion 213 to adhere better to the surrounding material. The bonding layer 214 may be a material such as titanium nitride (TiN).
A plurality of channel structures, including a memory layer and a channel layer, are disposed in the stacked layer 210 perpendicular to the surface of the substrate 201 and reaching the conductor layer 204. The memory layer may include a blocking layer, a charge trapping layer, and a tunneling layer disposed from outside to inside between the channel layer and a channel hole in which the channel structure is located. The details of this structure are not important to the present application and will not be described further herein. The sidewall of the channel layer in the second sub-layer 204b is in contact with the second sub-layer 204b as a contact layer.
In step 104, a first via is formed vertically through the conductor layer to the insulating layer.
In this step, a first via is formed in the peripheral region, penetrating the conductor layer to reach the insulating layer.
Referring to fig. 2B, a first via 216 extends from the insulating layer 215 down through the conductor layer 204 to the insulating layer 202. When the insulating layer 202 includes the etch stop layer 203, the first via hole 216 is formed to stop on the etch stop layer 203. The number of the first through holes 216 in fig. 2B is merely an example, and the number of the first through holes 216 is not limited in the present embodiment.
At step 106, spacers are formed in the first via.
In this step, spacers are formed in the first via to separate the contact to be formed later from the other material of the via sidewalls.
First, as shown in fig. 2C, a spacer 217 is formed in the first via hole 216. The spacer 217 covers the sidewalls and the bottom of the first via hole 216. The spacer 217 may be formed by chemical vapor deposition or atomic layer deposition. Next, as shown in fig. 2D, the spacer 217a at the bottom of the first through hole 216 is removed, and only the spacer 217 of the sidewall remains. This step can be performed by, for example, dry etching. The material of the spacer 217 is, for example, silicon oxide or silicon oxynitride.
At step 108, a first conductive portion is formed in the first via.
In this step, a first conductive portion is formed vertically through the stack layer to the insulating layer.
As shown in fig. 2E, the first conductive portion 218 is located in the first via and reaches the etch stop layer 202. The first conductive portion 218 may be a metal material such as tungsten. Before forming the first conductive portion 218, an adhesive layer 219 is preferably formed. The adhesive layer 219 may help the first conductive portion 218 to better adhere in the surrounding material. The bonding layer 219 may be a material such as titanium nitride (TiN). . A spacer 217 is disposed between the first conductive portion 218 and the conductive layer 204 to separate them. Here, the spacer 217 may cover only the sidewall adjacent to the conductor layer 204 in the first via hole 216, and does not necessarily cover the entire first via hole sidewall.
In step 110, a second conductive portion is formed to vertically penetrate the insulating layer and electrically connect the first conductive portion.
In this step, the insulating layer is vertically penetrated from the back side of the substrate to form a second conductive part, and the second conductive part is electrically connected with the first conductive part.
Referring to fig. 2F, the second conductive portion 219 penetrates the insulating layer 202' from the back surface (lower surface in the figure) side to electrically connect with the first conductive portion 221. The second conductive portion 221 may be a metal material such as tungsten. Before forming the first conductive portion 221, an adhesive layer 222 is preferably formed. The adhesive layer 222 may help the second conductive portion 221 to adhere better in the surrounding material. The bonding layer 222 may be a material such as titanium nitride (TiN).
On the other hand, at the same time as the second conductive portions 219, third conductive portions 223 are formed, which are the third sub-layers 204c in the bottom conductor layer 204. The third conductive portion 223 serves as a lead-out portion of the N-well. Before the third conductive portion 223 is formed, an adhesive layer 224 is preferably formed. The adhesive layer 224 may help the second conductive portion 223 to better adhere in the surrounding material. The bonding layer 224 may be a material such as titanium nitride (TiN).
Step 110 may include some conventional processes such as removing the substrate 201 and thinning the insulating layer 202. A protective layer is formed over the insulating layer 202 to form a new insulating layer 202'. A second via is formed from the back side of the protective layer 202' to the first conductive portion 218. A second conductive portion 219 is then formed in the second via hole.
In addition to the steps 102-110, a three-dimensional memory is formed through conventional steps.
FIG. 3 is a partial schematic view of a three-dimensional memory according to an embodiment of the present application. Referring to fig. 3, the three-dimensional memory according to an embodiment of the present invention may define a core region 207, a word line connection region 205, and a peripheral region 206. The three-dimensional memory may include an insulating layer 202', a conductive layer 204, and a stacked layer 210. Insulating layer 202' may cover core region 207, word line connection region 205, and peripheral region 206. A conductive layer 204 is disposed on the insulating layer 202' and also covers the core region 207, the word line connection region 205, and the peripheral region 206. The stacked layer 210 is disposed on the conductive layer 204 and covers the core region 207 and the word line connection region 205, and the stacked layer 210 does not cover the peripheral region 206 of the conductive layer 204. The stack layer 210 forms a stepped structure at the word line connection region 205.
The periphery region 206 of the three-dimensional memory has a first via that extends vertically through the conductive layer 204 to the insulating layer 202', and the first via has a spacer 219 and a first conductive portion 218 therein.
The three-dimensional memory may have a second conductive portion 221 electrically connected to the first conductive portion 218 from the backside of the insulating layer 202'. In the extending direction of the insulating layer 202', the characteristic dimension of the second conductive portion 221 is smaller than the characteristic dimension of the first conductive portion 218.
The conductive layer 204 is part of an SWNN (Side Wall N-poly/N-Sub) structure. Typically, the conductor layer 204 includes a first sub-layer 204a, a second sub-layer 204b, and a third sub-layer 204 c. The second sublayer 204b is located between the first sublayer 204a and the third sublayer 204 c. In the core region 207, the second sub-layer 204b is a contact layer for contacting the channel layers 220 in the respective channel structures 220. The material of the second sub-layer 204b at the peripheral region 206 may be the same as the material at the core region 207. Alternatively, the material of the second sub-layer 204b at the peripheral region 206 may be different from the material at the core region 207, while still remaining as the material of the sacrificial layer. In the embodiment of the present application, the first sub-layer 204a and the third sub-layer 204c are doped polysilicon layers, the doping type is N-type doping, and the doping concentrations are 1 × 1018-1×1022/cm-3And 1X 1019-1×1022/cm-3. The material of the second sub-layer 204b in the core region 207 may be doped polysilicon, the doping type is N-type doping, and the doping concentration is 1 × 1019-1×1022/cm-3. The material of the second sub-layer 204b in the peripheral region 206 may be doped polysilicon, the doping type is N-type doping, and the doping concentration is 1 × 1019-1×1022/cm-3Or undoped polysilicon.
In core region 207, conductor layer 204 may directly contact the channel layer in the channel hole without the need for silicon formed by selective epitaxial growth at the bottom of the channel hole. Therefore, the 3D NAND SONO etching process can be omitted. Compared with the conventional 3D NAND SONO etching process, SWNN can reduce SONO etching challenges due to increased layer number, such as large variation in alignment margin (alignment margin) and pressure, and increase the process window of 3D NAND. Fig. 4 is a partial schematic diagram of a three-dimensional memory as a comparison. Referring to fig. 4, the three-dimensional memory device may include an insulating layer 402, a conductive layer 404, and a stack layer 410. A conductive layer 404 is disposed on the insulating layer 402. The stack layer 410 is disposed on the conductive layer 404. An annular gap 412 is formed in the peripheral region of the conductive layer 404 and filled with an insulating material. The peripheral region of the three-dimensional memory forms a first conductive portion 414 that vertically penetrates from the front surface and reaches the conductor layer 204, and forms a second conductive portion 416 that vertically penetrates from the back surface and reaches the conductor layer 204. Here, additional steps and reticles are required to etch the annular gap 412. Compared with the scheme of the embodiment of the application, the step of etching the annular gap 412 and the corresponding mask can be saved.
In the context of the present invention, the three-dimensional memory device may be a 3D flash memory, such as a 3D NAND flash memory.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Although the present application has been described with reference to the present specific embodiments, it will be recognized by those skilled in the art that the foregoing embodiments are merely illustrative of the present application and that various changes and substitutions of equivalents may be made without departing from the spirit of the application, and therefore, it is intended that all changes and modifications to the above-described embodiments that come within the spirit of the application fall within the scope of the claims of the application.
Claims (13)
1. A method of fabricating a three-dimensional memory, comprising the steps of:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, and an insulating layer, a conductor layer and a stacking layer which are sequentially arranged on the substrate, and the conductor layer is provided with a peripheral area which is not covered by the stacking layer;
forming a first via hole vertically penetrating the conductor layer to the insulating layer;
forming a spacer in the first via; and
and forming a first conductive part in the first through hole, wherein the clearance wall is arranged between the conductor layer and the first conductive part.
2. The method of claim 1, wherein the insulating layer comprises an etch stop layer, wherein the first via is formed stopping on the etch stop layer.
3. The method of claim 1, further comprising forming a second conductive portion extending vertically through the insulating layer, the second conductive portion electrically connecting the first conductive portion.
4. The method of claim 3, wherein the step of forming the second conductive portion comprises:
removing the substrate and thinning the insulating layer;
forming a protective layer on the insulating layer;
forming a second through hole penetrating to the first conductive portion from the back surface of the protective layer;
forming the second conductive portion in the second via hole.
5. The method of claim 1, wherein the conductor layer comprises a first sublayer, a second sublayer and a third sublayer, the second sublayer located between the first sublayer and the third sublayer, the second sublayer being a sacrificial layer or a contact layer for contacting a sidewall of the channel layer vertically through the stacked layers.
6. The method of claim 5, wherein the first and third sub-layers are doped polysilicon layers, the sacrificial layer is undoped polysilicon, and the contact layer is doped polysilicon.
7. The method of claim 1, wherein the peripheral region is adjacent to a word line connection region of the stacked layers.
8. A three-dimensional memory, comprising:
an insulating layer;
a conductor layer disposed on the insulating layer;
a stack layer disposed on the conductor layer, the stack layer having a core region, wherein the conductor layer has a peripheral region not covered by the stack layer;
a channel structure disposed on the core region and through the stacked layers to the conductor layer; and
and a first via hole vertically penetrating the conductor layer to reach the insulating layer, the via hole having a spacer and a first conductive portion therein.
9. The three-dimensional memory according to claim 8, further comprising a second conductive portion vertically penetrating the insulating layer and electrically connected to the first conductive portion.
10. The three-dimensional memory of claim 8, wherein the conductor layer comprises a first sublayer, a second sublayer, and a third sublayer, the second sublayer located between the first sublayer and the third sublayer, the second sublayer being a contact layer in the core region, the contact layer contacting a channel layer sidewall of the channel structure.
11. The three-dimensional memory according to claim 10, wherein the first to third sublayers are doped polysilicon layers.
12. The three-dimensional memory according to claim 11, wherein the doping types of the first to third sublayers are the same.
13. The three-dimensional memory according to claim 8, wherein the first conductive portion is configured to electrically connect to a peripheral circuit.
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