CN106992182B

CN106992182B - Memory device, method of manufacturing the same, and electronic apparatus including the same

Info

Publication number: CN106992182B
Application number: CN201710273427.2A
Authority: CN
Inventors: 朱慧珑
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2017-04-24
Filing date: 2017-04-24
Publication date: 2020-06-09
Anticipated expiration: 2037-04-24
Also published as: CN106992182A

Abstract

A memory device, a method of manufacturing the same, and an electronic apparatus including the memory device are disclosed. According to an embodiment, a memory device may include a plurality of pillar-shaped active regions formed on a substrate and extending upward from the substrate; and a plurality of gate electrode layers which are sequentially arranged on the substrate from bottom to top, are spaced from each other and respectively surround the columnar active regions, wherein each gate electrode layer faces each columnar active region through the storage gate dielectric stack, the columnar active regions comprise first doping regions opposite to each gate electrode layer and second doping regions positioned at two opposite sides of each first doping region, and the doping characteristics in the first doping regions are different from the doping characteristics in the second doping regions.

Description

Memory device, method of manufacturing the same, and electronic apparatus including the same

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to a vertical device-based memory device, a method of manufacturing the same, and an electronic device including such a memory device.

Background

In a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a source, a gate, and a drain are arranged in a direction substantially parallel to a surface of a substrate. Due to this arrangement, the horizontal type device is not easily further downsized. Unlike this, in the vertical type device, the source, the gate, and the drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, vertical devices are more easily scaled down relative to horizontal devices.

In a memory device based on a vertical type device, there are memory cells stacked so that their respective resistances are connected in series. Thus, the total resistance increases, and the memory device performance deteriorates. Since the active regions (including the channel region and the source/drain regions) are generally integrally formed in the conventional vertical type memory device, the dopant type and concentration in the channel region and the source/drain regions are substantially the same. Therefore, it is difficult to reduce the total resistance by increasing the doping concentration of the source/drain regions, since this also increases the doping concentration in the channel region, resulting in an increase in leakage current between the source and drain regions.

Disclosure of Invention

In view of the above, it is an object of the present disclosure, at least in part, to provide a vertical device-based memory device, a method of manufacturing the same, and an electronic device including the same, in which a doping type/concentration can be adjusted for a channel region and a source/drain region, respectively.

According to an aspect of the present disclosure, there is provided a memory device including: a plurality of pillar-shaped active regions formed on the substrate and extending upward from the substrate; and a plurality of gate electrode layers which are sequentially arranged on the substrate from bottom to top, are spaced from each other and respectively surround the columnar active regions, wherein each gate electrode layer faces each columnar active region through the storage gate dielectric stack, the columnar active regions comprise first doping regions opposite to each gate electrode layer and second doping regions positioned at two opposite sides of each first doping region, and the doping characteristics in the first doping regions are different from the doping characteristics in the second doping regions.

According to another aspect of the present disclosure, there is provided a method of manufacturing a memory device, including: providing an alternating stack of dopant source layers and gate electrode layers on a substrate, wherein the dopant source layers comprise a type of dopant; forming a plurality of holes in the stack; filling the hole with a semiconductor material and performing heat treatment to drive dopants from the dopant source layer into the semiconductor material; and forming a storage gate dielectric stack between the gate electrode layer and the semiconductor material.

According to another aspect of the present disclosure, there is provided an electronic device including the above memory device.

According to embodiments of the present disclosure, different regions of the active region (e.g., the channel region and the source/drain regions) may be doped differently and thus may have different doping characteristics. For example, the source/drain regions may be further doped using a solid phase dopant source of dielectric as a diffusion source to increase the doping concentration therein, thereby reducing the resistance of the source/drain regions and, thus, the overall series resistance of the stacked memory cells. Thus, the number of memory cells stacked can be increased, and thus the integration density can be increased.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

1-10 illustrate schematic diagrams of a process flow for fabricating a memory device according to an embodiment of the present disclosure;

FIGS. 11 and 12 show a flow diagram for a middle staging of a flow for fabricating a memory device according to another embodiment of the present disclosure;

fig. 13 and 14 show a flow chart of a middle staging of a flow of fabricating a memory device according to yet another embodiment of the present disclosure.

Throughout the drawings, the same or similar reference numerals denote the same or similar components.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

The memory device according to the embodiments of the present disclosure is based on a vertical type device, and thus may include a plurality of pillar-shaped active regions formed on a substrate to extend upward (e.g., substantially perpendicular to a surface of the substrate) from the substrate. The columnar active region may be solid or hollow (in which a dielectric may be filled). Vertical devices may be formed based on these vertically extending columnar active regions by forming gate stacks around their peripheries. The gate stack may be a memory gate stack in order to implement a memory function. For example, the gate stack may include a storage gate dielectric stack formed on at least a portion of an outer wall of the columnar active region and a gate electrode layer facing the columnar active region via the storage gate dielectric stack. The gate electrode layer extends in a direction intersecting with the extending direction of the columnar active region (e.g., substantially parallel to the substrate surface) so as to intersect with the columnar active region, and thus can define a channel region in the columnar active region (and accordingly define a source/drain region, i.e., a portion of the active region on opposite sides of the channel region). A conductive path may be formed between the source/drain regions through the channel region.

A plurality of gate electrode layers may be provided, arranged in sequence from bottom to top, spaced apart from each other and surrounding each respective columnar active region, so as to define a plurality of channel regions in each respective columnar active region (and thus a plurality of memory cells, each memory cell including a respective channel region and source/drain regions on opposite sides of the channel region). Respective source/drain regions of upper and lower adjacent memory cells may be connected together (e.g., physically integrated). Here, the memory unit may be a flash memory (flash) unit.

The columnar active regions may be arranged in an array (e.g., a two-dimensional array that is typically arranged in rows and columns). In addition, the memory devices may be three-dimensional (3D) arrays because they vertically extend over the substrate and define multiple layers of memory cells through multiple layers of gate electrode layers, respectively, as described above. In the 3D array, each columnar active region defines a string of memory cells.

In this context, the term "memory gate dielectric stack" refers to the portion of the memory gate stack between the gate electrode layer and the active region (or channel region). The stack as a whole exhibits dielectric properties, i.e. such that the gate electrode layer is not in direct electrical connection with the channel region, and is thus referred to as a "dielectric" stack, but this does not exclude the possibility of one or more conductive layers being comprised in the stack. The storage gate dielectric stack may include a charge trapping layer, a floating gate layer, or a ferroelectric material, etc. to perform a storage function. For example, the storage gate dielectric stack may include a first gate dielectric layer, a floating gate layer or charge trapping layer, and a second gate dielectric layer, which are sequentially stacked, or may include a first metal layer, a ferroelectric material layer, a second metal layer, and a gate dielectric layer. There are various memory gate stack configurations in the art that can implement the memory function and are not described in detail herein.

The columnar active region may include a first doped region opposite to each gate electrode layer and a second doped region on opposite sides of each first doped region. For example, the first doped region may correspond to a channel region and the second doped region may correspond to a source/drain region. According to an embodiment of the present disclosure, a doping characteristic in the first doping region may be different from a doping characteristic in the second doping region. Here, the "different doping characteristics" means that there is a difference in at least one of the doping concentration and the doping type. For example, there may be at least one of the following: (1) the doping concentration in the first doping region is different from the doping concentration in the second doping region; (2) the doping type in the first doping area is different from the doping type in the second doping area; (3) the doping concentration in the first doping region is different from the doping concentration in the second doping region, and the doping type in the first doping region is different from the doping type in the second doping region.

According to the embodiments of the present disclosure, the doping concentration in the second doping region may be increased (at the same time, the doping concentration in the first doping region may be kept relatively small to avoid an increase in leakage current). Thus, the total series resistance of the memory cells stacked on top of each other can be reduced.

According to embodiments of the present disclosure, the semiconductor material in the columnar active region may be homogenous (e.g., a common silicon material), and a desired doping profile may be achieved in the columnar active region by doping differently. For example, a relatively high doping concentration in the second doping region may be achieved by driving dopants into the columnar active region from a dopant source layer (and thus aligned with the location of the source/drain regions) disposed between the gate electrode layers.

Such a memory device can be manufactured, for example, as follows. In particular, an alternating stack of dopant source layers and gate electrode layers may be provided on a substrate. The stack may have a dopant source layer at the bottom and a dopant source layer at the top. The dopant source layer may be a dielectric layer containing a type and concentration of dopant therein. For example, the dopant may be introduced into the dopant source layer by in-situ doping thereof when forming it, for example, upon deposition. A diffusion barrier layer may also be formed in each dopant source layer and each gate electrode layer to inhibit undesired diffusion of dopants in the dopant source layers.

Then, several holes may be formed in the stack. Active regions (corresponding to the shape of the holes and thus may be "columnar," including but not limited to columnar) will then be formed in these holes. These holes may extend in the stacking direction (vertical direction) of the stack and may extend through the stack. In the following process, these holes are machining passages.

A memory gate dielectric stack may be formed on the sidewalls of the hole at least where it corresponds to the gate electrode layer. The memory gate dielectric stack thus formed, together with the gate electrode layer, forms a memory gate stack. The holes may then be filled (doped) with a semiconductor material to form (pillar) active regions. The semiconductor material may completely fill the hole to form a solid pillar-shaped active region, or may be formed only along the inner wall of the hole to form a hollow pillar-shaped active region (the inner side may be further filled with a dielectric layer). The active region cooperates with each memory gate stack to form a memory cell.

Subsequently, a thermal treatment may be performed to drive dopants from the dopant source layer into the semiconductor material. Due to the dopants from the dopant source layer, the doping concentration in the portion (source/drain region) of the columnar active region corresponding to the dopant source layer will increase, and thus the resistance of the source/drain region can be reduced.

In addition to changing the doping profile in the active region by driving dopants from the dopant source layer, the doping profile in the channel region may be individually adjusted in accordance with embodiments of the present disclosure. This may be achieved, for example, by forming (at least part of) the channel region separately. For this reason, some processing may be performed on a portion where the channel region is to be formed (i.e., a position where the gate electrode layer is located). For example, the gate electrode layer may be selectively etched through the hole so as to be recessed to some extent. These recesses may then accommodate the channel region. Depending on the manufacturing process, the semiconductor material for the channel region may be filled (which may typically be lightly doped) only in these recesses. Such filling may be performed, for example, as follows. In particular, the holes may be filled with a semiconductor material via the holes (e.g., simultaneously with in situ doping). During the filling, the semiconductor material can likewise enter the recesses. The filled semiconductor material may then be etched back via the holes. In this way, semiconductor material may be left in the recess, while semiconductor material in the hole is substantially removed. The holes may then be filled with a semiconductor material forming other parts of the active region (which may be doped differently, for example, may be moderately doped in order to adjust the threshold voltage). The active region thus formed may be heavily doped at the source/drain regions after receiving the dopants driven from the dopant source layer.

In conjunction with this process, the memory gate dielectric stack may also be confined to the channel region rather than being formed over the entire inner wall of the hole. For example, after filling the recess with the semiconductor material, the storage gate dielectric stack may be selectively etched using the filled semiconductor material as a mask, so that the storage gate dielectric stack only remains under the semiconductor material (i.e., only remains at the channel region).

The present disclosure may be presented in various forms, some examples of which are described below.

Fig. 1-10 show schematic diagrams of a process flow for fabricating a memory device according to an embodiment of the present disclosure.

As shown in fig. 1, a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, a bulk Si substrate is described as an example for convenience of explanation.

In the substrate 1001, a well region 1001w is formed, for example, by ion implantation. This well region 1001w may then serve as a common ground potential plane for the memory device to which the source/drain regions underlying respective ones of the lowermost memory cells in the memory device may be connected. If the memory cell is an n-type device, well region 1001w may be doped n-type; well region 1001w may be doped p-type if the memory cell is a p-type device.

Over the substrate 1001, a first dopant source layer 1003, a first gate electrode layer 1005, a second dopant source layer 1007, a second gate electrode layer 1009, and a third dopant source layer 1011 may be formed in this order by, for example, deposition. The first, second, and third dopant source layers 1003, 1007, 1011 may each comprise a suitable dielectric material, such as an oxide, and contain a type of dopant (e.g., p-type dopant for p-type devices and n-type dopant for n-type devices) having a thickness of about 20-50 nm. Dopants may be introduced into the dopant source layer at the same time as the formation of the dopant source layer, for example, by in situ doping. In one example, each dopant source layer may comprise n-type doped phosphosilicate glass (PSG) or arsenic silicate glass (AsSG) for n-type devices, or p-type doped borosilicate glass (BSG) for p-type devices, and may contain dopants at a concentration of about 0.01-10%. The first gate electrode layer 1005 and the second gate electrode layer 1009 may comprise a suitable gate electrode material such as doped polysilicon or metal, and may have a thickness of about 10-100 nm. The steps of forming the gate electrode layer and the dopant source layer may be repeated until a desired number of layers are formed.

In addition, a hard mask may also be formed over the grown layers for the purpose of convenience of patterning in subsequent processing, providing an appropriate stop layer, and the like. For example, a nitride (e.g., silicon nitride) layer 1015 may be formed, for example, to a thickness of about 10-100 nm.

Subsequently, the location of the active region can be defined. As shown in the top view of fig. 2, the substrate may include a memory cell region in which memory cells may be formed and a contact region in which various electrical contacts may be formed. Of course, the substrate may also include other areas, such as circuit areas for forming associated circuitry, etc. In the memory cell region, a photoresist 1017 may be formed on the structure shown in fig. 1. By photolithography (exposure and development), the photoresist 1017 is patterned into the nitride layer 1015 exposed at the position of the active region. The layout of the holes depends on the layout of the memory cells, for example, the holes may be arranged in rows and columns in a two-dimensional array.

Next, as shown in FIG. 3 (cross-sectional view along line AA' in FIG. 2), a hole may be opened downward through the photoresist. Specifically, the nitride layer 1015, the third dopant source layer 1011, the second gate electrode layer 1009, the second dopant source layer 1007, the first gate electrode layer 1005, and the first dopant source layer 1003 may be selectively etched, for example, in this order, to form a hole. For example, the RIE may be performed in a direction substantially perpendicular to the substrate surface, resulting in holes extending in a direction substantially perpendicular to the substrate surface. After that, the photoresist 1017 may be removed. In this example, the hole may penetrate through the stack of the gate electrode layer and the dopant source layer.

Here, the hole is illustrated as a circle, but the present disclosure is not limited thereto. The holes may be of any shape suitable for machining.

Then, as shown in fig. 4, the

gate electrode layers

1005, 1009 may be selectively etched (with respect to the dopant source layers) via the holes. For example, a suitable etchant may be selected that etches the gate electrode layer (much) more than the dopant source layer. Accordingly, the

gate electrode layers

1005, 1009 may be recessed with respect to the dopant source layers 1003, 1007, 1011 in order to provide a space to accommodate (at least a portion of) the channel region. Here, the amount of etching can be controlled so that the recesses formed in the

gate electrode layers

1005 and 1009 have a ring shape surrounding the holes without communication between the holes.

Thereafter, as shown in fig. 5, a storage gate dielectric stack 1019 can be formed on the inner wall of the hole. For example, layers of the memory gate dielectric stack (the arrangement of layers in the stack is not shown) may be deposited sequentially on the structure shown in fig. 4, so that the memory gate dielectric stack may be formed on each exposed surface in fig. 4. For example, the memory gate dielectric stack 1019 may include a first gate dielectric layer (e.g., an oxide or a high-K dielectric such as HfO) stacked in sequence₂About 1-10nm thick), a charge trapping layer (e.g., nitride, about 1-20nm thick), and a second gate dielectric layer (e.g., oxide or high K dielectric, about 1-10nm thick).

Alternatively, the storage gate dielectric stack 1019 may include a first gate dielectric layer (e.g., an oxide or a high-K dielectric such as HfO) stacked in sequence₂About 1-10nm thick), a floating gate layer (e.g., metal, about 1-20nm thick), and a second gate dielectric layer (e.g., oxide or high K dielectric, about 1-10nm thick).

Alternatively, the memory gate dielectric stack 1019 may comprise a ferroelectric material. For example, the memory gate dielectric stack 1019 may include a first metal layer, a ferroelectric material layer, a second metal layer, and a gate dielectric layer (e.g., an oxide or a high-K dielectric such as HfO) stacked in this order₂And a thickness of about 1-10 nm). For example, the ferroelectric material may include hafnium oxide such as HfO₂Zirconium oxides such as ZrO₂Tantalum oxide such as TaO₂Hafnium zirconium hafnium oxide_xZr_1-xO₂(wherein x is in the range of (0, 1)) such as Hf_0.5Zr_0.5O₂Hafnium tantalum hafnium oxide_xTa_1-xO₂(wherein x is in the range of (0, 1)) such as Hf_0.5Ta_0.5O₂HfO containing Si₂HfO containing Al₂、BaTiO₃、KH₂PO₄Or SBTi, the first metal layer and the second metal layer may each comprise TiN. In this case, the gate dielectric layer side in the memory gate dielectric stack 1019 faces the gate electrode layer.

The recess may then be filled with semiconductor material 1021, such as polysilicon, for the channel region. Here, the semiconductor material 1021 may be lightly doped to reduce channel resistance. For a junction device, semiconductor material 1021 may be n-type doped for a p-type device and p-type doped for an n-type device; while for a junction-less device, semiconductor material 1021 may be p-type doped for a p-type device and n-type doped for an n-type device.

For example, as shown in fig. 5, the holes and recesses may be filled with a semiconductor material 1021 by deposition, while in-situ doping may be performed. The filled semiconductor material 1021 should completely fill the holes and recesses with excess. The semiconductor material 1021 may be subjected to a planarization process such as Chemical Mechanical Polishing (CMP) to remove portions thereof outside the holes and recesses. For example, the planarization process may stop at the hard mask layer 1015 (so that the storage gate dielectric stack on its top surface may also be removed, see fig. 6).

The semiconductor material 1021 may then be etched back, leaving it in the recess, as shown in fig. 6. For example, the RIE may be performed in a direction substantially perpendicular to the substrate surface to etch back the semiconductor material 1021. Due to the presence of the layers above the recess, the semiconductor material 1021 in the recess may be masked and may thus be left behind. The portion of the (lightly doped) semiconductor material 1021 remaining in the recess (which may be referred to as "first doped region") may then be used for the channel region. The remaining semiconductor material 1021 is self-aligned to the gate electrode layer due to the formation in the recess in the gate electrode layer.

In conjunction with this, as shown in fig. 7, the memory gate dielectric stack 1019 may be selectively etched to be confined to the channel region, particularly if the memory gate dielectric stack 1019 includes a conductive layer therein. In this example, the storage gate dielectric stack 1019 also remains in the recess due to the shadowing of the semiconductor material 1021.

Of course, the present disclosure is not limited thereto. For example, the storage gate dielectric stack 1019 may also be left on the inner wall, particularly the sidewalls, of the hole (the portion on the bottom wall may be removed, for example, by vertical RIE), which may not affect the operation of the device, particularly in the case where the storage gate dielectric stack 1019 does not include a conductive layer therein.

Subsequently, as shown in fig. 8, the holes may be filled with semiconductor material 1023 for other parts of the active region. Here, the semiconductor material 1023 and the semiconductor material 1021 may be the same material, such as polysilicon. Here, semiconductor material 1023 may be moderately doped to adjust the device threshold voltage. For junction devices, semiconductor material 1023 may be n-doped for p-type devices and p-doped for n-type devices; and for a junction-less device semiconductor material 1023 may be p-doped for a p-type device and n-doped for an n-type device.

For example, the holes may be filled with semiconductor material 1023 by deposition, possibly with in-situ doping. The filled semiconductor material 1023 should completely fill the hole with excess. The semiconductor material 1023 may be subjected to a planarization process such as CMP to remove portions thereof outside the holes. For example, the planarization process may stop on the hard mask layer 1015.

Together,

semiconductor materials

1021 and 1023 form a (pillar-shaped) active region. The active region is filled in the hole so as to have substantially the same shape as the hole and vertically extend on the substrate like the hole.

As shown in fig. 9, a heat treatment, such as an anneal at a temperature of about 700 c to 1100 c, may be performed to drive dopants from the dopant source layers 1003, 1007, 1011 into the

active regions

1021, 1023. The dopant from the dopant source layer forms a certain distribution in the active region resulting in a heavily doped second doped region that can serve as a source/drain region S/D (in the case of a junction device, the dopant from the dopant source layer can reverse the doping type in the portion of the active region into which it diffuses), as shown by the dashed box in fig. 9. Since the dopant source layer as diffusion source is located on both upper and lower sides of the gate electrode layer, the resulting second doped region or source/drain region S/D may be aligned to the dopant source layer and correspondingly located on both upper and lower sides of the channel region (including the first doped region and possibly also including a portion of the semiconductor material 1023, e.g. the portion located between the source/drain regions S/D). Since the first doped region and the second doped region may each be self-aligned to the gate electrode layer and the dopant source layer, respectively, the doping profile in the first doped region may be substantially aligned to the doping profile in the second doped region (specifically, the upper end of the doping profile of the first doped region may be substantially aligned to the lower end of the doping profile of the second doped region above, and the lower end of the doping profile of the first doped region may be substantially aligned to the upper end of the doping profile of the second doped region below).

Since the dopant source layer surrounds the periphery of each active region, diffusion can proceed inward from the outer walls of the active regions. The diffusion may be open in the radial direction, so that the source/drain regions S/D may have a ring shape. Additionally, the source and drain regions S/D may have some overlap with the semiconductor material 1021, and the lowermost source and drain regions S/D may have some overlap with the common ground plane 1001 w.

Thus, in the memory cell region, vertical strings of memory cells are formed, each memory cell including a corresponding channel region and source/drain regions located on both upper and lower sides of the channel region. Since the source/drain regions are shared between adjacent memory cells, each string of memory cells is connected to each other in series.

In this example, the dopant source layer is left behind. However, the present disclosure is not limited thereto. For example, the dopant source layer may be removed by, for example, forming a tooling hole in the contact region and selectively etching through the tooling hole. The space left by the removal of the dopant source layer may be filled with a dielectric material, for example, by deposition through a process hole.

Also, in this example, polysilicon is left as the gate. However, the present disclosure is not limited thereto, and an alternative gate structure may be further formed. For example, the polysilicon layer may be removed by, for example, forming a machining hole in the contact region and selectively etching through the machining hole. The space left by the removal of the polysilicon layer may be filled with the gate electrode and/or the storage gate dielectric stack, for example, by deposition through a tooling hole (in which case the storage gate dielectric stack may not need to be preformed on the interior of the hole as described above in connection with fig. 5 and 6).

In addition, in this example, the doping profile is adjusted separately for the channel region. However, the present disclosure is not limited thereto. For example, after opening the hole as described above in connection with fig. 3, a storage gate dielectric stack may be formed on the sidewalls of the hole and filled (lightly or moderately doped) with a semiconductor material on the inside thereof to serve as an active region. Dopants may then be driven into the active region by thermal treatment to form heavily doped source/drain regions.

Subsequently, various electrical contacts may be fabricated to achieve the desired electrical connection. For three-dimensional arrays, there are a number of ways in the art to make interconnects. For example, the gate electrode layer in the contact region may be patterned in a step shape to form an electrical contact to each gate electrode layer.

The memory device after the electrical contacts are formed is shown in fig. 10. As shown in fig. 10, a dielectric layer 1025 (e.g., oxide) may be formed over the device. In the dielectric layer 1025, electrical contacts 1027-1 to the common ground plane 1001w (and thus to the source/drain regions of all the lowermost memory cells), electrical contacts 1027-2, 1027-3 to the respective

gate electrode layers

1005, 1009, and electrical contacts 1027-4, 1027-5, 1027-6 to the source/drain regions of the respective uppermost memory cells may be formed. Such electrical contacts may be made by forming contact holes in a dielectric layer and filling it with a conductive material, such as tungsten (W).

Thus, a memory device according to this embodiment is obtained. As shown in fig. 10, the memory device may include a plurality of memory cell layers (in this example, only two layers are shown), each including an array of memory cells. Each memory cell includes a channel region opposite a corresponding gate electrode layer and source/drain regions on opposite sides of the channel region. The memory cells in the same columnar active region extending in the vertical direction are connected in a string in the vertical direction, at the upper end to the corresponding electrical contact, and at the lower end to a common ground potential plane. The memory cells in each layer share the same gate electrode layer.

A certain memory cell layer can be selected by electrical contacts to the gate electrode layer. In addition, a certain memory cell string can be selected by the source/drain contact portion.

In this example, electrical contacts are formed for the source/drain regions of each memory cell of the uppermost layer. The density of such source/drain contacts is greater due to the greater density of memory cells. According to another embodiment, electrodes arranged in rows (or columns) electrically connected to the source/drain regions of the memory cells of the lowermost layer may be formed, and electrodes arranged in columns (or rows) electrically connected to the source/drain regions of the memory cells of the uppermost layer may be formed. Thus, by the electrodes on the upper side and the electrodes on the lower side (intersecting with each other to form an array corresponding to the memory cell array), the corresponding memory cell string can be selected.

According to the embodiments of the present disclosure, since the doping concentration at different regions can be individually adjusted, different doping profiles can be achieved. For example, the doping concentration of the first doping region may be about 1E16-1E18cm^-3The doping concentration of the second doping region may be about 1E18-5E21cm^-3The doping concentration of the portion of the active region outside the first and second doped regions may be about 1E17-5E19cm^-3。

According to the embodiment of the disclosure, the doping concentration of the active region can exist in the normal direction of the storage gate dielectric stackAnd (4) distribution. For example, the active region may include a region located inside the first doped region and having a higher doping concentration than that in the first doped region. This distribution is advantageous for controlling short channel effects. For example, the doping concentration in the first doped region may be about 1E16-3E18cm^-3And the doping concentration in the region is about 1E17-2E19cm^-3。

Fig. 11 and 12 show a flow diagram of a middle staging of a flow of fabricating a memory device according to another embodiment of the present disclosure. Hereinafter, differences of this embodiment from the above-described embodiment will be mainly described.

After forming the storage gate dielectric stack 1019 and semiconductor material 1021 in the recess as described above in connection with fig. 9, instead of filling the hole with semiconductor material 1023, as shown in fig. 11, semiconductor material 1023' (with respect to its material and doping, see the description above for semiconductor material 1023) may be formed along the inner walls of the hole. Thus, a hollow active region may be formed, which may be filled with a dielectric layer 1029 (e.g., oxide) on the inside. Such a structure can be formed, for example, as follows. Specifically, on the structure shown in fig. 9, semiconductor material 1023' (having a thickness of, for example, about 5-20nm) may be formed in a substantially conformal manner by, for example, deposition, and then an oxide may be deposited. Subsequently, the deposited semiconductor material 1023' and oxide may be subjected to a planarization process such as CMP. The planarization process may stop on the hard mask layer 1015.

The subsequent processing may be performed as described above, and will not be described herein. Thus, a structure as shown in fig. 12 can be obtained. In this example, since the thickness (dimension in the horizontal direction in the figure) of the active region on the inner wall of the hole is small, the source/drain regions S/D can be extended over the entire thickness, effectively reducing the resistance.

Fig. 13 and 14 show a flow chart of a middle staging of a flow of fabricating a memory device according to yet another embodiment of the present disclosure. Hereinafter, differences of this embodiment from the above-described embodiment will be mainly described.

In this embodiment, as shown in fig. 13, a diffusion barrier layer 1013 may be provided between each

dopant source layer

1003, 1007, 1011 and each

gate electrode layer

1005, 1009. For example, the diffusion barrier 1013 may comprise a nitride having a thickness of about 1-3 nm. On one hand, the diffusion barrier layer 1013 may inhibit undesired diffusion of dopants in the dopant source layer; on the other hand, the thickness of the diffusion barrier 1013 may also be used to control the diffusion of dopants into the channel region (the thicker the diffusion barrier 1013, the less impurities or dopants diffuse into the channel region). The subsequent processing may be performed as described above, and will not be described herein. Thus, a structure as shown in fig. 14 can be obtained.

In addition, according to the embodiments of the present disclosure, a selection transistor may be further added at the uppermost end and/or the lowermost end of the pillar-shaped active region, which is not described herein again. Such a selection transistor may also be a vertical device.

The memory device according to the embodiments of the present disclosure may be applied to various electronic devices. For example, the memory device may store various programs, applications, and data required for the operation of the electronic device. The electronic device may further include a processor cooperating with the memory device. For example, the processor may operate the electronic device by allowing a program stored in the storage device. Such electronic devices are for example smart phones, computers, tablets (PCs), wearable smart devices, mobile power supplies, robots, smart chips, etc.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A memory device, comprising:

a plurality of pillar-shaped active regions formed on the substrate and extending upward from the substrate; and

a plurality of gate electrode layers arranged on the substrate in sequence from bottom to top, spaced apart from each other and surrounding the respective columnar active regions, wherein each gate electrode layer faces each columnar active region via the memory gate dielectric stack,

the columnar active region comprises first doping regions opposite to the gate electrode layers and second doping regions located on two opposite sides of the first doping regions, and the doping characteristics in the first doping regions are different from the doping characteristics in the second doping regions.

2. The memory device of claim 1, wherein a doping concentration in the second doped region is higher than a doping concentration in the first doped region.

3. The memory device of claim 1, wherein a doping type in the first doped region is the same as or different from a doping type in the second doped region.

4. The storage device of any of claims 1-3, further comprising:

a dopant source layer between the gate electrode layers, wherein the dopant source layer comprises a dopant of the same type as the second doped region.

5. The memory device of claim 4, wherein the second doped region has a ring shape and an outer wall of the second doped region is an outer wall of the pillar-shaped active region.

6. The memory device of claim 4, further comprising: a diffusion barrier layer between each gate electrode layer and each dopant source layer.

7. The memory device of claim 4, wherein the dopant source layer comprises n-type doped phospho-or arseno-silicate glass, or p-type doped borosilicate glass, wherein the dopant is included at a concentration of 0.01% -10%.

8. The memory device of claim 1, wherein the gate electrode layer comprises doped polysilicon or metal.

9. The memory device of claim 1, wherein the semiconductor material in the pillar active regions is homogenous.

10. The memory device of claim 1, wherein a portion of the columnar active region where the first doped region is located protrudes outward relative to a remaining portion of the columnar active region, and a portion of the columnar active region outside the first doped region and the second doped region has a concentration higher than the first doped region and lower than the second doped region.

11. The memory device of claim 10, wherein the first doped region has a doping concentration of 1E16cm^-3-1E18cm^-3The doping concentration of the second doping region is 1E18cm^-3-5E21cm^-3The doping concentration of the part of the columnar active region outside the first doping region and the second doping region is 1E17cm^-3-5E19cm^-3。

12. The memory device of claim 1, wherein the pillar active region is hollow and filled with a dielectric.

13. The memory device of claim 1, wherein the storage gate dielectric stack comprises a first gate dielectric layer, a charge trapping layer, and a second gate dielectric layer stacked in sequence.

14. The memory device of claim 1, wherein a doping profile in the first doped region is substantially aligned with a doping profile in the second doped region.

15. The memory device of claim 1, wherein the columnar active region comprises a region inside the first doped region and having a higher doping concentration than in the first doped region in a normal direction of the memory gate dielectric stack.

16. The memory device of claim 15, wherein a doping concentration in the first doped region is 1E16cm^-3-3E18cm^-3。

17. The memory device of claim 15, wherein the doping concentration in the region is 1E17cm-³-2E19cm^-3。

18. A method of manufacturing a memory device, comprising:

providing an alternating stack of dopant source layers and gate electrode layers on a substrate, wherein the dopant source layers comprise a type of dopant;

forming a plurality of holes in the stack;

filling semiconductor material into the holes to form a columnar active region, and performing heat treatment to drive dopants into the semiconductor material from the dopant source layer, and forming a first doping region opposite to each gate electrode layer and second doping regions on two opposite sides of each first doping region in the columnar active region, wherein the doping characteristics in the first doping regions are different from the doping characteristics in the second doping regions; and

a storage gate dielectric stack is formed between the gate electrode layer and the semiconductor material.

19. The method of claim 18, further comprising: the gate electrode layer is selectively etched through the hole to be recessed,

wherein filling the hole with the semiconductor layer includes: filling the recess with a lightly doped semiconductor material through a hole; the hole is filled with a moderately doped semiconductor material.

20. The method of claim 19, wherein forming a storage gate dielectric stack comprises:

forming a storage gate dielectric stack on the inner wall of the hole before filling the lightly doped semiconductor material; and

after filling the lightly doped semiconductor material, the storage gate dielectric stack is selectively etched.

21. The method of claim 19, wherein a hollow, medium doped semiconductor material is formed along an inner wall of the hole, the method further comprising: the medium-doped semiconductor material is filled with a dielectric layer on the inside.

22. The method of claim 18, wherein providing alternating tiers further comprises:

a diffusion barrier layer is disposed between the gate electrode layer and the dopant source layer.

23. An electronic device comprising a memory device as claimed in any one of claims 1-17.

24. The electronic device of claim 23, comprising a smartphone, a computer, a wearable smart device, a mobile power source, a robot, a smart chip.