CN107068686B

CN107068686B - Memory device, method of manufacturing the same, and electronic apparatus including the same

Info

Publication number: CN107068686B
Application number: CN201710273430.4A
Authority: CN
Inventors: 朱慧珑
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2017-04-24
Filing date: 2017-04-24
Publication date: 2020-06-09
Anticipated expiration: 2037-04-24
Also published as: CN107068686A

Abstract

A memory device, a method of manufacturing the same, and an electronic apparatus including the memory device are disclosed. According to an embodiment, a memory device may include a plurality of pillar-shaped active regions formed on a substrate and extending upward from the substrate; and multiple gate electrode layers sequentially arranged on the substrate from bottom to top, spaced from each other and respectively surrounding the columnar active regions, wherein each gate electrode layer faces each columnar active region through the storage gate dielectric stack, the columnar active regions comprise source/drain regions, and the doping concentration of the source/drain regions is higher than that of the rest parts in the active regions.

Description

Memory device, method of manufacturing the same, and electronic apparatus including the same

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to a vertical device-based memory device, a method of manufacturing the same, and an electronic device including such a memory device.

Background

In a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a source, a gate, and a drain are arranged in a direction substantially parallel to a surface of a substrate. Due to this arrangement, the horizontal type device is not easily further downsized. Unlike this, in the vertical type device, the source, the gate, and the drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, vertical devices are more easily scaled down relative to horizontal devices.

In a memory device based on a vertical type device, there are memory cells stacked so that their respective resistances are connected in series. Thus, the total resistance increases, and the memory device performance deteriorates. Since the active regions (including the channel region and the source/drain regions) are generally integrally formed in the conventional vertical type memory device, the dopant type and concentration in the channel region and the source/drain regions are substantially the same. Therefore, it is difficult to reduce the total resistance by increasing the doping concentration of the source/drain regions, since this also increases the doping concentration in the channel region, resulting in an increase in leakage current between the source and drain regions.

Disclosure of Invention

In view of the above, it is an object of the present disclosure, at least in part, to provide a vertical device-based memory device, a method of manufacturing the same, and an electronic device including the same, in which a doping type/concentration can be adjusted for a channel region and a source/drain region, respectively.

According to an aspect of the present disclosure, there is provided a memory device including: a plurality of pillar-shaped active regions formed on the substrate and extending upward from the substrate; and multiple gate electrode layers sequentially arranged on the substrate from bottom to top, spaced from each other and respectively surrounding the columnar active regions, wherein each gate electrode layer faces each columnar active region through the storage gate dielectric stack, the columnar active regions comprise source/drain regions, and the doping concentration of the source/drain regions is higher than that of the rest parts in the active regions.

According to another aspect of the present disclosure, there is provided a method of manufacturing a memory device, including: providing an alternating stack of first material layers and gate electrode layers on a substrate; forming a plurality of holes in the stack; forming a mask layer on the exposed side wall of the first material layer in the hole; forming a storage gate dielectric stack on the inner wall of the hole; filling semiconductor material into the hole, and etching back to make the semiconductor material remain between the mask layers; selectively etching the storage gate dielectric stack by using the remaining semiconductor material as a mask; removing the mask layer to expose the side wall of the first material layer, and selectively etching the first material layer through the hole to retract the side wall of the first material layer; forming a dopant source layer in a space resulting from sidewall retraction of the first material layer; the holes are filled with a semiconductor material and a thermal process is performed to drive dopants from the dopant source layer into the semiconductor material.

According to another aspect of the present disclosure, there is provided an electronic device including the above memory device.

According to the embodiments of the present disclosure, a portion of the active region, such as the source/drain region, may be separately doped, and thus the source/drain region resistance may be reduced. For example, the source/drain regions may be further doped using a solid phase dopant source of dielectric as a diffusion source to increase the doping concentration therein, thereby reducing the resistance of the source/drain regions and, thus, the overall series resistance of the stacked memory cells. Thus, the number of memory cells stacked can be increased, and thus the integration density can be increased.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

fig. 1-15 show schematic diagrams of a process flow for fabricating a memory device according to an embodiment of the present disclosure.

Throughout the drawings, the same or similar reference numerals denote the same or similar components.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

The memory device according to the embodiments of the present disclosure is based on a vertical type device, and thus may include a plurality of pillar-shaped active regions formed on a substrate to extend upward (e.g., substantially perpendicular to a surface of the substrate) from the substrate. The columnar active region may be solid or hollow (in which a dielectric may be filled). Vertical devices may be formed based on these vertically extending columnar active regions by forming gate stacks around their peripheries. The gate stack may be a memory gate stack in order to implement a memory function. For example, the gate stack may include a storage gate dielectric stack formed on at least a portion of an outer wall of the columnar active region and a gate electrode layer facing the columnar active region via the storage gate dielectric stack. The gate electrode layer extends in a direction intersecting with the extending direction of the columnar active region (e.g., substantially parallel to the substrate surface) so as to intersect with the columnar active region, and thus can define a channel region in the columnar active region (and accordingly define a source/drain region, i.e., a portion of the active region on opposite sides of the channel region). A conductive path may be formed between the source/drain regions through the channel region.

A plurality of gate electrode layers may be provided, arranged in sequence from bottom to top, spaced apart from each other and surrounding each respective columnar active region, so as to define a plurality of channel regions in each respective columnar active region (and thus a plurality of memory cells, each memory cell including a respective channel region and source/drain regions on opposite sides of the channel region). Respective source/drain regions of upper and lower adjacent memory cells may be connected together (e.g., physically integrated). Here, the memory unit may be a flash memory (flash) unit.

The columnar active regions may be arranged in an array (e.g., a two-dimensional array that is typically arranged in rows and columns). In addition, the memory devices may be three-dimensional (3D) arrays because they vertically extend over the substrate and define multiple layers of memory cells through multiple layers of gate electrode layers, respectively, as described above. In the 3D array, each columnar active region defines a string of memory cells.

In this context, the term "memory gate dielectric stack" refers to the portion of the memory gate stack between the gate electrode layer and the active region (or channel region). The stack as a whole exhibits dielectric properties, i.e. such that the gate electrode layer is not in direct electrical connection with the channel region, and is thus referred to as a "dielectric" stack, but this does not exclude the possibility of one or more conductive layers being comprised in the stack. The storage gate dielectric stack may include a charge trapping layer, a floating gate layer, or a ferroelectric material, etc. to perform a storage function. For example, the storage gate dielectric stack may include a first gate dielectric layer, a floating gate layer or charge trapping layer, and a second gate dielectric layer, which are sequentially stacked, or may include a first metal layer, a ferroelectric material layer, a second metal layer, and a gate dielectric layer. There are various memory gate stack configurations in the art that can implement the memory function and are not described in detail herein.

According to an embodiment of the present disclosure, the doping concentration of the source/drain region may be higher than that of the remaining portion of the pillar-shaped active region. Accordingly, the resistance of the source/drain regions can be reduced, and thus the total series resistance of the memory cells stacked on each other can be reduced. The remaining portion of the columnar active region may be unintentionally doped or may be relatively lightly doped to avoid increased leakage current.

According to embodiments of the present disclosure, the semiconductor material in the columnar active region may be homogenous (e.g., a common silicon material), and a desired doping profile may be achieved in the columnar active region by doping differently. For example, a relatively high doping concentration in the source/drain regions may be achieved by driving dopants into the columnar active region from a dopant source layer disposed between the gate electrode layers (and thus aligned with the location of the source/drain regions).

Such a memory device can be manufactured, for example, as follows. In particular, an alternating stack of first material layers and gate electrode layers may be provided on the substrate. The first material layer may be the lowermost layer of the stack, or the first material layer may be the uppermost layer. Here, the first material layer may serve to define the location of the source/drain region.

Then, several holes may be formed in the stack. Active regions (corresponding to the shape of the holes and thus may be "columnar," including but not limited to columnar) will then be formed in these holes. These holes may extend in the stacking direction (vertical direction) of the stack and may extend through the stack. In the following process, these holes are machining passages.

A memory gate dielectric stack may be formed on the sidewalls of the hole at least where it corresponds to the gate electrode layer. The memory gate dielectric stack thus formed, together with the gate electrode layer, forms a memory gate stack. The holes may then be filled (doped) with a semiconductor material to form (pillar) active regions. The semiconductor material may completely fill the hole to form a solid pillar-shaped active region, or may be formed only along the inner wall of the hole to form a hollow pillar-shaped active region (the inner side may be further filled with a dielectric layer). The active region cooperates with each memory gate stack to form a memory cell.

Here, the storage gate dielectric stack may be formed in a self-aligned manner. For example, a mask layer may be formed on the sidewalls of the first material layer exposed in the hole, and a storage gate dielectric stack may be formed on the sidewalls of the hole. Then, the holes are filled with a semiconductor material and etched back to leave the semiconductor material between the mask layers. The remaining semiconductor material is aligned with the gate electrode layer. The memory gate dielectric stack may be selectively etched using the remaining semiconductor material as a mask. Thus, the remaining memory gate dielectric stack can be aligned to the gate electrode layer by selective etching.

Such a mask layer may also be formed in a self-aligned manner. For example, a polysilicon layer may be formed on the inner wall of the hole. Impurities may be driven from the first material layer into the polysilicon layer by a thermal process. For this purpose, an impurity capable of changing the etchability of polysilicon, such as boron (B), may be included in the first material layer (in this case, a diffusion barrier layer may also be formed between the first material layer and the gate electrode layer). Then, portions of the polycrystalline silicon layer, into which the impurities are not driven, may be selectively etched with respect to portions of the polycrystalline silicon layer, into which the impurities are driven. Since the portion of the polysilicon layer driven with the impurity is aligned with the first material layer as the impurity source, it remains as a mask layer aligned with the first material layer.

To separately dope the source/drain regions, a dopant source layer may be formed at the location of the first material layer. Subsequently, a thermal treatment may be performed to drive dopants from the dopant source layer into the semiconductor material. Due to the dopants from the dopant source layer, the doping concentration in the portion (source/drain region) of the columnar active region corresponding to the dopant source layer will increase, and thus the resistance of the source/drain region can be reduced.

The dopant source layer may be a dielectric layer containing a type and concentration of dopant therein. For example, the dopant may be introduced into the dopant source layer by in-situ doping thereof when forming it, for example, upon deposition.

The present disclosure may be presented in various forms, some examples of which are described below.

As shown in fig. 1, a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, a bulk Si substrate is described as an example for convenience of explanation.

In the substrate 1001, a well region 1001w is formed, for example, by ion implantation. This well region 1001w may then serve as a common ground potential plane for the memory device to which the source/drain regions underlying respective ones of the lowermost memory cells in the memory device may be connected. If the memory cell is an n-type device, well region 1001w may be doped n-type; well region 1001w may be doped p-type if the memory cell is a p-type device.

On the substrate 1001, alternating stacks of

first material layers

1003, 1007, 1011 and

gate electrode layers

1005, 1009 may be formed in sequence by, for example, deposition. Each of the

first material layers

1003, 1007, 1011 may comprise a suitable dielectric material such as an oxide and contain impurities such as boron (B) to a thickness of about 20-50 nm. The impurities may be introduced into the first material layer at the same time as the first material layer is formed, for example, by in-situ doping. In one example, the first material layer may include borosilicate glass (BSG), and the impurity may be included at a concentration of about 1-10%. The

gate electrode layers

1005, 1009 may comprise a suitable gate electrode material such as polysilicon or metal and may be about 10-100nm thick. Here, a replacement gate process is described as an example. In the replacement gate process, the

gate electrode layers

1005, 1009 at this time are sacrificial gate electrodes and may comprise (undoped) polysilicon. The steps of forming the gate electrode layer and the dopant source layer may be repeated until a desired number of layers are formed.

A diffusion barrier layer 1013 may be provided between the

first material layers

1003, 1007, 1011 and the

gate electrode layers

1005, 1009. For example, the diffusion barrier 1013 may comprise a nitride having a thickness of about 1-3 nm. On the one hand, the diffusion barrier layer 1013 may suppress undesired diffusion of impurities or dopants; on the other hand, the thickness of the diffusion barrier 1013 may also be used to control diffusion of impurities or dopants into the channel region (the thicker the diffusion barrier 1013, the less impurities or dopants diffuse into the channel region).

In addition, a hard mask may also be formed over the grown layers for the purpose of convenience of patterning in subsequent processing, providing an appropriate stop layer, and the like. For example, a nitride (e.g., silicon nitride) layer 1015 may be formed, for example, to a thickness of about 10-100 nm.

Subsequently, the location of the active region can be defined. As shown in the top view of fig. 2, the substrate may include a memory cell region in which memory cells may be formed and a contact region in which various electrical contacts may be formed. Of course, the substrate may also include other areas, such as circuit areas for forming associated circuitry, etc. In the memory cell region, a photoresist 1017 may be formed on the structure shown in fig. 1. By photolithography (exposure and development), the photoresist 1017 is patterned into the nitride layer 1015 exposed at the position of the active region. The layout of the holes depends on the layout of the memory cells, for example, the holes may be arranged in rows and columns in a two-dimensional array.

Next, as shown in FIG. 3 (cross-sectional view along line AA' in FIG. 2), a hole may be opened downward through the photoresist. Specifically, the nitride layer 1015 and the first material layer, the diffusion barrier layer 1013, and the gate electrode layer 1009 in the above-described alternating stack may be selectively etched in this order, for example, to form the hole. For example, the RIE may be performed in a direction substantially perpendicular to the substrate surface, resulting in holes extending in a direction substantially perpendicular to the substrate surface. After that, the photoresist 1017 may be removed. In this example, the hole may penetrate through the stack of the gate electrode layer and the first material layer.

Here, the hole is illustrated as a circle, but the present disclosure is not limited thereto. The holes may be of any shape suitable for machining.

Then, a self-aligned mask layer may be formed on the sidewalls of the

first material layers

1003, 1007, 1011 exposed in the holes. To this end, as shown in fig. 4, a mask material layer 1021 may be formed, for example, by deposition, on the structure shown in fig. 3. The mask material layer 1021 may include a material capable of changing etchability by impurities in the first material layer, such as silicon (amorphous silicon formed by deposition), and may have a thickness of about 5-10 nm. In this case, in order to avoid an influence on the sacrificial

gate electrode layers

1005, 1009 of polysilicon when patterning the mask material layer 1021 of amorphous silicon, the protective layer 1015 may be formed by deposition, for example, before forming the mask material layer 1021. For example, the protective layer 1015 may comprise an oxide having a thickness of about 0.5-1 nm. Of course, in the case where the mask material layer 1021 has etching selectivity with respect to the sacrificial

gate electrode layers

1005 and 1009, such a protective layer 1015 may be omitted.

As shown in fig. 5, a heat treatment, such as an anneal at a temperature of about 700 c to 1050 c, may be performed to drive impurities from

first material layers

1003, 1007, 1011 into mask material layer 1021. In this sense, the first material layer is also a "dopant source layer," and is referred to herein as the first material layer merely for purposes of distinguishing it from the dopant source layer described below. Thus, a portion 1021' into which impurities (such as B) are driven and thus modified is formed at a portion of the mask material layer 1021 opposite to the

first material layers

1003, 1007, 1011. The modified portion 1021' has an etch selectivity relative to the remainder of the mask material layer 1021. In addition, due to the annealing, amorphous silicon may be at least partially converted to polysilicon.

Then, as shown in fig. 6, the remaining portion of the mask material layer 1021 may be selectively etched with respect to the modified portion 1021'. For example, in the case of amorphous silicon/polysilicon, TMAH solution may be used. Thus, a mask layer 1021' is left on the inner walls of the holes, self-aligned to the

first material layers

1003, 1007, 1011. Due to the presence of the protective layer 1019, the sacrificial

gate electrode layers

1005, 1009 may not be etched during the etching. Thereafter, the protective layer 1019 may be selectively etched using the mask layer 1021' as a mask to expose sidewalls of the sacrificial

gate electrode layers

1005, 1009 for subsequent processing (see fig. 7).

Referring to fig. 7, due to the presence of the mask layer 1021' (and the protection layer 1019) at the sidewalls of the

first material layers

1003, 1007, 1011, recesses are formed that are self-aligned to the respective sacrificial

gate electrode layers

1005, 1009. Due to the presence of such a recess, material layers, such as a memory gate dielectric stack, can be formed that are self-aligned to the respective sacrificial

gate electrode layers

1005, 1009.

Specifically, as shown in fig. 7, a storage gate dielectric stack 1023 may be formed on the resulting structure, such as by deposition. For example, layers in a memory gate dielectric stack (layer configuration in the stack is not shown in the figure) may be deposited sequentially. For example, the memory gate dielectric stack 1023 can include a first gate dielectric layer (e.g., an oxide or high-K dielectric such as HfO) stacked in sequence₂About 1-10nm thick), a charge trapping layer (e.g., nitride, about 1-20nm thick), and a second gate dielectric layer (e.g., oxide or high K dielectric, about 1-10nm thick).

Alternatively, the memory gate dielectric stack 1023 may include a first gate dielectric layer (e.g., an oxide or high-K dielectric such as HfO) stacked in sequence₂About 1-10nm thick), a floating gate layer (e.g., metal, about 1-20nm thick), and a second gate dielectric layer (e.g., oxide or high K dielectric, about 1-10nm thick).

Alternatively, the memory gate dielectric stack 1023 may comprise a ferroelectric material. For example, the memory gate dielectric stack 1023 may include a first metal layer, a ferroelectric material layer, a second metal layer, and a gate dielectric layer (e.g., an oxide or high-K dielectric such as HfO) stacked in that order₂And a thickness of about 1-10 nm). For example, the ferroelectric material may include hafnium oxide such as HfO₂Zirconium oxides such as ZrO₂Tantalum oxide such as TaO₂Hafnium zirconium hafnium oxide_xZr_1-xO₂(wherein x is in the range of (0, 1)) such as Hf_0.5Zr_0.5O₂Hafnium tantalum hafnium oxide_xTa_1-xO₂(wherein x is in the range of (0, 1)) such as Hf_0.5Ta_0.5O₂HfO containing Si₂HfO containing A1₂、BaTiO₃、KH₂PO₄Or SBTi, the first metal layer and the second metal layer may each comprise TiN. In this case, the side of the gate dielectric layer in the memory gate dielectric stack 1023 faces the gate electrode layer.

Then, as shown in fig. 8, the recess may be filled with a semiconductor material 1025 for the channel region, such as polysilicon. Here, the semiconductorMaterial 1025 may be undoped or intentionally undoped. Alternatively, semiconductor material 1025 may be lightly doped (e.g., with a doping concentration of about 1E16-3E18cm^-3) To reduce channel resistance. For a junction device, semiconductor material 1025 may be n-doped for a p-type device and p-doped for an n-type device; while for a junction-less device, semiconductor material 1021 may be p-type doped for a p-type device and n-type doped for an n-type device.

For example, the holes and recesses may be filled with semiconductor material 1025 by deposition (in situ doping may be performed at the same time as deposition, if doping is desired). The filled semiconductor material 1025 should completely fill the holes and recesses with excess. The semiconductor material 1025 may be subjected to a planarization process, such as Chemical Mechanical Polishing (CMP), to remove portions thereof outside the holes and recesses. For example, the planarization process may stop at the hard mask layer 1015 (so that the storage gate dielectric stack on its top surface may also be removed). Semiconductor material 1025 may then be etched back, leaving it in the recess. For example, the RIE may be performed in a direction substantially perpendicular to the substrate surface to etch back the semiconductor material 1025. Due to the presence of the layers above the recess, the semiconductor material 1025 in the recess may be masked and, thus, may remain. The portion of (lightly doped) semiconductor material 1025 left in the recess may then be used for the channel region. Since the recess is self-aligned to the gate electrode layer as described above, the remaining semiconductor material 1025 is self-aligned to the gate electrode layer.

In conjunction with this, as shown in fig. 9, the memory gate dielectric stack 1023 may be selectively etched, using the remaining semiconductor material 1025 as a mask, to confine it to the channel region, especially if the memory gate dielectric stack 1023 includes a conductive layer.

In addition, as shown in fig. 9, the protective layer 1019 and the mask layer 1021' may be removed by selective etching. Thus, the sidewalls of the

first material layers

1003, 1007, 1011 are exposed. The

first material layer

1003, 1007, 1011 may be selectively etched to retract its sidewalls.

As shown in fig. 10, a dopant source layer 1027 may be formed in a space where sidewalls of the first material layer recede. Such dopant source layers 1027 may be formed by deposition and etch back. The dopant source layer 1027 may at least partially fill in the space due to the sidewall retraction of the first material layer, and thus the sidewalls of the dopant source layer 1027 may be recessed inward relative to or substantially aligned with the sidewalls of the gate electrode layer. The dopant source layer 1027 may include a type of dopant (e.g., p-type dopant for a p-type device and n-type dopant for an n-type device). The dopant source layer 1027 may comprise a semiconductor material such as polysilicon for the active region and may then serve as (part of) the source/drain regions. Dopants may be introduced into the dopant source layer at the same time as the formation of the dopant source layer, for example, by in situ doping. Alternatively, the dopant source layer 1027 may include other suitable solid phase diffusion sources. For example, the dopant source layer 1027 may comprise n-type doped phosphosilicate glass (PSG) or arsenic silicate glass (AsSG) for n-type devices, or p-type doped borosilicate glass (BSG) for p-type devices, which may contain dopants at a concentration of about 0.01-10%.

Then, as shown in fig. 11, the holes may be filled with semiconductor material 1029 for other portions of the active region. Here, the semiconductor material 1029 and the semiconductor material 1025 (and the dopant source layer 1027 in the case where it is a semiconductor material) may be the same material, such as polysilicon. Here, the semiconductor material 1029 may be undoped or not intentionally doped. Alternatively, semiconductor material 1029 can be medium doped (e.g., doping concentration of about 1E17-2E19 cm)^-3) To adjust the device threshold voltage. For a junction device, semiconductor material 1029 can be n-type doped for a p-type device and p-type doped for an n-type device; while for a junction-less device, semiconductor material 1029 may be p-type doped for a p-type device and n-type doped for an n-type device.

For example, the holes may be filled with semiconductor material 1029 by deposition, while in-situ doping may be performed. In this example, the filled semiconductor material 1029 may be relatively thin and, thus, not completely fill the hole. Of course, the filled semiconductor material 1023 may also completely fill the hole. In case the hole is not completely filled, the hole may be further filled with a dielectric material 1031 such as an oxide. The semiconductor material 1029 (and dielectric material 1031) may be subjected to a planarization process, such as CMP, to remove portions thereof outside the holes. For example, the planarization process may stop on the hard mask layer 1015.

In this way, semiconductor materials 1025 and 1029 (and optionally 1027) together form a (pillar-like) active region. The active region is filled in the hole, and extends vertically on the substrate like the hole. Since

semiconductor material

1025, 1029 is homogenous, they are collectively shown as 1029 in fig. 11 (and so on in subsequent figures), with the region of semiconductor material 1025 shown schematically in dashed lines.

As shown in fig. 12, a thermal treatment, such as an anneal at a temperature of about 700 c-1100 c, may be performed to drive dopants from the dopant source layer 1027 into the active region 1029. The dopants from the dopant source layer are distributed in the active region to result in a heavily doped region that can be used as a source/drain region S/D, as shown by the dashed box in fig. 12. Since the dopant source layers as diffusion sources are located at the upper and lower sides of the gate electrode layer, the resulting source and drain regions S/D may be aligned to the dopant source layers and correspondingly located at the upper and lower sides of the channel region.

Since the dopant source layer surrounds the periphery of each active region, diffusion can proceed inward from the outer walls of the active regions. The diffusion may be open in the radial direction, so that the source/drain regions S/D may have a ring shape.

Thus, in the memory cell region, vertical strings of memory cells are formed, each memory cell including a corresponding channel region and source/drain regions located on both upper and lower sides of the channel region. Since the source/drain regions are shared between adjacent memory cells, each string of memory cells is connected to each other in series.

In this example, the first material layer (and dopant source layer) is left. However, the present disclosure is not limited thereto. For example, the first material layer (and the dopant source layer) may be removed by, for example, forming a tooling hole in the contact region and selectively etching through the tooling hole. The space left by the removal of the first material layer (and dopant source layer) may be filled with a dielectric material, for example, by deposition through a process hole.

Next, a replacement gate process may be performed to replace the sacrificial

gate electrode layers

1005, 1009 with the final gate electrode layers.

For example, as shown in fig. 13, process channels for sacrificial

gate electrode layers

1005, 1009 may be formed in other regions on the substrate 1001, such as contact regions. For example, trenches (e.g., which may also be circular and may be substantially perpendicular to the substrate surface) may be formed by selective etching such as RIE to expose the respective sacrificial

gate electrode layers

1005, 1009. Sidewalls of the sacrificial

gate electrode layers

1005 and 1009 are exposed in the trench.

Next, as shown in fig. 14, the sacrificial

gate electrode layers

1005 and 1009 can be removed by selective etching through the trench. In the case where the sacrificial

gate electrode layers

1005 and 1009 include polysilicon as described above, the removal may be performed by, for example, a TMAH solution. Thus, a space is left at the position where each of the sacrificial

gate electrode layers

1005 and 1009 is located. After that, a final gate electrode layer 1005 ', 1009' may be formed in this space via a trench, e.g. by deposition. Here, the gate electrode layers 1005 'and 1009' may include a metal. Accordingly, a thin work function adjusting layer may be formed before the metal gate electrode layers 1005 'and 1009'. Excess gate electrode layer material (and work function adjusting layer material) may be removed, such as material in the trenches and material on the top surface of the nitride layer 1015.

Subsequently, various electrical contacts may be fabricated to achieve the desired electrical connection. For three-dimensional arrays, there are a number of ways in the art to make interconnects. For example, the gate electrode layer in the contact region may be patterned in a step shape to form an electrical contact to each gate electrode layer.

The memory device after the electrical contacts are formed is shown in fig. 15. As shown in fig. 15, a dielectric layer 1033 (e.g., oxide) may be formed over the device. In the dielectric layer 1033, electrical contacts 1035-1 to the common ground potential 1001w (and thus to the source/drain regions of all the lowermost memory cells), to electrical contacts 1035-2, 1035-3 to the respective gate electrode layers 1005 ', 1009', and to the source/drain regions of the respective uppermost memory cells can be formed. Such electrical contacts may be made by forming contact holes in a dielectric layer and filling it with a conductive material, such as tungsten (W).

Thus, a memory device according to this embodiment is obtained. As shown in fig. 15, the memory device may include a plurality of memory cell layers (in this example, only two layers are shown), each including an array of memory cells. Each memory cell includes a channel region opposite a corresponding gate electrode layer and source/drain regions on opposite sides of the channel region. The memory cells in the same columnar active region extending in the vertical direction are connected in a string in the vertical direction, at the upper end to the corresponding electrical contact, and at the lower end to a common ground potential plane. The memory cells in each layer share the same gate electrode layer.

A certain memory cell layer can be selected by electrical contacts to the gate electrode layer. In addition, a certain memory cell string can be selected by the source/drain contact portion.

In this example, electrical contacts are formed for the source/drain regions of each memory cell of the uppermost layer. The density of such source/drain contacts is greater due to the greater density of memory cells. According to another embodiment, electrodes arranged in rows (or columns) electrically connected to the source/drain regions of the memory cells of the lowermost layer may be formed, and electrodes arranged in columns (or rows) electrically connected to the source/drain regions of the memory cells of the uppermost layer may be formed. Thus, by the electrodes on the upper side and the electrodes on the lower side (intersecting with each other to form an array corresponding to the memory cell array), the corresponding memory cell string can be selected.

In addition, according to the embodiments of the present disclosure, a selection transistor may be further added at the uppermost end and/or the lowermost end of the pillar-shaped active region, which is not described herein again. Such a selection transistor may also be a vertical device.

The memory device according to the embodiments of the present disclosure may be applied to various electronic devices. For example, the memory device may store various programs, applications, and data required for the operation of the electronic device. The electronic device may further include a processor cooperating with the memory device. For example, the processor may operate the electronic device by allowing a program stored in the storage device. Such electronic devices are for example smart phones, computers, tablets (PCs), wearable smart devices, mobile power supplies, robots, smart chips, etc.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A memory device, comprising:

a plurality of pillar-shaped active regions formed on the substrate and extending upward from the substrate; and

a plurality of gate electrode layers arranged on the substrate in sequence from bottom to top, spaced apart from each other and surrounding the respective columnar active regions, wherein each gate electrode layer faces each columnar active region via the memory gate dielectric stack,

the columnar active region comprises a source/drain region, and the doping concentration of the source/drain region is higher than that of the rest part in the active region.

2. The memory device of claim 1, wherein the source/drain region is ring-shaped.

3. The memory device of claim 1, further comprising:

a dopant source layer between the gate electrode layers.

4. The memory device of claim 3, further comprising: a diffusion barrier layer between each gate electrode layer and each dopant source layer.

5. The memory device of claim 3, wherein each dopant source layer includes a ring-shaped first portion surrounding the respective pillar active region and a second portion between the respective first portions.

6. The memory device of claim 5, wherein the first portion comprises an n-type doped phosphosilicate glass or arsenosilicate glass, or a p-type doped borosilicate glass, containing a dopant at a concentration of 0.01% to 10%.

7. The memory device of claim 5, wherein the second portion comprises a boron-doped oxide.

8. The memory device of claim 3, wherein at least a portion of the source/drain regions protrude outward relative to a remainder of the columnar active regions.

9. The memory device of claim 1, wherein the gate electrode layer comprises a metal.

10. The memory device of claim 1, wherein the semiconductor material in the pillar active regions is homogenous.

11. The memory device of claim 1, wherein the pillar active region is hollow and filled with a dielectric.

12. The memory device of claim 1, wherein the storage gate dielectric stack comprises a first gate dielectric layer, a charge trapping layer, and a second gate dielectric layer stacked in sequence.

13. A method of manufacturing a memory device, comprising:

providing an alternating stack of first material layers and gate electrode layers on a substrate;

forming a plurality of holes in the stack;

forming a mask layer on the exposed side wall of the first material layer in the hole;

forming a storage gate dielectric stack on the inner wall of the hole;

filling semiconductor material into the hole, and etching back to make the semiconductor material remain between the mask layers;

selectively etching the storage gate dielectric stack by using the remaining semiconductor material as a mask;

removing the mask layer to expose the side wall of the first material layer, and selectively etching the first material layer through the hole to retract the side wall of the first material layer;

forming a dopant source layer in a space resulting from sidewall retraction of the first material layer;

filling the hole with a semiconductor material and performing heat treatment to drive dopants from the dopant source layer into the semiconductor material; the dopant from the dopant source layer forms a predetermined distribution in the active region resulting in a heavily doped region that serves as a source/drain region having a higher doping concentration than the remaining portion of the active region.

14. The method of claim 13, wherein forming a mask layer comprises:

forming a polysilicon layer on the inner wall of the hole;

carrying out heat treatment to drive impurities into the polycrystalline silicon layer from the first material layer; and

and selectively etching the part, which is not driven by the impurities, in the polycrystalline silicon layer relative to the part, which is driven by the impurities, in the polycrystalline silicon layer.

15. The method of claim 13, wherein the gate electrode layer is a sacrificial gate electrode layer, the method further comprising:

selectively removing the sacrificial gate electrode layer; and

a replacement gate electrode layer is formed in a space obtained by the removal of the sacrificial gate electrode layer.

16. The method of claim 13, wherein a hollow semiconductor material is formed along an inner wall of the hole, the method further comprising: a dielectric layer is filled inside the hollow semiconductor material.

17. The method of claim 13, wherein providing the alternating stack further comprises:

a diffusion barrier layer is disposed between the gate electrode layer and the first material layer.

18. An electronic device comprising a memory device as claimed in any one of claims 1 to 12.

19. The electronic device of claim 18, comprising a smartphone, a computer, a wearable smart device, a mobile power source, a robot, a smart chip.