CN105826323A - Memory element and making method thereof - Google Patents
Memory element and making method thereof Download PDFInfo
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- CN105826323A CN105826323A CN201510003971.6A CN201510003971A CN105826323A CN 105826323 A CN105826323 A CN 105826323A CN 201510003971 A CN201510003971 A CN 201510003971A CN 105826323 A CN105826323 A CN 105826323A
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- 238000000059 patterning Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
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- 238000002360 preparation method Methods 0.000 description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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Abstract
The invention discloses a memory element and a making method thereof. The memory element comprises a first conductive strip, a first storage layer, a first conductive column, a first dielectric layer, and a first conductive plug. The first conductive strip extends along a first direction. The first storage layer extends along a second direction, is adjacent to the first conductive strip, and overlaps with the first conductive strip to define a first storage area on the first storage layer. The first conductive column extends along the second direction, and is adjacent to and overlaps with the first storage area. The first dielectric layer extends along the second direction, and is adjacent to the first conductive strip, the first storage layer and the first conductive column. The first conductive plug extends along the second direction, at least partially overlaps with the first conductive strip, and is electrically isolated from the first conductive strip, the first storage layer and the first conductive column through the first dielectric layer.
Description
Technical field
The invention relates to a kind of non-volatile memory device and preparation method thereof.In particular to a kind of three-dimensional (Three-Dimension, 3D) non-volatile memory device and preparation method thereof.
Background technology
Traditional, nonvolatile memories (non-volatilememory) element, such as nand flash memory element, typically can use multiple memory element that the conductive strips (stripe) of monocrystal silicon or polysilicon material concatenates between bit line and source electrode line.And in order to reduce the series resistor (seriesresistance) between memory element, it will usually the monocrystal silicon asked or polycrystalline silicon band to series winding memory element carry out ion implantation doping.But, when making the nand flash memory element with 3-dimensional multi-layered memory array, owing to polysilicon or mono-crystalline epitaxial silicon conductive strips can form a multi-laminate structure with multiple dielectric layer laminations, memory element is then positioned on the vertical of multi-laminate structure；Polycrystalline silicon band between memory element to inject ion admixture, processing step not only can be made to complicate, increase the heat budget (thermalbudget) of technique, and the diffusion of ion admixture controls to be difficult to, easily understand the reading of disturbance storage element, program and wipe (program/erase), and then cause component failure.
Therefore, there is a need to provide a kind of more advanced memory component and preparation method thereof, to improve known technology problem encountered.
Summary of the invention
An embodiment according to this specification, it is provided that a kind of memory component, comprising: the first conductive strips, the first accumulation layer, the first conductive columns, the first dielectric layer and the first conductive plunger.First conductive strips extends in a first direction.First accumulation layer extends in a second direction, and overlapping with the first conductive strips, and defines the first memory block at the first accumulation layer and the first conductive strips overlapping.First conductive columns extends in a second direction, and adjacent first accumulation layer and overlapping with the first memory block.First dielectric layer extends in a second direction, and adjacent first conductive strips, the first accumulation layer and the first conductive columns.First conductive plunger, extends in a second direction, and least partially overlapped with the first conductive strips, and is electrically isolated with the first conductive strips, the first accumulation layer and the first conductive columns by the first dielectric layer.
Another embodiment according to this specification, it is provided that the manufacture method of a kind of memory component, comprises the steps: first to form multilayer laminated (multi-layerstack) structure on the surface of base material.Patterned multilayer laminated construction again, to form multiple carinate multilayer laminated (ridge-shapedstacks), makes each carinate multilayer laminated at least include a conductive strips extended along a first direction.Then, on the bottom and sidewall of these at least one grooves of carinate multilayer laminated, storage material layer is formed.Then at these carinate multilayer laminated upper formation conductive material layers, and fill up groove.Then, patterning conductive material layer and storage material layer, to form multiple through hole among groove, use outside a part of base material and conductive strips are exposed to.Wherein, the storage material layer of patterning at least includes an accumulation layer being positioned in groove；The conductive material layer of patterning at least includes a conductive columns being positioned in groove, and defines a memory block at this accumulation layer and conductive strips overlapping.Afterwards, in the sidewall of through hole and be exposed on outer base material and form dielectric layer.Form multiple conductive plunger again, respectively partially fill these through holes, and make conductive plunger at least partly overlap with conductive strips.Follow-up, on these conductive plungers, form multiple dielectric plugs, to fill up these through holes.Then, patterning conductive material layer again, to form at least one wordline in carinate multilayer laminated top, extend along third direction, and in electrical contact with conductive columns.
According to above-described embodiment, the present invention is to provide a kind of three-dimensional storage element and preparation method thereof.Three-dimensional storage element at least includes multiple stratum；Each stratum comprises multiple memory element, and is contacted by the conductive strips extended in a first direction.Each memory element includes accumulation layer and the conductive columns extended in a second direction.Wherein, accumulation layer adjoins conductive strips, and in the position overlapping with conductive strips, defines memory block.Conductive columns contiguous storage layer, and overlapping with memory block.There is between the conductive columns of adjacent two memory element the conductive plunger of a parallel electrically conductive column, least partially overlapped with the conductive strips concatenating two memory element, and by dielectric layer, conductive plunger is electrically isolated with adjacent two memory element and conductive strips respectively.
Configuration mode due to conductive plunger Yu dielectric layer, conductive plunger is made to have the function of floating grid, when three-dimensional storage element operates, conductive plunger can have an induced voltage because of conductive columns conducting, inversion layer can be formed in the conductive strips of adjacent two memory element of contacting, contribute to reducing the series resistor between two memory element.Therefore, it is not required to the conductive strips of adjacent two memory element of contacting is carried out ion implantation doping, the series resistor between memory element can be reduced.The problem that known technology is complicated because of the processing step using ion implantation doping process to be caused, heat budget increases and disturbance storage element reads, programs and wipe can be solved simultaneously.
Accompanying drawing explanation
In order to the above embodiment of the present invention and other objects, features and advantages can be become apparent, especially exemplified by several preferred embodiments, and coordinate institute's accompanying drawings, be described in detail below:
Figure 1A is the structural perspective according to the multi-layer laminate structure depicted in one embodiment of the invention；
Figure 1B is the structure top view according to the multi-layer laminate structure depicted in Figure 1A；
Fig. 2 A is to illustrate the multi-layer laminate structure to Figure 1A to carry out the structural perspective after Patternized technique；
Fig. 2 B is according to the structure top view depicted in Fig. 2 A；
Fig. 3 A is to illustrate sequentially to form the structural perspective after storage material layer and conductive material layer in the structure of Fig. 2 A；
Fig. 3 B is according to the structure top view depicted in Fig. 3 A；
Fig. 4 A be illustrate the conductive material layer to Fig. 3 B and storage material layer pattern after structure top view；
Fig. 4 B is along the part-structure perspective view depicted in the tangent line S41 of Fig. 4 A；
Fig. 4 C is along the part-structure perspective view depicted in the tangent line S42 of Fig. 4 A；
Fig. 5 A is to be shown in the structure of Fig. 4 B forming the structure top view after dielectric layer；
Fig. 5 B is along the part-structure perspective view depicted in the tangent line S51 of Fig. 5 A；
Fig. 5 C is along the part-structure perspective view depicted in the tangent line S52 of Fig. 5 A；
Fig. 6 A is the structure top view being shown in the structure of Fig. 5 A being formed after multiple conductive plunger；
Fig. 6 B is along the part-structure perspective view depicted in the tangent line S61 of Fig. 6 A；
Fig. 6 C is along the part-structure perspective view depicted in the tangent line S62 of Fig. 6 A；
Fig. 7 A is the structure top view being shown in the structure of Fig. 6 A being formed after multiple dielectric plugs；
Fig. 7 B is along the part-structure perspective view depicted in the tangent line S71 of Fig. 7 A；
Fig. 7 C is along the part-structure perspective view depicted in the tangent line S72 of Fig. 7 A；
Fig. 8 A is the structure top view being shown in the structure of Fig. 7 A being formed after a plurality of wordline；
Fig. 8 B is along the part-structure perspective view depicted in the tangent line S81 of Fig. 8 A；
Fig. 8 C is along the part-structure perspective view depicted in the tangent line S82 of Fig. 8 A；
Fig. 9 is along the part hierarchical structure generalized section depicted in the X-Y cross section of three-dimensional storage element.
[symbol description]
100: three-dimensional storage element 101: base material
102: through hole 103: accumulation layer
104: conductive columns 105: conductive strips
106: memory block 108: conductive plunger
109: dielectric plugs 110: multi-layer laminate structure
110a: groove 110b: carinate multilayer laminated
Sidewall 111-118: the conductive layer of 110c: groove
121-128: insulating barrier 130: patterning hard mask layer
130a: groove opening 140: storage material layer
150: conductive material layer 160: dielectric layer
170: wordline 180a-180f: memory element
S51, S52, S61S62, S71, S72, S81, S82, S91 and S92: tangent line
Detailed description of the invention
The present invention provides a kind of three-dimensional storage element and preparation method thereof, can reduce the series resistor between memory element in the case of being not required to the conductive strips of two consecutive storage units of contacting is carried out ion implantation doping.In order to become apparent the above embodiment of the present invention and other objects, features and advantages, several three-dimensional storage elements cited below particularly and preparation method thereof are as preferred embodiment, and coordinate institute's accompanying drawings to elaborate.
But must be noted that these specific case study on implementation and methods, be not limited to the present invention.The present invention still can use other features, element, method and parameter to be carried out.The proposition of preferred embodiment, is only the technical characteristic illustrating the present invention, is not limited to scope of the presently claimed invention.This technical field has usually intellectual, without departing from the scope of the present invention, will can make impartial modification and change according to the description of description below.Different embodiments with graphic among, identical element, will be represented with identical component symbol.
The method making three-dimensional storage element 100, comprises the steps: first to be formed on the surface of base material 101 multi-layer laminate structure (multi-layerstack) 110.Refer to Figure 1A and Figure 1B, Figure 1A is the structural perspective according to the multi-layer laminate structure 110 depicted in one embodiment of the invention.Figure 1B is the structure top view according to the multi-layer laminate structure 110 depicted in Figure 1A.In some embodiments of the invention, multi-layer laminate structure 110 is formed on base material 101.Multi-layer laminate structure 110 includes multiple conductive layer 111-118 and multiple insulating barrier 121-128.In the present embodiment, insulating barrier 121-128 and conductive layer 111-118 is along the Z-direction depicted in Figure 1A, lamination interlaced with each other on base material 101, makes conductive layer 111 be positioned at the bottom of multi-layer laminate structure 110, and insulating barrier 128 is positioned at the top layer of multi-layer laminate structure 110.
Conductive layer 111-118 can be by conducting semiconductor material, such as doped with the N-shaped polysilicon of phosphorus or arsenic, or N-shaped epitaxial monocrystalline silicon, constituted.Additionally, conductive layer 111-118 can also be made up of p-type or the p-type epitaxial monocrystalline silicon doped with boron.On the other hand, conductive layer 111-118 can also be by undoped semi-conducting material, and the most undoped polysilicon or epitaxial monocrystalline silicon are constituted.In the present embodiment, conductive layer 111-118 is to be made up of non-impurity-doped polysilicon.The crystallite dimension (grainsize) of non-impurity-doped polysilicon, preferably can be with essence between 400 nanometers (nm) to 600 nanometers；The sheet resistance (sheetresistance) of non-impurity-doped polysilicon can be with essence between 107Ohm/square to 1011Between ohm/square.The thickness of conductive layer 111-118 each can be with essence between 5 nanometers to 40 nanometers.
Insulating barrier 121-128 can be by dielectric material, such as Si oxide (oxide), silicon nitride (nitride), silicon nitrogen oxides (oxynitride), silicate (silicate) or other materials, constituted.The thickness of each insulating barrier 121-128 can be with essence between 10 nanometers to 50 nanometers.In some embodiments of the invention, conductive layer 111-118 and insulating barrier 121-128 can pass through, and such as low-pressure chemical vapor deposition (LowPressureChemicalVaporDeposition, LPCVD) technique, is made.
Then, multi-layer laminate structure 110 is carried out a Patternized technique, to form multiple carinate multilayer laminated 110b.Refer to Fig. 2 A and Fig. 2 B, Fig. 2 A is to illustrate the multi-layer laminate structure 110 to Figure 1A to carry out the structural perspective after Patternized technique.Fig. 2 B is according to the structure top view depicted in Fig. 2 A.In some embodiments of the invention, the Patternized technique of multi-layer laminate structure 110, including first forming a patterning hard mask layer 130 at multi-layer laminate structure 110 top.In the present embodiment, patterning hard mask layer 130 is formed at the top surface of insulating barrier 128.Wherein, patterning hard mask layer 130 includes multiple groove opening 130a downwardly extended along Z-direction.The major axis of these groove opening 130a extends along X-direction, and outside the top surface of a part of insulating barrier 128 is exposed to.
In some embodiments of the invention, patterning hard mask layer 130 can be a kind of by chemical gaseous phase deposition (ChemicalVaporDeposition, CVD) technique, at the advanced patterned film (AdvancedPatterningFilm, APF) that the top surface of multi-layer laminate structure 110 is formed.These groove opening 130a, then be to remove a part of advanced patterned film by photoetching (photolithography) technique to be formed.In the present embodiment, each groove opening 130a all has same size, and each groove opening 130a is all oblong aperture pattern (but being not limited).
Then, with patterning hard mask layer 130 as etching mask, by anisotropic etching technics (anisotropicetchingprocess), such as reactive ion etching (ReactiveIonEtching, RIE) technique, performs etching multi-layer laminate structure 110.Use among multi-layer laminate structure, form the groove 110a extended along Z-direction, multi-layer laminate structure 110 is divided into multiple carinate multilayer laminated 110b, and outside the subregion of base material 101 is exposed to via groove 110a.In the present embodiment, each carinate multilayer laminated 110b comprises the conductive layer 111-118 of a part of strip, can be as the conductive strips 105 of multiple memory element of the same stratum being positioned at same carinate multilayer laminated 110b in series winding three-dimensional storage element 100.
Then, refer to Fig. 3 A and Fig. 3 B, Fig. 3 A is to illustrate sequentially to form the structural perspective after storage material layer 140 and conductive material layer 150 in the structure of Fig. 2 A.Fig. 3 B is according to the structure top view depicted in Fig. 3 A.In some embodiments of the invention, storage material layer 140 can be made by low-pressure chemical vapor deposition process.Accumulation layer 140 can be made up of the composite bed (that is, ONO layer) comprising silicon oxide (siliconoxide) layer, silicon nitride (siliconnitride) layer and silicon oxide layer.In the present embodiment, storage material layer 140 covers and is positioned on the top of carinate lamination 110 and the bottom (being i.e. exposed to outer base material 101 by groove 110a) of groove 110a and sidewall 110c.
After forming accumulation layer 140, on these carinate multilayer laminated 110b, form conductive material layer 150, cover storage material layer 140, and fill up groove 110a.In some embodiments of the invention, conductive material layer 150 can be made by low-pressure chemical vapor deposition process.nullConstitute the material of conductive material layer 150，The N-shaped polysilicon (or N-shaped epitaxial monocrystalline silicon) doped with phosphorus or arsenic can be comprised、P-type (or p-type epitaxial monocrystalline silicon) doped with boron、Undoped polysilicon、Metal silicide (silicides)，Such as titanium silicide (TiSi)、Cobalt silicide (CoSi) or SiGe (SiGe)、Oxide semiconductor (oxidesemiconductors)，Such as indium zinc oxide (InZnO) or indium gallium zinc (InGaZnO)、Metal，Such as aluminum (A1)、Copper (Cu)、Tungsten (W)、Titanium (Ti)、Cobalt (Co)、Nickel (Ni)、Titanium nitride (TiN)、Tantalum nitride (TaN) or tantalum nitride aluminium (TaAlN)，Or the compositions of the above-mentioned material of two or more is constituted.
Then, patterning conductive material layer 150 and storage material layer 140, multiple through hole 102 is formed among groove 110a, use outside a part of base material 101 and conductive strips 105 are exposed to, and respectively among the conductive material layer 150 being patterned and the storage material layer 140 being patterned, define multiple accumulation layer 103 and multiple conductive columns 104.Refer to Fig. 4 A, Fig. 4 B and Fig. 4 C, Fig. 4 A be illustrate the conductive material layer 150 to Fig. 3 B and storage material layer 140 pattern after structure top view.Fig. 4 B is along the part-structure perspective view depicted in the tangent line S41 of Fig. 4 A.Fig. 4 C is along the part-structure perspective view depicted in the tangent line S42 of Fig. 4 A.
In some embodiments of the invention, through hole 102 is by anisotropic etching technics, such as reactive ion etching process, remove and be positioned at a part of conductive material layer 150 among groove 110a and a part of storage material layer 140 is formed, outside making the conductive strips 105 of some be exposed to by the sidewall of through hole 102；And remained in a part of conductive material layer 150 among groove 110a and storage material layer 140, then can form multiple strip accumulation layer 103 extended along Z-direction and multiple conductive columns 104 respectively.
In the present embodiment, each accumulation layer 103 is positioned on groove 110a sidewall with multiple, but a part of conductive strips 105 not exposed by through hole 102 adjoins；And in the position that each accumulation layer 103 is overlapping with each conductive strips 105, define a memory block 106.Each conductive columns 104 adjoins an accumulation layer 103, and overlapping with the memory block 106 of corresponding accumulation layer 103.Wherein, accumulation layer 103, conductive strips 105 and the conductive columns 104 overlapping with same memory block 106, three may make up a memory element.And by multiple accumulation layers 103, conductive strips 105 and 104 common definition of conductive columns multiple memory element out, may make up the memory array of three-dimensional storage element 100.
But in other embodiments of the present invention, it is positioned at the memory block 106 that conductive strips 105 institute overlapping with accumulation layer 103 common definition of memory array periphery goes out, the active area of transistor (not illustrating) can be selected as the string row selecting transistor of three-dimensional storage element 100 or ground connection, and the corresponding conductive columns 104 overlapping with this active area, then with the selection line (StringSelectLine of serial, SSL) or ground connection select line (GroundSelectLine, GSL) (not illustrating) connect.
Afterwards, in the sidewall (comprise be exposed to via through hole 110a outer conductive strips 105) of through hole 102 and be i.e. exposed to via through hole 110a on outer base material 101 and form dielectric layer 160.Refer to Fig. 5 A, Fig. 5 B and Fig. 5 C, Fig. 5 A is to be shown in the structure of Fig. 4 A forming the structure top view after dielectric layer 160.Fig. 5 B is along the part-structure perspective view depicted in the tangent line S51 of Fig. 5 A.Fig. 5 C is along the part-structure perspective view depicted in the tangent line S52 of Fig. 5 A.
Dielectric layer 160 can be made by low-pressure chemical vapor deposition process.Constitute the material of dielectric layer 160, can be identical with the material constituting insulating barrier 121-128.Among some embodiments of the present invention, dielectric layer 160 can be to be made up of the dielectric material comprising Si oxide, silicon nitride, silicon nitrogen oxides, silicate or combinations thereof.Among the present embodiment, the material constituting dielectric layer 160 can include silicon oxide.It addition, dielectric layer 160 preferably thickness is between 3nm to 10nm.
Afterwards, then form multiple conductive plunger 108, be partially filled with among each through hole 102, and make each conductive plunger 108 be at least exposed to outer conductive strips 105 with each by corresponding through hole 102 to partly overlap.Refer to Fig. 6 A, Fig. 6 B and Fig. 6 C, Fig. 6 A is to be shown in the structure of Fig. 5 A forming the structure top view after multiple conductive plunger 108.Fig. 6 B is along the part-structure perspective view depicted in the tangent line S61 of Fig. 6 A.Fig. 6 C is along the part-structure perspective view depicted in the tangent line S62 of Fig. 6 A.In the present embodiment, at least partly overlapping with each conductive strips 105 in order to ensure each conductive plunger 10g, each conductive plunger 108 must be filled with corresponding through hole 102, until exceeding the bottom of the conductive strips 105 of top.In other words, the height of conductive plunger 108, base material 101 start at, it is necessary to exceed the top of conductive layer 118.
Follow-up, on these conductive plungers 108, form multiple dielectric plugs 109, to fill up these through holes 102, and be connected with the dielectric layer 160 being positioned on through hole 102 sidewall.Refer to Fig. 7 A, Fig. 7 B and Fig. 7 C, Fig. 7 A is to be shown in the structure of Fig. 6 A forming the structure top view after multiple dielectric plugs 109.Fig. 7 B is along the part-structure perspective view depicted in the tangent line S71 of Fig. 7 A.Fig. 7 C is along the part-structure perspective view depicted in the tangent line S72 of Fig. 7 A.In some embodiments of the invention, dielectric plugs 109 can be made by low-pressure chemical vapor deposition process.Constitute the material of dielectric plugs 109, can be identical with the material constituting dielectric layer 160.Among some embodiments of the present invention, dielectric plugs 109 can be to be made up of the dielectric material comprising Si oxide, silicon nitride, silicon nitrogen oxides, silicate or combinations thereof.Among the present embodiment, the material constituting dielectric plugs 109 can include silicon oxide.
Then, it is pointed to the conductive material layer 150 above carinate multilayer laminated 110b and carries out Patternized technique again, form a plurality of wordline 170 with the top in carinate multilayer laminated 110b, extend along Y direction, and in electrical contact with conductive columns 104.Refer to Fig. 8 A, Fig. 8 B and Fig. 8 C, Fig. 8 A is to be shown in the structure of Fig. 8 A forming the structure top view after a plurality of wordline 170.Fig. 8 B is along the part-structure perspective view depicted in the tangent line S81 of Fig. 8 A.Fig. 8 C is along the part-structure perspective view depicted in the tangent line S82 of Fig. 8 A.Among some embodiments of the present invention, a plurality of wordline 170 is formed on the top of carinate multilayer laminated 110b；And each wordline 170 is in electrical contact with multiple conductive columns 104 respectively.Wherein, between two adjacent wordline 170, configure a conductive plunger 108, and conductive plunger 108 is electrically isolated by the wordline 170 that dielectric layer 160 and dielectric plugs 109 are adjacent with two.
Follow-up, then the preparation of three-dimensional storage element 100 is completed by a succession of last part technology.In the memory array of three-dimensional storage element 100, at least include multiple hierarchical structure being formed on conductive layer 111-118.Such as refer to Fig. 9, Fig. 9 is along the part hierarchical structure generalized section depicted in the X-Y cross section of three-dimensional storage element 100.In the present embodiment, the hierarchical structure depicted in Fig. 9 is on conductive layer 115.Wherein, each hierarchical structure comprises multiple memory element, such as memory element 180a, 180b, 180c, 180d, 180e and 180f；And these memory element 180a, 180b, 180c, 180d, 180e and 180f, all concatenated with one another along X-direction extension via the conductive strips 105 that patterned conductive layer 115 is formed.
These memory element 180a, each of 180b, 180c, 180d, 180e and 180f all include accumulation layer 103 and a conductive columns 104.Wherein, accumulation layer 103 extends along Z axis (vertical X-Y plane) direction, and adjacent conductive strips 105, and in the position overlapping with conductive strips 105, defines memory block 106.Conductive columns 104 also extends along Z-direction, and contiguous storage layer 103, and overlapping with memory block 106.
Two adjacent memory element, such as, have a segment distance D1 in paralleled by X axis direction between memory element 180a and 180b.And it is configured with therebetween dielectric layer 160 and a conductive plunger 108.Wherein, dielectric layer 160 extends along Z-direction, and adjoins adjacent biphase memory element 180a and the conductive strips 105 of 180b, accumulation layer 103 and conductive columns 104 respectively.Conductive plunger 108 extends along Z-direction, and with extend in X direction, be used for concatenating a part of conductive strips 105 of adjacent biphase memory element 180a and 180b least partially overlapped.Dielectric layer 160 is located between the conductive strips 105 of conductive plunger 108 and biphase memory element 180a and 180b, accumulation layer 103 and conductive columns 104 three, makes conductive plunger 108 conductive strips 105, accumulation layer 103 and conductive columns 104 with two consecutive storage unit 180a and 180b can be electrically isolated by dielectric layer 160.Due to, conductive plunger 108 is electrically isolated from one another with conductive strips 105, and at least part of overlapped.Therefore conductive plunger 108 can be as the floating grid of conductive strips 105.When three-dimensional storage element 100 is read out or during programming operation, conductive plunger 108 can have induced voltage because conductive columns 104 turns on, inversion layer can be formed in the conductive strips 105 of series winding two consecutive storage unit 180a and 180b, contribute to and the series resistor that reduces between memory element 180a and 180b.
It is otherwise noted that be formed at adjacent conductive layer, the hierarchical structure being such as positioned on the conductive layer 114 below conductive layer 115 also comprises and the identical structure depicted in Fig. 9.Wherein, the memory layer 103 and the conductive columns 104 that extend along Z-direction in memory element 180a also can be adjacent to each other and overlapping with the conductive strips 105 being positioned on conductive layer 114, and then define another memory element comprising memory block 106 (not illustrating).Due to, intercepting by insulating barrier 124 (not illustrating) between two memory element, the direction at parallel Z axis has a segment distance (not illustrating) the most therebetween.
According to above-described embodiment, the present invention is to provide a kind of three-dimensional storage element and preparation method thereof.Three-dimensional storage element at least includes multiple stratum；Each stratum comprises multiple memory element, and is contacted by the conductive strips extended in a first direction.Each memory element includes accumulation layer and the conductive columns extended in a second direction.Wherein, accumulation layer adjoins conductive strips, and in the position overlapping with conductive strips, defines memory block.Conductive columns contiguous storage layer, and overlapping with memory block.There is between the conductive columns of adjacent two memory element the conductive plunger of a parallel electrically conductive column, least partially overlapped with the conductive strips concatenating two memory element, and by dielectric layer, conductive plunger is electrically isolated with adjacent two memory element and conductive strips respectively.
Configuration mode due to conductive plunger Yu dielectric layer, conductive plunger is made to have the function of floating grid, when three-dimensional storage element operates, conductive plunger can have an induced voltage because of conductive columns conducting, inversion layer can be formed in the conductive strips of adjacent two memory element of contacting, contribute to reducing the series resistor between two memory element.Therefore, it is not required to the conductive strips of adjacent two memory element of contacting is carried out ion implantation doping, the series resistor between memory element can be reduced.The problem that known technology is complicated because of the processing step using ion implantation doping process to be caused, heat budget increases and disturbance storage element reads, programs and wipe can be solved simultaneously.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when depending on being as the criterion that appended claims scope is defined.
Claims (10)
1. a memory component, including:
One first conductive strips, extends along a first direction；
One first accumulation layer, extends along a second direction, overlapping with this first conductive strips, and defines one first memory block at the overlapping of this first accumulation layer Yu this first conductive strips；
One first conductive columns, extends along this second direction, and this first accumulation layer adjacent, and overlapping with this first memory block；
One first dielectric layer, extends along this second direction, and this first conductive strips adjacent, this first accumulation layer and this first conductive columns；And
One first conductive plunger, extends along this second direction, and least partially overlapped with this first conductive strips, and is electrically isolated with this first conductive strips, this first accumulation layer and this first conductive columns by this first dielectric layer.
Memory component the most according to claim 1, further includes:
One second dielectric layer, extends along this second direction, and this first conductive strips adjacent, this first accumulation layer and this first conductive columns, and makes this first conductive columns between this first dielectric layer and this second dielectric layer；And
One second conductive plunger, extends along this second direction, and is electrically isolated with this first conductive strips, this first accumulation layer and this first conductive columns by this second dielectric layer.
Memory component the most according to claim 2, further includes:
One second accumulation layer, extend along this second direction, and overlapping with this first conductive strips, and define one second memory block at this second accumulation layer and this first conductive strips overlapping, and between this second memory block and this first memory block, there is a distance of this first direction parallel；And
One second conductive columns, extends along this second direction, and adjacent and overlapping with this second memory block；Wherein, it is to be electrically isolated by this first dielectric layer between this first conductive plunger and this second conductive columns.
Memory component the most according to claim 3, further includes:
One second conductive strips, extend along this first direction, and overlapping with this first accumulation layer and this second accumulation layer, define one the 3rd memory block and one the 4th memory block respectively, and this first conductive columns is overlapping with the 3rd memory block and the 4th memory block respectively with this second conductive columns；And
One insulating barrier, extends along this first direction, and between this first conductive strips and this second conductive strips.
Memory component the most according to claim 4, further includes:
One first wordline, extends along a third direction, and in electrical contact with this first conductive columns；And
One second wordline, extends along this third direction, and in electrical contact with this second conductive columns；
Wherein, this first conductive plunger is between this first wordline and this second wordline, and electrically isolates with this first wordline and this second wordline.
Memory component the most according to claim 5, further includes:
One first dielectric plugs, is positioned on this first conductive plunger, and contacts with this first dielectric layer and this first conductive plunger；And
One second dielectric plugs, is positioned on this second conductive plunger, and contacts with this second dielectric layer and this second conductive plunger.
Memory component the most according to claim 5, further includes:
Multiple carinate multilayer laminated (ridged-shapedmulti-layerstacks) is positioned on a base material, extend along this first direction, these are carinate multilayer laminated for each of which, all include this first conductive strips, this insulating barrier and this second conductive strips of a part；
This first accumulation layer and this second accumulation layer, lay respectively in these carinate multilayer laminated defined grooves (trench), and be covered in a sidewall of this groove；
This first conductive columns and this second conductive columns, be positioned among these grooves, is covered each by these first accumulation layers and this second accumulation layer；And
This first wordline and this second wordline, be positioned at these carinate multilayer laminated tops.
Memory component the most according to claim 1, further includes:
One second accumulation layer, extends along this second direction, overlapping with this first conductive strips, and defines an active area at this second accumulation layer and this first conductive strips overlapping；And
One second conductive columns, extends along this second direction, and overlapping with this active area, and connects with a serial selection line (StringSelectLine, SSL).
Memory component the most according to claim 1, further includes:
One second accumulation layer, extends along this second direction, overlapping with this first conductive strips, and defines an active area at this second accumulation layer and this first conductive strips overlapping；And
One second conductive columns, extends along this second direction, and overlapping with this active area, and selects line (GroundSelectLine, GSL) to connect with a ground connection.
10. a manufacture method for memory component, including:
A multi-layer laminate structure (multi-layerstack) is formed on a base material；
Pattern this multi-layer laminate structure, multiple carinate multilayer laminated to be formed；Wherein, each these carinate multilayer laminated at least include that a conductive strips extends along a first direction；
In these carinate multilayer laminated between at least one groove one bottom and sidewall on form a storage material layer；
In these carinate multilayer laminated upper formation one conductive material layers, and fill up this groove；
Pattern this conductive material layer and this storage material layer, to form multiple through hole among this groove, outside this base material of a part and this conductive strips being exposed to；Wherein, this conductive material layer of patterning includes at least one conductive columns, is positioned in this groove；This storage material layer of patterning includes at least one accumulation layer, is positioned in this groove；And define a memory block at this accumulation layer and this conductive strips overlapping；
In the sidewall of these through holes and be exposed on this outer base material and form a dielectric layer；
Form multiple conductive plunger, respectively partially fill these through holes, and make these conductive plungers at least partly overlap with this conductive strips；
Multiple dielectric plugs is formed, to fill up these through holes on these conductive plungers；And
Pattern this conductive material layer again, to form at least one wordline in these carinate multilayer laminated tops, extend along a third direction, and in electrical contact with this conductive columns.
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