KR20210080583A - A three-dimensional memory device comprising alternating stacks of source and drain layers and vertical gate electrodes - Google Patents

Abstract

The three-dimensional memory device comprises an alternating stack of source and drain layers positioned over a substrate, gate electrodes extending vertically through each of the source and drain layers of the alternating stack, and a respective gate electrode of the gate electrodes laterally arranged. surrounding memory films, and semiconductor channels laterally surrounding a respective memory film of the memory films and connected to a respective vertically neighboring pair of source and drain layers. The array of memory openings may extend vertically through the alternating stack, and each of the gate electrodes may be located within a respective memory opening of the memory openings.

Description

A three-dimensional memory device comprising alternating stacks of source and drain layers and vertical gate electrodes

Related applications

This application claims the benefit of priority to U.S. Patent Applications Nos. 16/539,103 and 16/539,124, filed on August 13, 2019, the entire contents of which are incorporated herein by reference.

technical field

FIELD OF THE INVENTION The present invention relates generally to the field of semiconductor devices, and more particularly to a three-dimensional memory device comprising an alternating stack of source and drain layers and vertical gate electrodes and methods of manufacturing the same.

A typical three-dimensional NAND memory device includes an alternating stack of word lines and insulating layers positioned over a substrate. Vertical semiconductor channels surrounded by memory films comprising a charge storage layer positioned between a blocking dielectric layer and a tunneling dielectric layer extend vertically in the memory openings through an alternating stack. The bit lines are electrically connected to drain regions located at the top of the semiconductor channels, while the source line or interconnect is electrically connected to the source regions located at the bottom portion of the vertical semiconductor channels.

According to one aspect of the present invention, a three-dimensional memory device comprises an alternating stack of source and drain layers positioned over a substrate, gate electrodes extending vertically through each of the source and drain layers of the alternating stack, and gate electrodes. memory films each laterally surrounding a respective gate electrode, and a respective vertically adjacent pair of a source layer of a source layer and a drain layer of a drain layer each laterally surrounding a respective memory film of the memory films semiconductor channels in contact with the sidewalls of

According to another aspect of the present invention, a method of forming a three-dimensional memory device comprises forming an alternating stack of doped semiconductor source layers and doped semiconductor drain layers over a substrate, a memory opening extending vertically through the alternating stack. forming a continuous semiconductor channel layer within each memory opening - each vertically neighboring one of the doped semiconductor source layer and the doped one of the doped semiconductor drain layers. forming semiconductor channels on the pair of sidewalls, forming memory films over the semiconductor channels, and forming gate electrodes over the memory films, each of the gate electrodes comprising an alternating stack of doped semiconductor source layers and extending vertically through each of the doped semiconductor drain layers.

In accordance with one aspect of the present invention, a three-dimensional memory device comprises an alternating stack of source and drain layers positioned over a substrate, an array of memory openings extending vertically through the alternating stack, gate electrodes, each gate electrode comprising: each memory film positioned in one of the array of memory openings and extending vertically through each of the source and drain layers of an alternating stack, each memory film positioned in one of the array of memory openings and a respective gate of the gate electrodes laterally surrounding the electrode, and vertical stacks of semiconductor channels laterally surrounding a respective memory film of memory films, wherein each of the vertical semiconductor channels is in contact with a respective vertically neighboring horizontal surface. do.

According to another aspect of the present invention, a method of forming a three-dimensional memory device comprises forming an alternating stack of doped semiconductor source layers and doped semiconductor drain layers over a substrate, a memory opening extending vertically through the alternating stack. forming a memory film and a gate electrode in each memory opening, the memory film and the gate electrode extending vertically through each of the doped semiconductor source layers and the doped semiconductor drain layers of the alternating stack; and respective vertically neighboring pairs of horizontal surfaces of a doped one of the doped semiconductor source layers and a doped one of the doped semiconductor drain layers before or after formation of the memory film and the gate electrode forming a vertical stack of semiconductor channels thereon, each vertical stack of semiconductor channels laterally surrounding a respective memory film and a respective gate electrode.

1 includes a source sacrificial material layer, a doped semiconductor source layer, a channel level insulating layer, a doped semiconductor drain layer, a drain sacrificial material layer, and an inter-transistor level insulating layer over a substrate according to a first embodiment of the present invention; is a schematic vertical cross-sectional view of a first exemplary structure after formation of multiple instances of a unit layer stack.
2 is a schematic vertical cross-sectional view of a first exemplary structure after formation of stepped surfaces according to a first embodiment of the present invention;
3A is a schematic vertical cross-sectional view of a first exemplary structure after formation of retro-stepped portions of dielectric material in accordance with a first embodiment of the present invention;
3B is a top view of the first exemplary structure of FIG. 3A ; The vertical plane A-A' is the plane of the cross-section in FIG. 3A .
4 is a schematic vertical cross-sectional view of a first exemplary structure after formation of memory aperture filling structures in accordance with a first embodiment of the present invention.
5 is a schematic vertical cross-sectional view of a first exemplary structure after formation of contact pad structures in accordance with a first embodiment of the present invention.
6A is a schematic vertical cross-sectional view of a first exemplary structure after formation of a backside trench in accordance with a first embodiment of the present invention.
6B is a top view of the first exemplary structure of FIG. 6A . The vertical plane A-A' is the plane of the cross-section in FIG. 6A .
7 is a schematic vertical cross-sectional view of a first exemplary structure after formation of source level backside recesses and drain level recesses in accordance with a first embodiment of the present invention.
8 is a schematic vertical cross-sectional view of a first exemplary structure after formation of metal source layers, metal drain layers, and a backside trench fill structure in accordance with a first embodiment of the present invention.
9A is a schematic vertical cross-sectional view of a first exemplary structure after formation of contact via structures in accordance with a first embodiment of the present invention. 9B is a partial perspective top view of the first exemplary structure of FIG. 9A . The vertical plane A-A' is the plane of the cross-section in FIG. 9A.
10 is a diagram comprising a source sacrificial material layer, a doped semiconductor source layer, an insulating layer, a doped semiconductor drain layer, a drain sacrificial material layer, and an inter-transistor level sacrificial material layer over a substrate in accordance with a second embodiment of the present invention; A schematic vertical cross-sectional view of a second exemplary structure after formation of multiple instances of a unit layer stack.
11 is a schematic vertical cross-sectional view of a second exemplary structure after formation of stepped surfaces according to a second embodiment of the present invention;
12A is a schematic vertical cross-sectional view of a second exemplary structure after formation of an array of reverse-stepped dielectric material portions and memory openings in accordance with a second embodiment of the present invention.
12B is a top view of the second exemplary structure of FIG. 12A . The vertical plane A-A' is the plane of the cross-section in Fig. 12A.
13 is a schematic vertical cross-sectional view of a second exemplary structure after formation of memory aperture filling structures in accordance with a second embodiment of the present invention.
14 is a schematic vertical cross-sectional view of a second exemplary structure after formation of contact pad structures in accordance with a second embodiment of the present invention.
15A is a schematic vertical cross-sectional view of a second exemplary structure after formation of a backside trench in accordance with a second embodiment of the present invention.
15B is a top view of the second exemplary structure of FIG. 15A . The vertical plane A-A' is the plane of the cross-section in Fig. 15A.
16 is a schematic vertical cross-sectional view of a second exemplary structure after formation of source level backside recesses and drain level backside recesses in accordance with a second embodiment of the present invention.
17 is a schematic vertical cross-sectional view of a second exemplary structure after formation of metal source layers and metal drain layers in accordance with a second embodiment of the present invention.
18 is a vertical cross-sectional view of a second exemplary structure after formation of inter-transistor backside recesses in accordance with a second embodiment of the present invention.
19 is a vertical cross-sectional view of a second exemplary structure after dividing each successive semiconductor channel layer into a set of individual semiconductor channels that are vertically spaced apart from each other, in accordance with a second embodiment of the present invention.
20 is a vertical cross-sectional view of a second exemplary structure after deposition of a replacement insulating layer in inter-transistor backside recesses and formation of a backside trench filling structure, in accordance with a second embodiment of the present invention;
21 is a schematic vertical cross-sectional view of a second exemplary structure after formation of contact via structures in accordance with a second embodiment of the present invention.
22 includes a source sacrificial material layer, a doped semiconductor source layer, a channel level insulating layer, a doped semiconductor drain layer, a drain sacrificial material layer, and an inter-transistor level insulating layer over a substrate according to a third embodiment of the present invention. is a schematic vertical cross-sectional view of a third exemplary structure after formation of multiple instances of a unit layer stack.
23 is a schematic vertical cross-sectional view of a third exemplary structure after formation of stepped surfaces according to a third embodiment of the present invention;
24A is a schematic vertical cross-sectional view of a third exemplary structure after formation of an array of reverse-stepped dielectric material portions and memory openings in accordance with a third embodiment of the present invention.
24B is a top view of the third exemplary structure of FIG. 24A ; The vertical plane A-A' is the plane of the cross-section in Fig. 24A.
25 is a schematic vertical cross-sectional view of a third exemplary structure after formation of annular cavities at each level of channel level insulating layers, in accordance with a third embodiment of the present invention.
26 is a schematic vertical cross-sectional view of a third exemplary structure after formation of vertical stacks of individual semiconductor channels in accordance with a third embodiment of the present invention.
27 is a schematic vertical cross-sectional view of a third exemplary structure after formation of memory aperture filling structures in accordance with a third embodiment of the present invention.
28 is a schematic vertical cross-sectional view of a third exemplary structure after formation of contact pad structures in accordance with a third embodiment of the present invention.
29A is a schematic vertical cross-sectional view of a third exemplary structure after formation of a backside trench in accordance with a third embodiment of the present invention.
29B is a top view of the third exemplary structure of FIG. 29A . The vertical plane A-A' is the plane of the cross-section in Fig. 29A.
30 is a schematic vertical cross-sectional view of a third exemplary structure after formation of source level backside recesses and drain level recesses in accordance with a third embodiment of the present invention.
31 is a schematic vertical cross-sectional view of a third exemplary structure after formation of metal source layers, metal drain layers, and backside trench fill structure in accordance with a third embodiment of the present invention.
32 is a schematic vertical cross-sectional view of a third exemplary structure after formation of contact via structures in accordance with a third embodiment of the present invention.
33 includes a source sacrificial material layer, a doped semiconductor source layer, a channel level sacrificial material layer, a doped semiconductor drain layer, a drain sacrificial material layer, and an inter-transistor level insulating layer over a substrate in accordance with a fourth embodiment of the present invention. is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of multiple instances of a unit layer stack.
34 is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of stepped surfaces according to a fourth embodiment of the present invention;
35A is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of an array of reverse-stepped dielectric material portions and memory openings in accordance with a fourth embodiment of the present invention.
35B is a top view of the fourth exemplary structure of FIG. 35A . The vertical plane A-A' is the plane of the cross-section in Fig. 35A.
36 is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of memory aperture filling structures in accordance with a fourth embodiment of the present invention.
37 is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of contact pad structures in accordance with a fourth embodiment of the present invention.
38A is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of a backside trench according to a fourth embodiment of the present invention;
38B is a top view of the fourth exemplary structure of FIG. 38A . The vertical plane A-A' is the plane of the cross section of FIG. 38A.
39 is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of source level backside recesses and drain level recesses in accordance with a fourth embodiment of the present invention.
40 is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of metal source layers, metal drain layers, and backside trench fill structure in accordance with a fourth embodiment of the present invention.
41 is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of channel level backside recesses by removal of channel level sacrificial material layers in accordance with a fourth embodiment of the present invention.
42 is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of layers of semiconductor channel material in accordance with a fourth embodiment of the present invention.
43 is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of channel level insulating layers and backside trench fill structures in accordance with a fourth embodiment of the present invention.
44 is a schematic vertical cross-sectional view of a fourth exemplary structure after formation of contact via structures in accordance with a fourth embodiment of the present invention.
45 is a schematic vertical view of an alternative embodiment of a fourth exemplary structure formed by omission of source sacrificial layers and drain sacrificial layers in a process step corresponding to the process steps of FIG. 34 in accordance with a fourth embodiment of the present invention; It is a cross section.
Figure 46 is a schematic vertical cross-sectional view of an alternative embodiment of a fourth exemplary structure in a process step corresponding to the process steps of Figure 37 in accordance with a fourth embodiment of the present invention;
Figure 47 is a schematic vertical cross-sectional view of an alternative embodiment of a fourth exemplary structure in a process step corresponding to the process steps of Figure 44 according to a fourth embodiment of the present invention;
48 is a schematic circuit diagram of a three-dimensional memory device in accordance with various embodiments of the present invention.

As discussed above, embodiments of the present invention provide an alternating stack of horizontal source lines, source layers, drain layers and bit lines, and vertical gate electrodes surrounded by a semiconductor channel and memory film extending through the alternating stack. three-dimensional memory devices comprising, and methods of manufacturing the same, various aspects of which are described below The three-dimensional memory devices of embodiments of the present invention provide simpler electrical connections to source lines, drain lines, and word lines. The semiconductor channel width can be increased in such devices, which provides a tighter threshold voltage distribution and allows the use of higher cell currents for faster memory speeds. Some embodiments further provide electrical isolation between adjacent semiconductor channels.

The drawings are not drawn to scale. Multiple instances of an element may overlap when a single instance of an element is illustrated, unless the absence of overlapping elements is explicitly stated or clearly indicated otherwise. Ordinal numbers such as “first,” “second,” and “third” are merely employed to identify similar elements, and different ordinal numbers may be employed throughout the present specification and claims. Like reference numerals refer to like elements or like elements. Unless otherwise indicated, elements having the same reference numerals are assumed to have the same composition and the same function. Unless otherwise indicated, “contact” between elements refers to direct contact between elements that provides an edge or surface shared by the elements. As used herein, a first element positioned “on” a second element may be positioned on the outer surface of the surface of the second element or on the inner face of the second element. As used herein, a first element is positioned “directly on” a second element when there is physical contact between the surface of the first element and the surface of the second element. As used herein, a first element is "electrically connected" to a second element when there is a conductive path made of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or “in-process” structure refers to a temporary structure in which the shape or composition of at least one component therein is subsequently modified. .

As used herein, “layer” refers to a portion of a material comprising a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Also, the layer may be a region of a continuous structure that is homogeneous or heterogeneous with a thickness less than the thickness of the continuous structure. For example, the layer may be positioned between any pair of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and/or along a tapered surface. The substrate may be one layer, may include one or more layers therein, or may have one or more layers thereon, above, and/or below.

As used herein, a first surface when a second surface overlies or overlies a first surface, and when there is a vertical or substantially vertical plane comprising the first surface and the second surface. and the second surfaces “perpendicularly coincide” with each other. A substantially vertical plane is a plane extending straight along a direction deviating from the vertical direction by an angle of less than 5 degrees. A vertical or substantially vertical plane is straight along a vertical or substantially vertical direction, and may or may not include a curvature along a vertical or substantially vertical direction.

A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed on a single substrate, such as a semiconductor wafer, without intervening substrates. The term “monolithic” means that the layers of each level of the array are deposited directly on the layers of each underlying level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167 entitled "Three-dimensional Structure Memory," non-monolithic by forming memory levels on separate substrates and stacking the memory levels vertically. Stacked memories have been constructed. Substrates may be thinned or removed from the memory levels prior to bonding, but since the memory levels are initially formed over separate substrates, such memories are not truly monolithic three-dimensional memory arrays. Various three-dimensional memory devices of the present invention include monolithic three-dimensional NAND string memory devices, and may be fabricated employing various embodiments described herein.

Referring to FIG. 1 , a first exemplary structure is illustrated according to a first embodiment of the present invention, by forming a lowermost insulating layer 32B over a substrate 9 and an optional source over the lowermost insulating layer 32B. Sacrificial material layer 42S, doped semiconductor source layer 24, channel level insulating layer 32C (also referred to as first insulating layer), doped semiconductor drain layer 26, optional drain sacrificial material layer 42D, and an inter-transistor level insulating layer 321 (also referred to as a second insulating layer) by forming multiple instances of a unit layer stack. In an alternative configuration, one or both of the optional source sacrificial material layers 42S and/or the optional drain sacrificial material layer 42D may be omitted. As used herein, “unit layer stack” refers to a layer stack of multiple layers that functions as a unit of repetition within a structure in which multiple instances of the layer stack are repeated. A topmost insulating layer 32T may be formed in place of the inter-transistor level insulating layer 321 for the top instances of the unit layer stacks 42S, 24, 32C, 26, 42D, 321. The total number of iterations of the unit layer stack 42S, 24, 32C, 26, 42D, 321 may be equal to the total number of levels of vertical field effect transistors to be subsequently formed, which is the memory element to be subsequently formed. may be equal to the total number of levels of As used herein, “level” refers to the volume of a device located between a horizontal plane containing the top surface of an element of the device and a horizontal plane containing the bottom surface of an element of the device.

Accordingly, the channel level insulating layer 32C is an insulating layer formed between a horizontal plane including a top surface of a semiconductor channel to be subsequently formed and a horizontal plane including a bottom surface of a semiconductor channel to be subsequently formed. The inter-transistor level insulating layer 321 is an insulating layer formed between a horizontal plane including a top surface of an inter-transistor gap to be subsequently formed and a horizontal plane including a bottom surface of an inter-transistor gap to be formed subsequently. The number of repetitions of the unit layer stack in multiple instances of the unit layer stack may range from 2 to 1024, such as 8 to 128, although fewer and greater numbers of repetitions may also be employed.

In the present invention, the unit layer stack comprises a selective source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel level insulating layer 32C, a doped semiconductor drain layer 26, and a selective drain sacrificial material layer 42D. ), and an embodiment wherein the inter-transistor level insulation layer 321 is described as employing an embodiment comprising a layer stack arranged from bottom to top, but in which the layer stack is arranged from top to bottom in the reverse order as shown in FIG. 1 . Examples are clearly contemplated. Alternatively, the positions of the source elements 42S, 24 may be exchanged with the positions of the drain elements 42D, 26, since the source and drain regions may be symmetrical in field effect transistors. Because.

The channel level insulating layers 32C, the inter-transistor level insulating layers 321 , the bottommost insulating layer 32B, and the topmost insulating layers 32T are collectively referred to as the insulating layers 32 . Each of the insulating layers 32 includes a respective insulating material, such as doped silicate glass, undoped silicate glass (eg, silicon oxide), or organosilicate glass. The material composition of the channel level insulating layers 32C may be the same as or different from the material composition of the inter-transistor insulating layers 321 . In one embodiment, each of the insulating layers 32 has the same dielectric material composition throughout. Alternatively, the channel level insulating layers 32C may have a first dielectric material composition throughout, and the inter-transistor level insulating layers 321 may have a second dielectric material composition different from the first dielectric material composition. The thickness of each channel level insulating layer 32C may range from 5 nm to 50 nm, and the thickness of each of the inter-transistor level insulating layers 321 may range from 5 nm to 50 nm, but smaller and Larger thicknesses may also be employed.

Doped semiconductor source layers 24 and doped semiconductor drain layers 26 include doped polysilicon, or doped semiconductor material, such as doped amorphous silicon, which may be subsequently annealed to form doped polysilicon. do. The conductivity type of doped semiconductor source layers 24 and doped semiconductor drain layers 26 is referred to herein as a first conductivity type, which may be p-type or n-type.

As used herein, “semiconducting material” refers to a material having an electrical conductivity in the range of ^{1.0×10 −5} S/m to 1.0×10 ^{5 S/m.} As used herein, “semiconductor material” refers to a material having an electrical conductivity in the range of ^{1.0×10 −5 S/m to 1.0 S/m in the absence of electrical dopants therein, wherein the electrical dopant} A doped material having an electrical conductivity in the range of 1.0 S/m to 1.0×10 ^{5 S/m can be produced upon suitable doping with} As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band in the band structure, or an n-type dopant adds electrons to the conduction band in the band structure. As used herein, “conductive material” refers to a material having an electrical conductivity greater than ^{1.0×10 5 S/m.} As used herein, “insulator material” or “dielectric material” refers to a material having an electrical conductivity of less than ^{1.0×10 −5 S/m.} As used herein, "heavily doped semiconductor material" refers to a conductive material as formed as a crystalline material or when converted to a crystalline material via an annealing process (e.g., from an initial amorphous state); It refers to a semiconductor material doped with an electrical dopant at a sufficiently high atomic concentration to have an electrical conductivity greater than 1.0×10 ^{5 S/cm.} A “doped semiconductor material” may be a highly doped semiconductor material, or an electrical dopant (i.e., p) at a concentration that provides an electrical conductivity ranging from ^{1.0×10 −5} S/m to 1.0×10 ^{5 S/m.} type dopant and/or n-type dopant). “Intrinsic semiconductor material” refers to a semiconductor material that is not doped with an electrical dopant. Accordingly, the semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconducting material or a doped semiconducting material. The doped semiconductor material may be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material comprising therein at least one metallic element. All measurements of electrical conductivity are made under standard conditions.

The atomic concentration of dopants of the first conductivity type in doped semiconductor source layers 24 and doped semiconductor drain layers 26 may range from 5.0×10 ¹⁹ /cm 3 to 2.0×10 ²¹ /cm 3 , but with smaller and more Large atomic concentrations may also be employed. The thickness of each doped semiconductor source layer 24 may range from 5 nm to 50 nm, and the thickness of each doped semiconductor drain layer 26 may range from 5 nm to 50 nm, although smaller And larger thicknesses may also be employed.

Source sacrificial material layers 42S and drain sacrificial material layers 42D are optional layers that may or may not be present. The source sacrificial material layers 42S and the drain sacrificial material layers 42D may be selectively removed with respect to the materials of the insulating layers 32 , the doped semiconductor source layers 24 , and the doped semiconductor drain layers 26 . includes materials that are For example, if insulating layers 32 include doped silicate glass, undoped silicate glass, or organosilicate glass, source sacrificial material layers 42S and drain sacrificial material layers 42D may be silicon nitride, undoped It may include non-amorphous silicon, or a silicon germanium alloy. The thickness of each source sacrificial material layer 42S may range from 5 nm to 50 nm, and the thickness of each drain sacrificial material layer 42D may range from 5 nm to 50 nm, although smaller and larger Large thicknesses may also be employed.

Multiple instances of the unit layer stack include doped semiconductor source layers 24 and doped semiconductor drain layers 24 interlaced with a second alternating stack of channel level insulating layer 32C and inter-transistor level insulating layer 321 ( 26). When the source sacrificial material layers 42S and drain sacrificial material layers 42D are omitted, each doped semiconductor source layer 24 serves as a source region for a respective two-dimensional array of vertical field effect transistors. constituting the layer, the doped semiconductor drain layer 26 constitutes the drain layer which functions as the drain region for the respective two-dimensional array of vertical field effect transistors. When source sacrificial material layers 42S and drain sacrificial material layers 42D are included, each successive doped semiconductor source layer 24 and subsequently a metal source layer replacing the source sacrificial material layer 42S This combination constitutes a source layer that functions as a source region for a respective two-dimensional array of vertical field effect transistors, a metal drain displacing a doped semiconductor drain layer 26 and subsequently a drain sacrificial material layer 42D. Each successive combination of layers constitutes a drain layer that serves as a drain region for a respective two-dimensional array of vertical field effect transistors.

Insulating layers 32C and 321 are each of doped semiconductor source layer 24 of doped semiconductor source layers 24 and respective doped semiconductor drain layer 26 of doped semiconductor drain layers 26 respectively. It is formed between pairs of vertically neighboring pairs. Channel level insulating layers 32C are formed between each vertically adjacent pair of doped semiconductor source layer 24 and doped semiconductor drain layer 26 .

In one embodiment, each of the source level sacrificial material layers 42S is formed under a respective doped semiconductor source layer of the doped semiconductor source layers 24 , and each of the drain level sacrificial material layers 42D is a doped semiconductor drain. It is formed over the respective doped semiconductor drain layer of layers 26 . The first exemplary structure includes at least one memory array region 100 in which a three-dimensional array of memory elements will be subsequently formed, and multiple instances of unit layer stacks 42S, 24, 32C, 26, 42D, 321 . Stepped surfaces of the can include step regions 200A, 200B to be subsequently formed. The step regions may include a source-side step region 200A and a drain-side step region 200B.

Referring to FIG. 2 , multiple instances of unit layer stack 42S, 24, 32C, 26, 42D, 321 may be patterned to form stepped surfaces within step regions 200A, 200B. For example, a trimmable mask layer (not shown) may be formed over the first exemplary structure, covering adjacent portions of each memory array region 100 and step regions 200A, 200B. can be patterned to allow the edges of the trimmable mask layer to be formed at locations where the outermost vertical steps of the stepped surfaces will be subsequently formed. An anisotropic etch process may be performed to etch through one unit layer stack 42S, 24, 32C, 26, 42D, 321 in regions not covered by the trimmable mask layer. The trimmable mask layer may be trimmed isotropically such that edges of the trimmable mask layer are formed at locations where the second outermost vertical steps of the stepped surfaces will be subsequently formed. An anisotropic etch process may be performed to etch through one unit layer stack 42S, 24, 32C, 26, 42D, 321 in regions not covered by the trimmable mask layer. An isotropic trimming process and anisotropic etching process for the trimmable mask layer may be iteratively performed to form stepped surfaces in each of the stepped regions 200A, 200B.

In one embodiment, the stepped surfaces in a pair of stepped regions 200A, 200B located on each side of the memory array region 100 include one type of surfaces including the stepped regions 200A, 200B; 200B) and other types of surfaces may be vertically offset such that they are physically exposed in the other of the step regions 200A, 200B. For example, the horizontal surfaces of the doped semiconductor source layers 24 may be physically exposed in the source side step region 200A adjacent to one side of the memory array region 100 , and the drain level sacrificial material layers 42D Horizontal surfaces of can be physically exposed in the drain-side step region 200B adjacent to the opposite side of the memory array region 100 . The vertical offset between horizontal steps within each pair of step areas 200A, 200B located on opposite sides of the same memory array area 100 is the unit layer stack 42S, 24, 32C, 26, 42D, 321 . ½ of the thickness, such as the sum of the thickness of the selective source sacrificial material layer 42S, the thickness of the doped semiconductor source layer 24, and the thickness of the channel level insulating layer 32C, or the doped semiconductor drain layer ( 26 , the thickness of the optional drain sacrificial material layer 42D, and the thickness of the inter-transistor level insulating layer 321 . In this case, an etch mask layer (not shown), such as a patterned photoresist layer, may cover the memory array region 100 and one of the stepped regions (eg, 200A), and the unit layer stack Another step area (eg, 200B) may be vertically recessed by a thickness of 1/2 of (42S, 24, 32C, 26, 42D, 321).

Stepped cavities 69 having stepped bottom surfaces may be formed in step areas 200A, 200B. The lateral extent of each type of layer within the multiple instances of the unit layer stack 42S, 24, 32C, 26, 42D, 321 is the number of units in the unit layer stack 42S, 24, 32C, 26, 42D, 321. may decrease with the vertical distance from the substrate 9 when patterning stepped surfaces on instances of . As a result, the doped semiconductor source layers 24 in an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 have different lateral extents that decrease with vertical distance from the substrate 9 . have them Likewise, doped semiconductor drain layers 26 in an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 exhibit different lateral extents that decrease with vertical distance from substrate 9 . have The trimmable mask layer may be removed after forming the top vertical steps.

3A and 3B , a retro-stepped dielectric material portion 65 (ie, an insulating fill material portion) is formed into each stepped cavity by deposition of dielectric material therein. ) (69). For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from over the top surface of the topmost insulating layer 32T, for example by chemical mechanical planarization (CMP). Each remaining portion of the deposited dielectric material filling the stepped cavity constitutes a reverse-stepped dielectric material portion 65 . As used herein, an “inverse-stepped” element refers to an element having stepped surfaces and a horizontal cross-sectional area that monotonically increases as a function of vertical distance from the top surface of the substrate on which the element is present do. When silicon oxide is employed in the reverse-stepped dielectric material portion 65, the silicon oxide in the reverse-stepped dielectric material portion 65 may be doped with dopants such as B, P and/or F, or may not be doped.

A lithographic material stack (not shown) comprising at least a photoresist layer may be formed over the top insulating layer 32T and the reverse-stepped dielectric material portion 65 and lithographically patterned to provide openings therein. can be formed The openings include a first set of openings formed over the memory array region 100 and an optional second set of openings formed over the step regions 200A, 200B. The pattern in the lithographic material stack is formed by at least one anisotropic etch employing the patterned lithographic material stack as an etch mask, the top insulating layer 32T or inverse-stepped dielectric material portion 65, unit layer stacks 42S, 24 , 32C, 26, 42D, 321 , and may be transferred through the bottommost insulating layer 32B. Portions of multiple instances of the unit layer stack 42S, 24, 32C, 26, 42D, 321 located in the memory array region 100 and underlying a first set of openings in the patterned lithographic material stack are etched away. to form memory openings 49 . As used herein, “memory opening” refers to a structure in which memory elements, such as a memory stack structure, are subsequently formed. Memory openings 49 are formed throughout the top insulating layer 32T and multiple instances of the unit layer stacks 42S, 24, 32C, 26, 42D, 321 in the memory array region 100 . Portions of the multiple instances of the unit layer stack 42S, 24, 32C, 26, 42D, 321 and located within the step regions 200A, 200B, below the second set of openings in the patterned lithographic material stack A reverse-stepped dielectric layer 65 overlying is etched to form the optional support openings 19 shown in FIG. 3B .

Memory openings 49 extend through all multiple instances of unit layer stack 42S, 24, 32C, 26, 42D, 321 . The chemistry of the anisotropic etching process employed to etch through the materials of multiple instances of the unit layer stack 42S, 24, 32C, 26, 42D, 321 is the unit layer stack 42S, 24, 32C, 26 , 42D, 321) may alternate to optimize the etching of the respective materials in multiple instances. The anisotropic etch may be, for example, a series of reactive ion etches. The sidewalls of the memory openings 49 may be substantially vertical or may be tapered. The patterned lithographic material stack may subsequently be removed, for example by ashing.

The memory openings 49 may extend from the top surface of the multiple instances of the unit layer stack 42S, 24, 32C, 26, 42D, 321 to at least a horizontal plane including the top surface of the substrate 9 . Each of the memory openings 49 may include a sidewall (or a plurality of sidewalls) extending substantially perpendicular to the top surface of the substrate 9 . A two-dimensional array of memory openings 49 may be formed within memory array region 100 through multiple instances of unit layer stacks 42S, 24, 32C, 26, 42D, 321 . Thus, a two-dimensional array of memory openings 49 may be formed through alternating stacks of doped semiconductor source layers 24 and doped semiconductor drain layers 26 . In one embodiment, the two-dimensional array of memory openings 49 may be formed as clusters of periodic two-dimensional arrays, such as hexagonal arrays.

Referring to FIG. 4 , successive layers of material may be sequentially deposited on each of the memory openings 49 and each of the support openings 19 (if present). The continuous material layers may include a continuous semiconductor channel layer, a continuous memory film, a continuous conductive material layer, and an optional dielectric fill material layer. Excess portions of the successive material layers may be removed from above a horizontal plane including the top surface of the topmost insulating layers 32T and the top surfaces of the reverse-stepped dielectric material portions by a planarization process. The planarization process may employ chemical mechanical planarization (CMP) and/or at least one recess etch process. Each portion of the continuous material layers remaining within the memory opening 49 constitutes a memory opening filling structure 58 . Each portion of the continuous material layers remaining within the support opening 49 constitutes a support pillar 20 (shown in FIG. 6B ).

Each memory aperture filling structure 58 includes a continuous semiconductor channel layer 60L, a memory film 54 , a gate electrode 66 , and an optional dielectric core 62 . Each successive semiconductor channel layer 60L is the remainder of the successive semiconductor channel layer after the planarization process. Each memory film 54 is the remainder of the continuous memory film after the planarization process. Each gate electrode 66 is the remainder of the continuous conductive material layer after the planarization process. Each gate electrode 66 may be a control gate electrode of a NAND memory device. The gate electrode 66 may be electrically connected to an overlying word line to be formed in a subsequent step. Each dielectric core 62 is the remainder of the dielectric fill material layer.

The continuous semiconductor channel layer 60L includes a semiconductor material having a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa. The semiconductor material in the continuous semiconductor channel layer 60L may include silicon, a silicon germanium alloy, or a compound semiconductor material. The atomic concentration of the dopants of the second conductivity type in the continuous semiconductor channel layer 60L may range from 1.0 × 10 ¹⁴ /cm 3 to 3.0 × 10 ¹⁷ /cm 3 , although smaller and larger atomic concentrations may also be employed. . The thickness of the continuous semiconductor channel layer 60L may range from 1 nm to 30 nm, such as 3 nm to 10 nm, although smaller and larger thicknesses may also be employed.

Memory film 54 includes at least one layer of material capable of storing data bits in the form of trapped electrical charges or polarization. In one embodiment, each of the memory films includes, from the outside to the inside, a tunneling dielectric layer 542 in contact with the semiconductor channel layer 60L, a blocking dielectric layer 546 in contact with the gate electrode 66 , and a tunneling dielectric. and a layer stack including a charge storage layer 544 positioned between and in contact with the layer 542 and the blocking dielectric layer 546 . Tunneling dielectric layer 542 may include a tunneling dielectric material such as a silicon oxide layer or an ONO stack (ie, a stack of silicon oxide layers, silicon nitride layers, and silicon oxide layers). Charge storage layer 544 may include charge storage materials such as silicon nitride or charge storage nanoparticles embedded within a dielectric material. The blocking dielectric layer 546 may include a blocking dielectric material such as silicon oxide and/or a dielectric metal oxide, such as aluminum oxide. In another embodiment, each of the memory films 54 includes at least one optional layer of dielectric material (eg, a silicon oxide layer) and a layer of ferroelectric material that may be in contact with a continuous semiconductor channel layer 60L or gate electrode 66 ( not shown). The ferroelectric material layer may include hafnium oxide (HfO ₂ ) or hafnium zirconium oxide (H _fx Z _r1-x O ₂ ), where 0.01 < x < 0.99. The ferroelectric material layer may include suitable dopants such as Al, Zr, Y, Gd, La, Sr, and/or Si to enhance the ferroelectric properties.

Each gate electrode 66 includes a conductive material, such as a metallic material. For example, each gate electrode 66 may have a metal filled layer comprising a metal (eg, W, Co, Mo, Ru, Cu, or alloys thereof) and a conductive metal nitride (eg, TiN, TaN, or WN). ) of a metal nitride liner (eg, a barrier layer).

Each optional dielectric core 62 includes a dielectric filling material such as silicon oxide. In one embodiment, the dielectric cores 62 may include a dielectric material that has a higher etch rate than the topmost insulating layer 32T in the etch process. For example, dielectric cores 62 may include borosilicate glass, organosilicate glass, or phosphosilicate glass, and top insulating layer 32T may include densified undoped silicate glass. In this case, the material of the dielectric cores 62 may be subsequently recessed relative to the material of the topmost insulating layer 32T.

Each portion of the continuous semiconductor channel layer 60L extending from the bottom surface of the doped semiconductor source layer 24 to the top surface of the doped semiconductor drain layer 26 constitutes a semiconductor channel. Each successive semiconductor channel layer 60L includes a vertical stack of semiconductor channels. Each of the semiconductor channels is formed on a respective vertically neighboring pair of cylindrical sidewalls of doped semiconductor source layer 24 and doped semiconductor drain layer 26 . Each of the semiconductor channels is also formed on a cylindrical sidewall of a respective channel level insulating layer of the channel level insulating layer 32C. In a first embodiment, each vertical stack of semiconductor channels includes a respective doped semiconductor source layer 24 and a respective doped semiconductor source layer 24 in an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain regions 26 It is formed as a continuous semiconductor channel layer 60L extending through the doped semiconductor drain layer 26 . Each of the semiconductor channels is connected to a respective vertically neighboring pair of doped semiconductor source layer 24 and doped semiconductor drain layer 26 . Each successive semiconductor channel layer 60L is a respective doped semiconductor source layer 24 and a respective doped semiconductor drain layer in an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 . (26) is extended through.

A memory film 54 is formed on each of the vertical stacks of semiconductor channels, and a gate electrode 66 is formed on each of the memory films 54 . Each of the gate electrodes 66 extends vertically through each of the doped semiconductor source layers 24 and doped semiconductor drain layers 26 of the alternating stack. Each gate electrode 66 has a respective doped semiconductor source layer 24 and a respective doped semiconductor drain layer 26 in an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 . ) is extended through

Each continuous semiconductor channel layer 60L includes a hollow cylindrical portion and a bottom cap portion adjacent a bottom periphery of the cylindrical portion. Each memory film 54 includes a hollow cylindrical portion and a bottom cap portion adjacent the lower periphery of the cylindrical portion. Each gate electrode 66 may include a hollow cylindrical portion and a bottom cap portion adjacent a lower periphery of the cylindrical portion. The gate electrodes 66 may be vertically spaced from the substrate 9 by horizontal portions of the memory films 54 . Each of the gate electrodes 66 may laterally surround a respective dielectric core 62 when the gate electrodes 66 include a hollow cylindrical portion. Alternatively, the dielectric core 62 may be omitted if the gate electrode 66 comprises a filled cylinder. Although the cylinders and cylindrical portions filling the cylindrical memory openings 49 have been described above, the memory opening when the memory openings have a shape other than the cylindrical shape (eg, when the memory openings 49 have a polygonal horizontal cross-sectional shape). Other shapes of filling fields 49 may be formed.

Referring to FIG. 5 , top portions of dielectric cores 62 may be vertically recessed to form hollow regions. A conductive material, such as a metallic material, may be deposited in the cavity regions. Excess portions of conductive material may be removed from above a horizontal plane including the top surfaces of top insulating layer 32T. Each remaining portion of the conductive material constitutes the contact pad structure 68 .

In one embodiment, the contact pad structures 68 are formed of a metal nitride liner (TaN, TiN, or WN) and a conductive fill material, such as a metallic material (eg, W, Ru, Co, or Mo), a doped semiconductor material, and/or a metal silicide material. Each contact pad structure 68 contacts a top end of a respective gate electrode 66 and is laterally spaced from a respective continuous semiconductor channel layer 60L by a respective memory film 54 . Alternatively, if the gate electrodes 66 comprise a filled cylinder, the contact pad structure 68 may be omitted.

6A and 6B , a photoresist layer (not shown) may be applied over the top insulating layer 32T, between the clusters of memory aperture filling structures 58 and the support pillars 20 . It is lithographically patterned to form openings in the regions. Support pillars 20 are not shown in subsequent figures for the sake of simplicity. The pattern in the photoresist layer employs an anisotropic etch to transfer through multiple instances of the unit layer stack 42S, 24, 32C, 26, 42D, 321 and the top insulating layer 32T to leave the backside trenches 79. may form, which extends vertically from the top surface of the topmost insulating layer 32T to at least the top surface of the substrate 9 and laterally through the memory array region 100 and the step regions 200A, 200B. is extended

In one embodiment, the backside trenches 79 may extend laterally along the first horizontal direction hd1 and lateral to each other along the second horizontal direction hd2 perpendicular to the first horizontal direction hd1 . direction may be spaced apart. The memory opening filling structures 58 may be arranged in rows extending along the first horizontal direction hd1 .

Each backside trench 79 may have a uniform width that does not vary along the longitudinal direction (ie, along the first horizontal direction hd1 ). Multiple rows of memory aperture fill structures 58 may be positioned between adjacent pairs of backside trenches 79 . The photoresist layer may be removed, for example, by ashing.

7, insulating layers 32, doped semiconductor source layers 24, doped semiconductor drain layers 26, reverse-stepped dielectric material portions 65, and continuous semiconductor channel layers 60L An etchant that selectively etches the materials of the source sacrificial material layer 42S and the drain sacrificial material layers 42D relative to the materials of the etchant is introduced into the backside trenches 79 employing, for example, an etching process. can be Source level backside recesses 43S and drain level backside recesses 43D are respectively formed in the volumes from which the source sacrificial material layer 42S and drain sacrificial material layers 42D are removed. In one embodiment, the source sacrificial material layers 42S and the drain sacrificial material layers 42D may include silicon nitride, and the insulating layers 32 and materials of the inverse-stepped dielectric material portion 65 are silicon oxide. may include.

The etching process may be a wet etching process employing a wet etching solution, or it may be a gas phase (dry) etching process in which the etchant is introduced into the backside trenches 79 in the vapor phase. . For example, if the source sacrificial material layer 42S and the drain sacrificial material layers 42D include silicon nitride, the etching process may be performed in a wet etch tank in which the exemplary structure is immersed in a wet etch tank containing phosphoric acid. It may be an etch process, which etches silicon nitride selectively to silicon oxide, silicon, and various other materials.

Each backside recess 43S, 43D may be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43S, 43D may be greater than the height of the backside recess 43S, 43D. A plurality of source level backside recesses 43S and drain level backside recesses 43D may be formed in the volumes from which the materials of the source sacrificial material layer 42S and the drain sacrificial material layer 42D are removed. The memory openings from which the memory opening filling structures 58 are formed are herein front side openings or front cavity as opposed to the source level backside recesses 43S and drain level backside recesses 43D are referred to as Each of the plurality of source level backside recesses 43S and drain level backside recesses 43D may extend substantially parallel to the top surface of the substrate 9 . In one embodiment, each backside recess 43S, 43D may have a uniform height throughout.

Referring to FIG. 8 , at least one metallic material may be deposited in the source level backside recesses 43S and the drain level backside recesses 43D through the backside trenches 79 . The at least one metal material includes a metal nitride material (eg, TaN, TiN, or WN) forming a metal liner and source level backside recesses 43S and drain level backside recesses 43D not filled by the metal liner. ) may include a metal filling material (eg, W, Co, Ru, or Mo) that fills the remaining volumes. At least one metallic material fills all volumes of the source level backside recesses 43S and the drain level backside recesses 43D. Portions of at least one metallic material deposited on peripheral portions of backside trenches 79 or over top insulating layer 32T may be removed by an etching process, including an isotropic etching process and/or an anisotropic etching process. can do. The remaining portions of the at least one metal material filling the source level backside recesses 43S constitute the metal source layers (ie, electrically conductive source lines) 22 . The remaining portions of the at least one metal material filling the drain level backside recesses 43D constitute the metal drain layers (ie, electrically conductive bit lines) 28 . Each adjacent combination of doped semiconductor source layer 24 and metal source layer 22 constitutes source layers 22, 24 that serve as source regions and source lines for respective two-dimensional arrays of vertical field effect transistors. do. Each adjacent combination of doped semiconductor drain layer 26 and metal drain layer 28 constitutes drain layers 26 and 28 that serve as drain regions and bit lines for respective two-dimensional arrays of vertical field effect transistors. do.

As discussed above, the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are optional elements that may be omitted. When the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are present, the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are the metal source layers 22 and the metal drain layers, respectively. (28) (ie, source lines and bit lines). In this case, each of the source layers 22, 24 comprises a vertical stack of a doped semiconductor source layer 24 and a metal source layer 22, and each of the drain layers 26, 28 is a doped semiconductor drain layer ( 26 ) and a vertical stack of metal drain layers 28 . When the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are omitted, each of the source layers consists of a doped semiconductor source layer 24 , and each drain layer consists of a doped semiconductor drain layer 26 . ) is made of In this case, the doped semiconductor source layer 24 functions as both the source region and the source line, and the doped semiconductor drain layer 26 functions as both the drain regions and the bit line. It is understood that the process steps employed to replace the source sacrificial material layer 42S and the drain level sacrificial material layers 42D with the metal source layers 22 and the metal drain layers 28, respectively, are omitted in all such embodiments. do.

Insulating layers 32C, 321 are positioned between each vertically neighboring pair of source layers 22, 24 and drain layers 26, 28. In one embodiment, the insulating layers 32C, 321 may have the same dielectric material composition throughout, which may be a composition of doped silicate glass, undoped silicate glass, or organosilicate glass. In another embodiment, the channel level insulating layers 32C may have a different composition from the inter-transistor level insulating layers 321 . In one embodiment, each semiconductor channel comprises a cylindrical sidewall of a respective channel level insulating layer 32C positioned between a respective vertically neighboring pair of source layers 22, 24 and drain layers 26 and 28; contact

A dielectric material, such as silicon oxide, may be deposited in each backside trench to form backside trench fill structures 76 . Portions of dielectric material deposited over top insulating layer 32T may constitute contact level dielectric layer 80 . Each backside trench fill structure 76 includes a metal source layer 22, a doped semiconductor source layer 24, a channel level insulating layer 32C, a doped semiconductor drain layer 26, a metal drain layer 28, and an inter-transistor level insulating layer 321 , which may extend vertically through multiple instances of the unit layer stack.

9A and 9B , contact via structures 88 , 86 may be formed through the contact level dielectric layer 80 and optionally through the reverse-stepped dielectric material portion 65 . Contact via structures 88 , 86 include word line contact via structures 88 , each in contact with a respective contact pad structure of contact pad structures 68 and at a respective gate electrode 66 . electrically connected. In addition, contact via structures 88 and 86 are layered contact via structures in contact with respective layers of source layers 22 and 24 and drain layers 26 and 28 in respective stepped regions 200A, 200B. (86) (eg, 86S, 86D). Specifically, each of the layer contact via structures 86S, 86D is a respective layer of the source layers 22, 24 or the drain layers 26, 28 exposed to stepped surfaces in the stepped regions 200A, 200B. may be in contact with the horizontal surface of Word lines 98 are then formed over contact level dielectric layer 80 (and over gate electrodes 66 , source layers 22 , 24 , and drain layers 26 , 28 ) and contact via structures Electrical contact with gate electrodes 66 through 88 and optional contact pad structures 68 . The word lines 98 are arranged as a two-dimensional array extending along a horizontal direction perpendicular to the longitudinal direction of the backside trenches 79 , as shown in FIG. 9B . In FIG. 9B , the locations of the memory aperture fill structures 58 are schematically shown as clear circles, while the locations of the backside trenches 79 are schematically shown as clear lines.

Each vertical stack of semiconductor channels extends through a respective source layer 22 , 24 and a respective drain layer 26 , 28 in an alternating stack of source layers 22 , 24 and drain layers 26 , 28 . formed as portions of the continuous semiconductor channel layer 60L, which remains after formation of the contact via structures 86 and 88. Layer contact via structures 86 include source layer contact via structures 86S and drain layer contact via structures 86D. Each source layer contact via structure 86S is in contact with a respective source layer of the source layers 22 , 24 . Each drain layer contact via structure 86D is in contact with a respective drain layer of the drain layers 26 and 28 .

In one embodiment, source layers 22 , 24 in an alternating stack of source layers 22 , 24 and drain layers 26 , 28 have different lateral extents that decrease with vertical distance from substrate 9 . and drain layers 26 , 28 in an alternating stack of source layers 22 , 24 and drain layers 26 , 28 have different lateral extents that decrease with vertical distance from the substrate 9 . A first counter-stepped dielectric material portion 65 contacts the horizontal surfaces of the source layers 22 , 24 in the alternating stack and laterally surrounds the source layer contact via structures 86S. A second counter-stepped dielectric material portion 65 contacts the horizontal surfaces of drain layers 26 , 28 in the alternating stack and laterally surrounds drain layer contact via structures 86D.

Referring to FIG. 10 , a second exemplary structure according to a second embodiment of the present invention can be derived from the first exemplary structure of FIG. 1 by replacing the inter-transistor level insulating layers 321 with sacrificial material layers, These are referred to herein as inter-transistor level sacrificial material layers 142 . Thus, each instance of the unit layer stack within the plurality of instances of the unit layer stack is a source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel level insulating layer 32C, a doped semiconductor drain layer ( 26 ), a drain sacrificial material layer 42D, and an inter-transistor level sacrificial material layer 142 .

Source sacrificial material layers 42S and drain sacrificial material layers 42D are selective with respect to the material of channel level insulating layers 32C, top insulating layer 32, and top insulating layer 32T, and inter-transistor level sacrificial material. and a sacrificial material that can be selectively removed with respect to the material of the material layers 142 . For example, channel level insulating layer 32C, bottom insulating layer 32, and top insulating layer 32T may include undoped silicate glass, doped silicate glass, or organosilicate glass; Inter-transistor level sacrificial material layers 142 may include a material such as a dielectric metal oxide (eg, aluminum oxide), a silicon germanium alloy having an atomic concentration of germanium greater than 20%, a polymer material, or source sacrificial material layers 42S and drain may include a metal material different from the metal materials to be employed for the metal source layers and metal drain layers that subsequently replace the sacrificial material layers 42D; The source sacrificial material layers 42S and the drain sacrificial material layers 42D may include silicon nitride. Each inter-transistor level sacrificial material layer 142 may have a thickness in the range of 5 nm to 50 nm, although smaller and larger thicknesses may also be employed. In an alternative configuration, one or both of the source sacrificial material layers 42S and/or the drain sacrificial material layer 42D may be omitted.

Multiple instances of the unit layer stack include an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 . Channel level insulating layers 32C may be provided between the underlying doped semiconductor source layer 24 and the overlying doped semiconductor drain layer 26 of each vertically neighboring pair. Intertransistor level sacrificial material layers 142 are formed between an overlying doped semiconductor source layer 24 and an underlying doped semiconductor drain layer 26 of vertically adjacent pairs.

Referring to FIG. 11 , the process steps of FIG. 2 may be performed to form stepped cavities 69 in step regions 200A, 200B. Stepped surfaces are formed in the step areas 200A, 200B. The steps of the anisotropic etching processes to form the stepped surfaces may be modified to provide an etching chemistry that effectively etches the inter-transistor level sacrificial material layers 142 .

12A and 12B , the process steps of FIGS. 3A and 3B may be performed to form memory openings 49 through each layer in multiple instances of a unit layer stack. As discussed above, the unit layer stack of the second exemplary structure comprises a source sacrificial material layer 42S, a doped semiconductor source layer 24 , a channel level insulating layer 32C, a doped semiconductor drain layer 26 , a drain sacrificial material layer 42D, and an inter-transistor level sacrificial material layer 142 . The steps of the anisotropic etching processes to form the memory openings 49 may be modified to provide an etching chemistry that effectively etches the inter-transistor level sacrificial material layers 142 .

Referring to FIG. 13 , the process steps of FIG. 4 may be performed to form memory aperture filling structures 58 . Each of the memory aperture filling structures 58 of the second exemplary structure may have the same set of elements as the memory aperture filling structures 58 of FIG. 4 .

Referring to FIG. 14 , the process steps of FIG. 5 may be performed to form contact pad structures 68 . Each memory aperture filling structure 58 may include a respective contact pad structure 68 in contact with a top end of a respective gate electrode of the gate electrodes 66 .

15A and 15B , the process steps of FIGS. 6A and 6B may be performed to form backside trenches 79 through multiple instances of the unit layer stack. The steps of the anisotropic etch processes to form the backside trenches 79 may be modified to provide an etch chemistry that effectively etches the inter-transistor level sacrificial material layers 142 .

Referring to FIG. 16 , insulating layers 32 , inter-transistor level sacrificial material layers 142 , doped semiconductor source layers 24 , doped semiconductor drain layers 26 , reverse-stepped dielectric material portions 65 , ), and an etchant that selectively etches the materials of the source sacrificial material layer 42S and the drain sacrificial material layers 42D with respect to the materials of the successive semiconductor channel layers 60L, employing an etching process, for example can be introduced into trenches 79 . Source level backside recesses 43S and drain level backside recesses 43D are respectively formed in the volumes from which the source sacrificial material layer 42S and drain sacrificial material layers 42D are removed. In one embodiment, the source sacrificial material layer 42S and the drain sacrificial material layers 42D may include silicon nitride; Inter-transistor level sacrificial material layers 142 may include a material such as a dielectric metal oxide (eg, aluminum oxide), a silicon germanium alloy having an atomic concentration of germanium greater than 20%, a polymer material, or source sacrificial material layers 42S and drain may include a metal material different from the metal materials to be employed for the metal source layers and metal drain layers that subsequently replace the sacrificial material layers 42D; The materials of the channel level insulating layers 32 and the inverse-stepped dielectric material portion 65 may include silicon oxide.

The etching process may be a wet etching process employing a wet etching solution, or it may be a gas phase (dry) etching process in which the etchant is introduced into the backside trenches 79 in the vapor phase. For example, if source sacrificial material layers 42S and drain sacrificial material layers 42D include silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etch tank containing phosphoric acid , which etches silicon nitride selective to silicon oxide, silicon, and various other materials.

Referring to FIG. 17 , at least one metal material may be deposited in the source level backside recesses 43S and the drain level backside recesses 43D. The at least one metal material includes a metal nitride material (eg, TaN, TiN, or WN) forming a metal liner and source level backside recesses 43S and drain level backside recesses 43D not filled by the metal liner. ) may include a metal filling material (eg, W, Co, Ru, or Mo) that fills the remaining volumes. At least one metallic material fills all volumes of the source level backside recesses 43S and the drain level backside recesses 43D. Portions of at least one metallic material deposited on peripheral portions of backside trenches 79 or over top insulating layer 32T may be removed by an etching process, including an isotropic etching process and/or an anisotropic etching process. can do. The remaining portions of the at least one metal material filling the source level backside recesses 43S constitute the metal source layers 22 . The remaining portions of the at least one metal material filling the drain level backside recesses 43D constitute the metal drain layers 28 . Each adjacent combination of doped semiconductor source layer 24 and metal source layer 22 forms source layers 22, 24 that serve as source regions and source lines for a respective two-dimensional array of vertical field effect transistors. make up Each adjacent combination of doped semiconductor drain layer 26 and metal drain layer 28 forms drain layers 26 and 28 that serve as bit lines and drain regions for a respective two-dimensional array of vertical field effect transistors. make up

Source sacrificial material layer 42S and drain level sacrificial material layers 42D are optional elements that may be omitted. When the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are present, the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are the metal source layers 22 and metal drain layers respectively is replaced by (28). In this case, each of the source layers 22, 24 comprises a vertical stack of a doped semiconductor source layer 24 and a metal source layer 22, and each of the drain layers 26, 28 is a doped semiconductor drain layer ( 26 ) and a vertical stack of metal drain layers 28 . When the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are omitted, each of the source layers consists of a doped semiconductor source layer 24 or a doped semiconductor drain layer 26 .

Referring to FIG. 18 , the inter-transistor backside recesses 143 include doped semiconductor source layers 24 , doped semiconductor drain layers 26 , channel level insulating layers 32C, metal source layers 22 , and may be formed by removing the inter-transistor level sacrificial material layers 142 selectively with respect to the materials of the metal drain layers 28 . In one embodiment, the inter-transistor level sacrificial material layers 142 are made of a material such as a dielectric metal oxide (eg, aluminum oxide), a silicon germanium alloy having an atomic concentration of germanium greater than 20%, a polymer material, or metal source layers ( 22) and a metal material different from the metal materials of the metal drain layers 28, and the channel level insulating layers 32C may include silicon oxide.

Referring to FIG. 19 , an isotropic etching process may be performed to remove physically exposed portions of the continuous semiconductor channel layers 60L exposed in the inter-transistor backside recesses 143 . Removal of the physically exposed portions of the continuous semiconductor channel layers 60L may be selective for the materials of the doped semiconductor source layers 24 and doped semiconductor drain layers 26 . For example, continuous semiconductor channel layer 60L may include amorphous silicon comprising dopants of a second conductivity type (eg, p-type) at an atomic concentration ranging ^{from 1.0 × 10 14} /cm 3 to 3.0 × 10 ^{17 /cm 3} and doped semiconductor source layers 24 and doped semiconductor drain layers 26 are of a first conductivity type (eg, n-type) at an atomic concentration ranging ^{from 5.0 × 10 19} /cm 3 to 2.0 × 10 ^{21 /cm 3} It may include polysilicon or amorphous silicon with dopants. In this case, an isotropic etching process that etches physically exposed portions of the continuous semiconductor channel layer 60L is high temperature trimethyl-2 hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH). ), a wet etching process using Alternatively, physically exposed surface portions of doped semiconductor source layers 24 and doped semiconductor drain layers 26 collaterally during removal of physically exposed portions of successive semiconductor channel layers 60L can be etched.

Portions of each successive semiconductor channel layer 60L that are physically exposed to the inter-transistor level backside recesses 143 may be removed by an isotropic etch process. Accordingly, the isotropic etch process may split each successive semiconductor channel layer 60L into a set of individual semiconductor channels 60 spaced apart vertically from each other. In other words, the remaining portions of each successive semiconductor channel layer 60L include a set of individual semiconductor channels 60 that are not in direct contact with each other. Each of the individual semiconductor channels 60 is in contact with the cylindrical vertical surface of the respective source layer of the source layers 22 , 24 and the cylindrical vertical surface of the respective drain layer of the drain layers 26 , 28 .

Referring to FIG. 20 , a dielectric material may be deposited in the inter-transistor backside recesses 143 by a conformal deposition process. Portions of dielectric material filling the inter-transistor level backside recesses 143 constitute replacement insulating layers, referred to herein as inter-transistor level insulating layers 176 . Portions of dielectric material filling backside trenches 79 constitute backside trench filling structures 76 . Portions of dielectric filling material overlying the topmost insulating layer 32T constitute the contact level dielectric layer 80 . The dielectric material of the inter-transistor level insulating layers 176 , the backside trench fill structure 76 , and the contact level dielectric layer 80 may have a uniform material composition throughout, doped silicate glass, undoped silicate glass. , or organosilicate glass.

Insulating layers 32C, 176 are provided between each vertically neighboring pair of source layers 22,24 and drain layers 26,28. In one embodiment, the insulating layers 32C and 176 may have the same dielectric material composition throughout, which may be a composition of doped silicate glass, undoped silicate glass, or organosilicate glass. In another embodiment, the channel level insulating layers 32C may have a different composition than the inter-transistor level insulating layers 176 . For example, the channel level insulating layers 32C in contact with the sidewall of a respective semiconductor channel of the semiconductor channels 60 may have a first dielectric material composition and not in contact with the sidewalls of the semiconductor channels 60 . The inter-transistor level insulating layers 176 may have a second dielectric material composition different from the first dielectric material composition. In one embodiment, each semiconductor channel 60 comprises a respective channel level insulating layer 32C positioned between a respective vertically neighboring pair of source layers 22 and 24 and drain layers 26 and 28 . in contact with the cylindrical sidewall.

Referring to FIG. 21 , the process steps of FIG. 9A may be performed to form contact via structures 88 , 86 through contact level dielectric layer 80 and optionally through reverse-stepped dielectric material portion 65 . can Contact via structures 88 , 86 include word line contact via structures 88 , each in contact with a respective contact pad structure of contact pad structures 68 and at a respective gate electrode 66 . electrically connected. In addition, contact via structures 88 and 86 are layered contact via structures in contact with respective layers of source layers 22 and 24 and drain layers 26 and 28 in respective stepped regions 200A, 200B. (86) (eg, 86S, 86D). Specifically, each of the layer contact via structures 86S, 86D is a respective layer of the source layers 22, 24 or the drain layers 26, 28 exposed to stepped surfaces in the stepped regions 200A, 200B. may be in contact with the horizontal surface of Word lines 98 are then formed over contact level dielectric layer 80 (and over gate electrodes 66, source layers 22, 24, and drain layers 26, 28), and a contact via structure ( 88 and optional contact pad structures 68 , in electrical contact with the gate electrodes 66 .

With reference to all drawings of the first exemplary structure and the second exemplary structure of the first and second embodiments, a three-dimensional memory device is provided, comprising source layers 24 , optionally located over a substrate 9 , 22) and an alternating stack of drain layers 26, optionally 28; gate electrodes 66 extending vertically through each of the source layers 24 (optionally 22) and drain layers 26 (optionally 28) of the alternating stack; memory films 54 laterally surrounding a respective gate electrode of the gate electrodes 66, respectively; and a respective vertically neighboring pair of sidewalls of the source layer 24 (optionally 22) of the source layers 24 (optionally 22) and the drain layer 26 (optionally 28) of the drain layers 26 (optionally 28). and semiconductor channels (or portions of layer 60L) contacting the semiconductor channels and laterally surrounding a respective memory film of memory films 54, respectively.

In one embodiment, word lines 98 are positioned over gate electrodes 66 and over an alternating stack of source and drain layers, where the word lines are electrically connected to the gate electrodes. An array of memory openings 49 , such as cylindrical memory openings, may extend vertically through an alternating stack, each of gate electrodes 66 positioned within a respective memory opening of memory openings 49 . Each of the semiconductor channels may have a hollow cylindrical shape.

Each gate electrode 66 may extend through an alternating stack of at least four source layers 24 , optionally 22 and at least four drain layers 26 , optionally 28 positioned over the substrate 9 . .

Insulating layers (32C, 321 or 32C, 176) may be positioned between each vertically neighboring pair of first source layer 24 (optionally 22) and drain layer 26 (optionally 28). have. In one embodiment, the insulating layers (32C, 321 or 32C, 176) have the same dielectric material composition throughout. In another embodiment, the insulating layers (32C, 321 or 32C, 176) contact a respective semiconductor channel of the semiconductor channels 60 or portions of the layer 60L and have a first dielectric material composition. level insulating layers 32C; and inter-transistor level insulating layers 176 having a second dielectric material composition different from the first dielectric material composition without contacting any of the semiconductor channels 60 or portions of layer 60L.

In one embodiment, the semiconductor channel is a respective portion of a continuous semiconductor channel layer 60L extending through each source layer 24 (optionally 22) and each drain layer 26 (optionally 28) in an alternating stack. includes

In another embodiment, each of the semiconductor channels includes one channel 60 of a set of individual semiconductor channels 60 spaced apart vertically from each other. In one embodiment, each of the individual semiconductor channels 60 has an annular top surface in contact with the bottom surface of a respective overlying inter-transistor insulating layer 176, and a respective underlying inter-transistor insulating layer 176; and an annular bottom surface in contact.

In one embodiment, each of the semiconductor channels (portions of 60 or 60L) is each positioned between the source layer 24 (optionally 22) and the drain layer 26 (optionally 28) of a respective vertically neighboring pair. in contact with the cylindrical sidewall of the channel level insulating layer 32C.

In one embodiment, each of the source layers 24 , 22 comprises a vertical stack of a doped semiconductor source layer 24 and a metal source layer 22 ; Each of the drain layers 26 , 28 includes a vertical stack of a doped semiconductor drain layer 26 and a metal drain layer 28 .

In one embodiment, each of the memory films 54 includes a tunneling dielectric layer 542 ; a charge storage layer 544 in contact with the tunneling dielectric layer 542 ; a nested layer stack including a blocking dielectric layer 546 in contact with a charge storage layer 544 . In another embodiment, each of the memory films 54 includes and/or consists of a layer of ferroelectric material.

In one embodiment, the three-dimensional memory device includes source layer contact via structures 86S in contact with a respective source layer of source layers 24, optionally 22; and drain layer contact via structures 86D in contact with a respective drain layer of drain layers 26 , optionally 28 .

In one embodiment, the source layers 24 , optionally 22 in the alternating stack, have different lateral extents that decrease with vertical distance from the substrate 9 ; The drain layers 26 , optionally 28 in the alternating stack, have different lateral extents that decrease with vertical distance from the substrate 9 ; a first reverse-stepped dielectric material portion 65 contacts the horizontal surfaces of the source layers 24 , optionally 22 in the alternating stack, and laterally surrounds the source layer contact via structures 86S; Then, the second inverse-stepped dielectric material portion 65 contacts the horizontal surfaces of the drain layers 26 , optionally 28 in the alternating stack, and laterally through the drain layer contact via structures 86D. surround

In one embodiment, the gate electrodes 66 are vertically spaced from the substrate 9 by horizontal portions of the memory films 54 ; each of the gate electrodes 66 laterally surrounds a respective dielectric core 62; Then, the contact pad structures 68 contact the top end of the respective gate electrode of the gate electrodes 66 .

Referring to FIG. 22 , a third exemplary structure in accordance with a third embodiment of the present invention comprises inter-transistor level insulating layers 32C and channel level insulating layers 132 having a different material composition from the inter-transistor level insulating layers 321 ) can be derived from the first exemplary structure of FIG. 1 by substituting Thus, each instance of the unit layer stack within the plurality of instances of the unit layer stack comprises a source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel level insulating layer 132, a doped semiconductor drain layer ( 26), a drain sacrificial material layer 42D, and an inter-transistor level insulating layer 321 . In an alternative configuration, one or both of the source sacrificial material layers 42S and/or the drain sacrificial material layer 42D may be omitted.

The channel level insulating layers 132 include a first insulating material, and the inter-transistor level insulating layers 321 include a second insulating material that can provide a smaller etch rate in an isotropic etch process. For example, the channel level insulating layers 132 may include borosilicate glass or organosilicate glass, and the inter-transistor level insulating layers 321 may include undoped silicate glass. In this case, the etch rate of the material of the channel level insulating layers 132 in 100:1 diluted hydrofluoric acid is the etch rate of the material of the intertransistor level insulating layers 321 in 100:1 diluted hydrofluoric acid. It may be at least 10 times, for example, 100 times or more. Each of the channel level insulating layers 132 may have a thickness in the range of 5 nm to 50 nm, although smaller and larger thicknesses may also be employed. Alternatively, the channel level insulating layers 132 may comprise aluminum oxide, and the inter-transistor level insulating layers 321 may comprise undoped silicate glass (i.e., silicon oxide) when aluminum oxide selective etching is used. can

Multiple instances of the unit layer stack include an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 . Channel level insulating layers 132 are formed at the levels of semiconductor channels to be subsequently formed. For example, channel level insulating layers 132 may be formed between an underlying doped semiconductor source layer 24 and an overlying doped semiconductor drain layer 26 of each vertically neighboring pair. Inter-transistor level insulating layers 321 may be provided at the levels of inter-transistor gaps to be subsequently formed. For example, inter-transistor level insulating layers 321 may be formed between an overlying doped semiconductor source layer 24 and an underlying doped semiconductor drain layer 26 of vertically adjacent pairs. Accordingly, insulating layers 131 , 321 are formed between each vertically neighboring pair of doped semiconductor source layer 24 and doped semiconductor drain layer 26 .

Referring to FIG. 23 , the process steps of FIG. 2 may be performed to form stepped cavities 69 in step regions 200A, 200B. Stepped surfaces are formed in the step areas 200A, 200B. The steps of the anisotropic etch processes to form the stepped surfaces can be modified to provide an etch chemistry that effectively etches the channel level insulating layers 132 .

24A and 24B , the process steps of FIGS. 3A and 3B may be performed to form memory openings 49 through each layer in multiple instances of a unit layer stack. As discussed above, the unit layer stack of the second exemplary structure includes a source sacrificial material layer 42S, a doped semiconductor source layer 24 , a channel level insulating layer 132 , a doped semiconductor drain layer 26 , a drain sacrificial material layer 42D, and an inter-transistor level insulating layer 321 . The steps of the anisotropic etch processes to form the memory openings 49 may be modified to provide an etch chemistry that effectively etches the channel level insulating layers 132 .

25 , the lateral annular cavities 349 include inter-transistor level insulating layers 321, doped semiconductor source layers 24, doped semiconductor drain layers 26, source sacrificial material layers 42S, and laterally recessing the channel level insulating layers 132 with respect to the drain sacrificial material layers 42D. As discussed above, the first insulating material of the channel level insulating layers 132 provides a greater etch rate than the second insulating material of the inter-transistor level insulating layers 321 in an isotropic etching process. In one embodiment, the first insulating material of the channel level insulating layers 132 may include borosilicate glass or organosilicate glass, and the second insulating material of the inter-transistor level insulating layers 321 is undoped silicate glass. may include.

In this case, the etch rate of the first insulating material of the channel level insulating layers 132 in 100:1 dilute hydrofluoric acid is the same as that of the intertransistor level insulating layers 321 in 100:1 dilute hydrofluoric acid. 2 It may be at least 10 times the etch rate of the insulating material, such as 100 times or more. The isotropic etching process may be a wet etching process employing hydrofluoric acid diluted 100:1. The lateral recess distance of each of the annular cavities 349 may range from 5 nm to 100 nm, such as 10 nm to 50 nm, although smaller and larger distances may also be employed.

Referring to FIG. 26 , semiconductor material may be deposited within the annular cavities 349 by a conformal deposition process, such as a chemical vapor deposition process. The semiconductor material deposited in the annular cavities 349 may have the same material composition as the continuous semiconductor channel layers 60L used in the first exemplary structure. Portions of conformally deposited semiconductor material may be removed from outside the annular cavities 349 by performing an anisotropic etch process. The remaining portions of conformally deposited semiconductor material within the annular cavities 349 constitute vertical stacks of semiconductor channels 360 . Each vertical stack of semiconductor channels 360 is formed as a set of individual semiconductor channels located within the annular cavities 349 and spaced apart vertically from each other, ie not in direct contact with each other. Each semiconductor channel 360 may have an annular shape (eg, a hollow disk shape). For example, each semiconductor channel 360 may have an inner cylindrical sidewall, an outer cylindrical sidewall, a top annular surface, and a bottom annular surface.

Each of the individual semiconductor channels 360 contacts a cylindrical sidewall of a respective channel level insulating layer of the channel level insulating layers 132 . Insulating layers 132 , 321 in multiple instances of the unit layer stack are channel level insulating layers 132 in contact with a sidewall of a respective semiconductor channel of semiconductor channels 360 , and one of semiconductor channels 360 . Inter-transistor level insulating layers 321 that are not in contact with any semiconductor channel. The sidewalls of the channel level insulating layers 132 are doped semiconductor source layers 24 and doped semiconductor drain layers 26 with respect to the sidewalls of the inter-transistor level insulating layers 321 and around each memory opening 49 . is laterally recessed outward relative to the sidewalls of the Each of the channel level insulating layers 132 will be in direct contact with the horizontal surfaces of the respective doped semiconductor source layer of the doped semiconductor source layers 24 and the respective doped semiconductor drain layer of the doped semiconductor drain layers 26 . can

Each of the semiconductor channels 360 is on a respective vertically neighboring pair of horizontal planes of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26 prior to formation of the memory films and gate electrodes. is formed A vertical stack of semiconductor channels 360 is formed in each of the memory openings 49 . Each of the semiconductor channels 360 is connected to a respective vertically neighboring pair of a doped semiconductor source layer 24 and a doped semiconductor drain layer 26 .

In one embodiment, the entire outer sidewall of each semiconductor channel 360 is at a respective channel level positioned between a respective vertically neighboring pair of doped semiconductor source layer 24 and doped semiconductor drain layer 26 . It contacts the cylindrical sidewall of the insulating layer 132 . In one embodiment, the outer sidewall comprises an upper perimeter in contact with the horizontal surface of one of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26 in a respective vertically neighboring pair, each a lower perimeter in contact with the horizontal surface of the other layers of doped semiconductor source layer 24 and doped semiconductor drain layer 26 in a vertically neighboring pair of

Referring to FIG. 27 , successive layers of material may be sequentially deposited into each of the memory openings 49 . The continuous material layers may include a continuous memory film, a continuous conductive material layer, and an optional dielectric fill material layer. Excess portions of the successive material layers may be removed from above a horizontal plane including the top surface of the topmost insulating layers 32T and the top surfaces of the reverse-stepped dielectric material portions by a planarization process. The planarization process may employ chemical mechanical planarization and/or at least one recess etch process. Each portion of the continuous material layers remaining within the memory opening 49 constitutes a memory opening filling structure 58 .

Each memory aperture filling structure 58 includes a memory film 54 , a gate electrode 66 , and an optional dielectric core 62 . Each memory film 54 is the remainder of the continuous memory film after the planarization process. Each gate electrode 66 is the remainder of the continuous conductive material layer after the planarization process. Each dielectric core 62 is the remainder of the dielectric fill material layer. Each vertical stack of semiconductor channels 360 laterally surrounds a respective memory film 54 and a respective gate electrode 66 .

Memory film 54 includes at least one material layer capable of storing data bits in the form of trapped electrical charges, polarization, or magnetic moments. In one embodiment, each of the memory films comprises, from the outside to the inside, a tunneling dielectric layer 542 , a charge storage layer 544 in contact with the tunneling dielectric layer 542 , and a blocking contact with the charge storage layer 544 . dielectric layer 546 . Tunneling dielectric layer 542 may include a tunneling dielectric material such as silicon oxide or an ONO stack (ie, a stack of silicon oxide layers, silicon nitride layers, and silicon oxide layers). Charge storage layer 544 may include a charge storage material such as silicon nitride. Blocking dielectric layer 546 may include a blocking dielectric material such as silicon oxide and/or dielectric metal oxide. In another embodiment, each of the memory films 54 includes at least one optional layer of dielectric material (eg, a silicon oxide layer) and a layer of ferroelectric material (as shown) that may be in contact with the semiconductor channels 360 or the gate electrode 66 . not included).

Each gate electrode 66 includes a conductive material, such as a metallic material. For example, each gate electrode 66 may have a metal layer comprising a metal (eg, W, Co, Mo, Ru, Cu, or alloys thereof) and a conductive metal nitride (eg, TiN, TaN, or WN). and a layer stack of metal nitride liners comprising:

Each dielectric core 62 includes a dielectric filling material such as silicon oxide. In one embodiment, the dielectric cores 62 may include a dielectric material that has a higher etch rate than the topmost insulating layer 32T in the etch process. For example, dielectric cores 62 may include borosilicate glass, organosilicate glass, or phosphosilicate glass, and top insulating layer 32T may include densified undoped silicate glass. In this case, the material of the dielectric cores 62 may be subsequently recessed relative to the material of the topmost insulating layer 32T.

A memory film 54 is formed on each of the vertical stacks of semiconductor channels 360 , and a gate electrode 66 is formed on each of the memory films 54 . Each of the memory films 54 passes through each of doped semiconductor source layers 24 and doped semiconductor drain layers 26 of an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 . is extended Each of the gate electrodes 66 extends vertically through each of the doped semiconductor source layers 24 and doped semiconductor drain layers 26 of the alternating stack. Each gate electrode 66 has a respective doped semiconductor source layer 24 and a respective doped semiconductor drain layer 26 in an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 . ) is extended through

Each memory film 54 includes a cylindrical portion and a bottom cap portion adjacent the lower periphery of the cylindrical portion. Each gate electrode 66 may include a cylindrical portion and a bottom cap portion adjacent a lower periphery of the cylindrical portion. The gate electrodes 66 may be vertically spaced from the substrate 9 by horizontal portions of the memory films 54 . Each of the gate electrodes 66 may laterally surround a respective dielectric core 62 .

Referring to FIG. 28 , the process steps of FIG. 5 may be performed to form contact pad structures 68 . Each memory aperture filling structure 58 may include a respective contact pad structure 68 in contact with a top end of a respective gate electrode of the gate electrodes 66 .

29A and 29B , the process steps of FIGS. 6A and 6B may be performed to form backside trenches 79 through multiple instances of the unit layer stack. The steps of the anisotropic etch processes to form the backside trenches 79 may be modified to provide an etch chemistry that effectively etches the channel level insulating layers 132 .

Referring to FIG. 30 , insulating layers 132 , 321 , doped semiconductor source layers 24 , doped semiconductor drain layers 26 , reverse-stepped dielectric material portions 65 , and semiconductor channels 360 . An etchant that selectively etches the materials of the source sacrificial material layer 42S and the drain sacrificial material layers 42D with respect to the materials of . have. Source level backside recesses 43S and drain level backside recesses 43D are respectively formed in the volumes from which the source sacrificial material layer 42S and drain sacrificial material layers 42D are removed. In one embodiment, the source sacrificial material layer 42S and the drain sacrificial material layers 42D may include silicon nitride, and materials of the channel level insulating layers 132 , the inter-transistor level insulating layers 321 , and vice versa. -Stepped dielectric material portion 65 may include silicate glass materials such as undoped silicate glass, doped silicate glass, and/or organosilicate glass.

The etching process may be a wet etching process employing a wet etching solution, or it may be a gas phase (dry) etching process in which the etchant is introduced into the backside trenches 79 in the vapor phase. For example, if the source sacrificial material layers 42S and the drain sacrificial material layers 42D include silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etch tank containing phosphoric acid. , which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the present technology.

Referring to FIG. 31 , at least one metal material may be deposited in the source level backside recesses 43S and the drain level backside recesses 43D. The at least one metal material includes a metal nitride material (eg, TaN, TiN, or WN) forming a metal liner and source level backside recesses 43S and drain level backside recesses 43D not filled by the metal liner. ) may include a metal filling material (eg, W, Co, Ru, or Mo) that fills the remaining volumes. At least one metallic material fills all volumes of the source level backside recesses 43S and the drain level backside recesses 43D. Portions of at least one metallic material deposited on peripheral portions of backside trenches 79 or over top insulating layer 32T may be removed by an etching process, including an isotropic etching process and/or an anisotropic etching process. can do. The remaining portions of the at least one metal material filling the source level backside recesses 43S constitute the metal source layers 22 . The remaining portions of the at least one metal material filling the drain level backside recesses 43D constitute the metal drain layers 28 . Each adjacent combination of doped semiconductor source layer 24 and metal source layer 22 forms source layers 22, 24 that serve as source regions and source lines for a respective two-dimensional array of vertical field effect transistors. make up Each adjacent combination of doped semiconductor drain layer 26 and metal drain layer 28 forms drain layers 26 and 28 that serve as bit lines and drain regions for a respective two-dimensional array of vertical field effect transistors. make up

Source sacrificial material layer 42S and drain level sacrificial material layers 42D are optional elements that may be omitted. When the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are present, the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are the metal source layers 22 and metal drain layers respectively is replaced by (28). In this case, each of the source layers 22, 24 comprises a vertical stack of a doped semiconductor source layer 24 and a metal source layer 22, and each of the drain layers 26, 28 is a doped semiconductor drain layer ( 26 ) and a vertical stack of metal drain layers 28 . When the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are omitted, each of the source layers consists of a doped semiconductor source layer 24 or a doped semiconductor drain layer 26 .

A dielectric material may be deposited in the backside trenches 79 and over the top insulating layer 32T. Portions of dielectric material filling backside trenches 79 constitute backside trench filling structures 76 . Portions of dielectric filling material overlying the topmost insulating layer 32T constitute the contact level dielectric layer 80 .

Referring to FIG. 32 , the process steps of FIG. 9A may be performed to form contact via structures 88 , 86 through contact level dielectric layer 80 and optionally through reverse-stepped dielectric material portion 65 . can Contact via structures 88 , 86 include word line contact via structures 88 , each in contact with a respective contact pad structure of contact pad structures 68 and at a respective gate electrode 66 . electrically connected. In addition, contact via structures 88 and 86 are layered contact via structures in contact with respective layers of source layers 22 and 24 and drain layers 26 and 28 in respective stepped regions 200A, 200B. (86) (eg, 86S, 86D). Specifically, each of the layer contact via structures 86S, 86D is a respective layer of the source layers 22, 24 or the drain layers 26, 28 exposed to stepped surfaces in the stepped regions 200A, 200B. may be in contact with the horizontal surface of Word lines 98 are then formed over contact level dielectric layer 80 (and over gate electrodes 66, source layers 22, 24, and drain layers 26, 28), and a contact via structure ( 88 and optional contact pad structures 68 , in electrical contact with the gate electrodes 66 .

Referring to FIG. 33 , a fourth exemplary structure according to a fourth embodiment of the present invention is derived from the first exemplary structure of FIG. 1 by replacing the channel level insulating layers 32C with the channel level sacrificial material layers 232 . can be Thus, each instance of the unit layer stack within the plurality of instances of the unit layer stack is a source sacrificial material layer 42S, doped semiconductor source layer 24, channel level sacrificial material layers 232, doped semiconductor drain layer. 26 , a drain sacrificial material layer 42D, and an inter-transistor level insulating layer 321 .

Channel level sacrificial material layers 232 are optionally in materials of doped semiconductor source layers 24 , doped semiconductor drain layers 26 , and inter-transistor level insulating layers 321 , and source sacrificial material layers 42S ) and a material that can be selectively removed in metal materials to be employed for the metal source layers and metal drain layers subsequently replacing the drain sacrificial material layers 42D. For example, the channel level sacrificial material layers 232 may include a material such as a dielectric metal oxide (eg, aluminum oxide), a silicon germanium alloy having an atomic concentration of germanium greater than 20%, a polymer material, or the source sacrificial material layers 42S ) and a metal material different from the metal materials to be employed for the metal source layers and metal drain layers subsequently replacing the drain sacrificial material layers 42D. Each of the channel level sacrificial material layers 232 may have a thickness in the range of 5 nm to 50 nm, although smaller and larger thicknesses may also be employed.

Multiple instances of the unit layer stack include an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 . Channel level sacrificial material layers 232 are formed at the levels of semiconductor channels to be subsequently formed. For example, channel level sacrificial material layers 232 may be formed between an underlying doped semiconductor source layer 24 and an overlying doped semiconductor drain layer 26 of each vertically neighboring pair. Inter-transistor level insulating layers 321 may be provided at the levels of inter-transistor gaps to be subsequently formed. For example, inter-transistor level insulating layers 321 may be formed between an overlying doped semiconductor source layer 24 and an underlying doped semiconductor drain layer 26 of vertically adjacent pairs.

Referring to FIG. 34 , the process steps of FIG. 2 may be performed to form stepped cavities 69 in step regions 200A, 200B. Stepped surfaces are formed in the step areas 200A, 200B. The steps of the anisotropic etch processes to form stepped surfaces may be modified to provide an etch chemistry that effectively etches the channel level sacrificial material layers 232 .

35A and 35B , the process steps of FIGS. 3A and 3B may be performed to form memory openings 49 through each layer in multiple instances of a unit layer stack. As discussed above, the unit layer stack of the second exemplary structure includes a source sacrificial material layer 42S, doped semiconductor source layer 24 , channel level sacrificial material layers 232 , doped semiconductor drain layer 26 . , a drain sacrificial material layer 42D, and an inter-transistor level insulating layer 321 . The steps of the anisotropic etch processes to form the memory openings 49 may be modified to provide an etch chemistry that effectively etches the channel level sacrificial material layers 232 .

Referring to FIG. 36 , successive layers of material may be sequentially deposited into each of the memory openings 49 . The continuous material layers may include a continuous memory film, a continuous conductive material layer, and an optional dielectric fill material layer. Excess portions of the successive material layers may be removed from above a horizontal plane including the top surface of the topmost insulating layers 32T and the top surfaces of the reverse-stepped dielectric material portions by a planarization process. The planarization process may employ chemical mechanical planarization and/or at least one recess etch process. Each portion of the continuous material layers remaining within the memory opening 49 constitutes a memory opening filling structure 58 .

Each memory aperture filling structure 58 includes a memory film 54 , a gate electrode 66 , and an optional dielectric core 62 . Each memory film 54 is the remainder of the continuous memory film after the planarization process. Each gate electrode 66 is the remainder of the continuous conductive material layer after the planarization process. Each dielectric core 62 is the remainder of the dielectric fill material layer.

Memory film 54 includes at least one material layer capable of storing data bits in the form of trapped electrical charges, polarization, or magnetic moments. In one embodiment, each of the memory films comprises, from the outside to the inside, a tunneling dielectric layer 542 , a charge storage layer 544 in contact with the tunneling dielectric layer 542 , and a blocking contact with the charge storage layer 544 . dielectric layer 546 . Tunneling dielectric layer 542 may include a tunneling dielectric material such as a silicon oxide layer or an ONO stack (ie, a stack of silicon oxide layers, silicon nitride layers, and silicon oxide layers). Charge storage layer 544 may include a charge storage material such as silicon nitride. Blocking dielectric layer 546 may include a blocking dielectric material such as silicon oxide and/or dielectric metal oxide. In another embodiment, each of the memory films 54 includes at least one optional layer of dielectric material (eg, a silicon oxide layer) and a layer of ferroelectric material that can contact the channel level sacrificial material layers 232 or the gate electrode 66 (not shown).

Each gate electrode 66 includes a conductive material, such as a metallic material. For example, each gate electrode 66 may have a metal layer comprising a metal (eg, W, Co, Mo, Ru, Cu, or alloys thereof) and a conductive metal nitride (eg, TiN, TaN, or WN). and a layer stack of metal nitride liners comprising:

Each dielectric core 62 includes a dielectric filling material such as silicon oxide. In one embodiment, the dielectric cores 62 may include a dielectric material that has a higher etch rate than the topmost insulating layer 32T in the etch process. For example, dielectric cores 62 may include borosilicate glass, organosilicate glass, or phosphosilicate glass, and top insulating layer 32T may include densified undoped silicate glass. In this case, the material of the dielectric cores 62 may be subsequently recessed relative to the material of the topmost insulating layer 32T.

A memory film 54 may be formed on the sidewalls of each layer of the multiple iterations of the unit layer stack, and a gate electrode 66 may be formed on each of the memory films 54 . Each of the memory films 54 passes through each of doped semiconductor source layers 24 and doped semiconductor drain layers 26 of an alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 . is extended Each of the gate electrodes 66 extends vertically through each of the doped semiconductor source layers 24 and doped semiconductor drain layers 26 of the alternating stack.

Each memory film 54 includes a cylindrical portion and a bottom cap portion adjacent the lower periphery of the cylindrical portion. Each gate electrode 66 may include a cylindrical portion and a bottom cap portion adjacent a lower periphery of the cylindrical portion. The gate electrodes 66 may be vertically spaced from the substrate 9 by horizontal portions of the memory films 54 . Each of the gate electrodes 66 may laterally surround a respective dielectric core 62 .

Referring to FIG. 37 , the process steps of FIG. 5 may be performed to form contact pad structures 68 . Each memory aperture filling structure 58 may include a respective contact pad structure 68 in contact with a top end of a respective gate electrode of the gate electrodes 66 . 38A and 38B , the process steps of FIGS. 6A and 6B may be performed to form backside trenches 79 through multiple instances of the unit layer stack. The steps of the anisotropic etch processes to form the backside trenches 79 may be modified to provide an etch chemistry that effectively etches the channel level sacrificial material layers 232 .

Referring to FIG. 39 , channel level sacrificial material layers 232 , inter-transistor level insulating layers 321 , doped semiconductor source layers 24 , doped semiconductor drain layers 26 , and a reverse-stepped dielectric material portion An etchant that selectively etches the materials of the source sacrificial material layer 42S and the drain sacrificial material layers 42D relative to the materials of the 65 , for example employing an etching process, into the backside trenches 79 . can be introduced. Source level backside recesses 43S and drain level backside recesses 43D are respectively formed in the volumes from which the source sacrificial material layer 42S and drain sacrificial material layers 42D are removed. In one embodiment, the source sacrificial material layer 42S and the drain sacrificial material layers 42D may include silicon nitride, the material of the inter-transistor level insulating layers 321 and the inverse-stepped dielectric material portion 65 . These may include silicate glass materials, such as undoped silicate glass, doped silicate glass, and/or organosilicate glass, the material of the channel level sacrificial material layers 232 being a dielectric metal oxide (eg, aluminum oxide) and In the same material, a silicon germanium alloy having an atomic concentration of germanium greater than 20%, a polymer material, or metal source layers and metal drain layers subsequently replacing the source sacrificial material layers 42S and the drain sacrificial material layers 42D. It may include a different metal material than the metal materials to be employed for it.

The etching process may be a wet etching process employing a wet etching solution, or it may be a gas phase (dry) etching process in which the etchant is introduced into the backside trenches 79 in the vapor phase. For example, if the source sacrificial material layers 42S and the drain sacrificial material layers 42D include silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etch tank containing phosphoric acid. , which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the present technology.

Referring to FIG. 40 , at least one metal material may be deposited in the source level backside recesses 43S and the drain level backside recesses 43D. The at least one metal material includes a metal nitride material (eg, TaN, TiN, or WN) forming a metal liner and source level backside recesses 43S and drain level backside recesses 43D not filled by the metal liner. ) may include a metal filling material (eg, W, Co, Ru, or Mo) that fills the remaining volumes. At least one metallic material fills all volumes of the source level backside recesses 43S and the drain level backside recesses 43D. Portions of at least one metallic material deposited on peripheral portions of backside trenches 79 or over top insulating layer 32T may be removed by an etching process, including an isotropic etching process and/or an anisotropic etching process. can do. The remaining portions of the at least one metal material filling the source level backside recesses 43S constitute the metal source layers 22 . The remaining portions of the at least one metal material filling the drain level backside recesses 43D constitute the metal drain layers 28 . Each adjacent combination of doped semiconductor source layer 24 and metal source layer 22 forms source layers 22, 24 that serve as source regions and source lines for a respective two-dimensional array of vertical field effect transistors. make up

Each adjacent combination of doped semiconductor drain layer 26 and metal drain layer 28 forms drain layers 26 and 28 that serve as bit lines and drain regions for a respective two-dimensional array of vertical field effect transistors. make up

Source sacrificial material layer 42S and drain level sacrificial material layers 42D are optional elements that may be omitted. When the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are present, the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are the metal source layers 22 and metal drain layers respectively is replaced by (28). In this case, each of the source layers 22, 24 comprises a vertical stack of a doped semiconductor source layer 24 and a metal source layer 22, and each of the drain layers 26, 28 is a doped semiconductor drain layer ( 26 ) and a vertical stack of metal drain layers 28 . In the case where the source sacrificial material layer 42S and the drain level sacrificial material layers 42D are omitted, each of the source layers is a doped semiconductor source layer 24, as described in greater detail with respect to FIGS. 45-47 below. or a doped semiconductor drain layer 26 . If layers 42S and 42D are omitted, channel level sacrificial material layers 232 may include silicon nitride.

Referring to FIG. 41 , the channel level backside recesses 233 include doped semiconductor source layers 24 , doped semiconductor drain layers 26 , inter-transistor level insulating layers 321 , and optional metal source layers 22 . , and by removing the channel level sacrificial material layers 232 selectively to the materials of the optional metal drain layers 28 , physically attached to the surfaces of the substrate 9 (which may be semiconductor surfaces). may be exposed. In one embodiment, the channel level sacrificial material layers 232 are a material such as a dielectric metal oxide (eg, aluminum oxide), a silicon germanium alloy having an atomic concentration of germanium greater than 20%, a polymer material, or metal source layers 22 ) and a metal material different from the metal materials of the metal drain layers 28 , and the inter-transistor level insulating layers 321 may include silicon oxide. Alternatively, if the metal source layers 22 and metal drain layers 28 are omitted, the channel level sacrificial material layers 232 may include silicon nitride and may be selectively removed by phosphoric acid etching.

Referring to FIG. 42 , a continuous doped semiconductor material layer is conformally within the channel level backside recesses 233 , in the peripheral regions of the backside trenches 79 , and over the top surface of the topmost insulating layer 32T. can be calm. The continuously doped semiconductor material layer comprises a semiconductor material having a doping of a second conductivity type opposite to the first conductivity type.

The semiconductor material in the continuously doped semiconductor channel layer may include silicon, a silicon germanium alloy, or a compound semiconductor material. The atomic concentration of dopants of the second conductivity type in the continuously doped semiconductor material layer may range from 1.0 x 10 ¹⁴ /cm 3 to 3.0 x 10 ¹⁷ /cm 3 , although smaller and larger atomic concentrations may also be employed. The thickness of the continuously doped semiconductor material layer may be less than half the minimum height of the channel level backside recesses 233 and may range from 1 nm to 20 nm, such as 3 nm to 10 nm, but smaller and Larger thicknesses may also be employed.

An anisotropic etch process may be performed to remove portions of the continuous doped semiconductor material layer formed in the backside trenches 79 and over the top insulating layer 32T. Each remaining portion of the successively doped semiconductor material layer in the channel level backside recesses 233 constitutes the semiconductor channel material layer 460 . The semiconductor channel material layers 460 may be conformal material layers located entirely within respective channel level backside recesses of the channel level backside recesses 233 . Each cylindrical portion of the layers of semiconductor channel material 460 that laterally surrounds the memory film 54 constitutes a semiconductor channel 60'. Each vertical semiconductor channel 60 ′ contacts a bottom surface of an overlying doped semiconductor layer, such as doped semiconductor drain layer 26 , and an underlying doped semiconductor layer, such as doped semiconductor source layer 24 . in contact with the top surface of A vertical stack of semiconductor channels 60 consists of a doped semiconductor source layer and doped semiconductor drain layer 26 of a respective vertically neighboring pair after formation of memory films 54 and gate electrodes 66 . It may be formed on horizontal planes. Each vertical stack of semiconductor channels 60 ′ laterally surrounds a respective memory film 54 and a respective gate electrode 66 .

Referring to FIG. 43 , a dielectric material may be deposited in the remaining volumes of the channel level backside recesses 233 by a conformal deposition process. Portions of dielectric material filling the channel level backside recesses 233 constitute replacement insulating layers, referred to herein as channel level insulating layers 276 . Portions of dielectric material filling backside trenches 79 constitute backside trench filling structures 76 . Portions of dielectric filling material overlying the topmost insulating layer 32T constitute the contact level dielectric layer 80 . The dielectric material of the channel level insulating layers 276, the backside trench fill structure 76, and the contact level dielectric layer 80 may have a uniform material composition throughout, including doped silicate glass, undoped silicate glass, or organosilicate glass.

Insulating layers 276 , 321 are provided between each vertically neighboring pair of source layers 22 , 24 and drain layers 26 , 28 . In one embodiment, the insulating layers 276 and 321 may have the same dielectric material composition throughout, which may be a composition of doped silicate glass, undoped silicate glass, or organosilicate glass. In another embodiment, the channel level insulating layers 276 may have a different composition from the inter-transistor level insulating layers 321 . For example, the channel level insulating layers 276 in contact with a respective semiconductor channel of the semiconductor channels 60 ′ may have a first dielectric material composition and not in contact with any of the semiconductor channels 60 ′. Inter-transistor level insulating layers 321 may have a second dielectric material composition different from the first dielectric material composition. In one embodiment, each semiconductor channel of the vertical stack of semiconductor channels 60 ′ has a respective semiconductor channel positioned between a respective vertically neighboring pair of source layers 22 , 24 and drain layers 26 , 28 . It contacts the cylindrical sidewalls of the channel level insulating layer 276 .

Referring to FIG. 44 , the process steps of FIG. 9A may be performed to form contact via structures 88 , 86 through contact level dielectric layer 80 and optionally through reverse-stepped dielectric material portion 65 . can Contact via structures 88 , 86 include word line contact via structures 88 , each in contact with a respective contact pad structure of contact pad structures 68 and at a respective gate electrode 66 . electrically connected. In addition, contact via structures 88 and 86 are layered contact via structures in contact with respective layers of source layers 22 and 24 and drain layers 26 and 28 in respective stepped regions 200A, 200B. (86) (eg, 86S, 86D). Specifically, each of the layer contact via structures 86S, 86D is a respective layer of the source layers 22, 24 or the drain layers 26, 28 exposed to stepped surfaces in the stepped regions 200A, 200B. may be in contact with the horizontal surface of Word lines 98 are then formed over contact level dielectric layer 80 (and over gate electrodes 66, source layers 22, 24, and drain layers 26, 28), and a contact via structure ( 88 and optional contact pad structures 68 , in electrical contact with the gate electrodes 66 .

Referring to FIG. 45 , a fourth exemplary embodiment formed by omitting the source sacrificial layers 42S and the drain sacrificial layers 42D in a process step corresponding to the process steps of FIG. 34 according to the fourth embodiment of the present invention An alternative embodiment of the structure is illustrated. In such an embodiment, the channel level sacrificial material layers 232 may include silicon nitride.

Referring to FIG. 46 , an alternative embodiment of the fourth exemplary embodiment is illustrated in process steps corresponding to the process steps in FIG. 37 .

Referring to FIG. 47 , an alternative embodiment of a fourth exemplary structure is illustrated in a process step corresponding to the process steps of FIG. 44 , wherein the channel level sacrificial material layers 232 are selectively etched (eg, phosphoric acid). etch) and replaced with vertical semiconductor channels 60'. Optionally, the vertical semiconductor channel 60' and the doped semiconductor source layers 24 and drain layers 26 using a selective etch to etch semiconductor materials (eg, silicon) relative to the remaining insulating layers in the stack. It may be recessed by selective etching through the backside trenches 79 . Metal is then formed in the recesses to form an electrically conductive source line 122 and an electrically conductive drain line 128 in contact with the respective semiconductor source layers 24 and drain layers 26 . The metal may include tungsten, nickel or cobalt. If desired, the metal is reacted with the respective semiconductor source layers 24 and drain layers 26, and all or part of the electrically conductive source line 122 and the electrically conductive drain line 128 is replaced with a metal silicide, such as tungsten silicide; A silicidation anneal may be performed to convert to nickel silicide or cobalt silicide. The electrically conductive source line 122 and the electrically conductive drain line 128 may contact the semiconductor channel material layer 460 , or may be formed such that they do not contact the semiconductor channel material layer 460 .

With reference to all figures of the third exemplary structure and the fourth exemplary structure, a three-dimensional memory device is provided, comprising source layers 24 , optionally 22 , and drain layers 26 , optionally located over a substrate 9 . 28), an array of memory openings 49 extending vertically through the alternating stack, source layers of alternating stacks respectively located within respective memory openings of the array of memory openings 49 ( 24, optionally 22, and gate electrodes 66 extending vertically through each of the drain layers 26, optionally 28; memory films 54 each positioned within one of the array of memory openings 49 and laterally surrounding a respective gate electrode of the gate electrodes 66 , and each of the memory films 54 . vertical stacks of semiconductor channels 360 , 60 ′ laterally surrounding a memory film of Layer 24 (optionally 22) and a respective vertically neighboring pair of horizontal surfaces of a drain layer 26 (optionally 28) of the drain layers 26 (optionally 28).

In one embodiment, word lines 98 are positioned over gate electrodes 66 and over an alternating stack of source and drain layers, where word lines 98 electrically connect to gate electrodes 66 . connected

In one embodiment, insulating layers 132 , 270 , 321 are positioned between each vertically neighboring pair of source layer 24 , optionally 22 and drain layer 26 , optionally 28 .

In one embodiment, insulating layers 132 , 270 , 321 include channel level insulating layers 132 , 270 in contact with respective semiconductor channels of semiconductor channels 360 , 60 ′; and inter-transistor level insulating layers 321 that do not contact any of the semiconductor channels 360, 60'.

In one embodiment, the sidewalls of the channel level insulating layers 132 are source layers 24 (optionally 22) and drain layers with respect to the sidewalls of the inter-transistor level insulating layers 321 and around each memory opening 49 . 26 , optionally laterally recessed to the sidewalls of 28 .

In one embodiment, each of the channel level insulating layers 132 is in direct contact with the horizontal surfaces of a respective source layer of source layers 24 , optionally 22 and a respective drain layer of drain layers 26 , optionally 28 . do.

In one embodiment, each of the channel level insulating layers 270 is not in contact with the source layers 24 , optionally 22 , and the drain layers 26 , optionally 28 , therefrom at least a respective semiconductor channel material layer 460 . vertically spaced by

In one embodiment, each of the vertical stacks of semiconductor channels 360 , 60 ′ includes a set of individual semiconductor channels 360 , 60 ′ that are vertically spaced apart from each other without direct contact with each other.

In one embodiment, the entirety of the outer sidewall of each semiconductor channel 360 , 60 ′ is between the respective vertically neighboring pair of source layer 24 , optionally 22 and drain layers 26 , optionally 28 . It contacts the cylindrical sidewalls of the respective channel level insulating layers 132 , 270 located there.

In a third embodiment, the outer sidewall of each semiconductor channel 360 is the horizontal of one of the source layer 24 (optionally 22) and the drain layer 26 (optionally 28) in a respective vertically neighboring pair. and an upper perimeter in contact with the surface and a lower perimeter in contact with the horizontal surface of the other of the respective vertically neighboring pairs of source layer 24, optionally 22 and drain layer 26, optionally 28. do.

In a fourth embodiment, each of the semiconductor channels 60' comprises a hollow cylindrical segment of a semiconductor channel material layer 460, which is an upper semiconductor channel material layer segment adjacent the upper end of the respective semiconductor channel 60'. ; and a lower semiconductor channel material layer segment adjacent the lower end of the respective semiconductor channel 60'. The upper semiconductor channel material layer segment is the upper horizontal portion of the semiconductor channel material layer 460 in contact with an overlying doped semiconductor material layer such as the doped semiconductor drain layer 26 at the first p-n junction. The lower semiconductor channel material layer segment is the lower horizontal portion of the semiconductor channel material layer 460 in contact with an overlying doped semiconductor material layer such as the doped semiconductor source layer 24 at the second p-n junction.

In one embodiment, the semiconductor channel material layer 460 includes a set of semiconductor channels 60 ′ including a hollow cylindrical segment and additional cylindrical segments laterally surrounding the gate electrodes 66 .

In one embodiment, each of the source layers 24 , 22 comprises a vertical stack of a doped semiconductor source layer 24 and a metal source line 22 ; Each of the drain layers 26 , 28 includes a doped semiconductor drain layer 26 and a vertical stack of metal bit lines 28 .

In one embodiment, each of the memory films 54 includes a tunneling dielectric layer 542 ; a charge storage layer 544 in contact with the tunneling dielectric layer 542 ; and a nested layer stack including a blocking dielectric layer 546 in contact with the charge storage layer 544 . In another embodiment, each of the memory films 54 includes and/or consists of a layer of ferroelectric material.

In one embodiment, the three-dimensional memory device includes source layer contact via structures 86S in contact with a respective source layer of source layers 24, optionally 22; and drain layer contact via structures 86D in contact with a respective drain layer of drain layers 26 , optionally 28 .

In one embodiment, the source layers 24 , optionally 22 in the alternating stack, have different lateral extents that decrease with vertical distance from the substrate 9 ; The drain layers 26 , optionally 28 in the alternating stack, have different lateral extents that decrease with vertical distance from the substrate 9 ; a first reverse-stepped dielectric material portion 65 contacts the horizontal surfaces of the source layers 24 , optionally 22 in the alternating stack, and laterally surrounds the source layer contact via structures 86S; Then, a second inverse-stepped dielectric material portion 65 contacts the horizontal surfaces of the drain layers 26 , optionally 28 in the alternating stack, and laterally surrounds the drain layer contact via structures 86D. All.

In one embodiment, the gate electrodes 66 are vertically spaced from the substrate 9 by horizontal portions of the memory films 54 ; each of the gate electrodes 66 laterally surrounds a respective dielectric core 62; Then, the contact pad structures 68 contact the top end of the respective gate electrode of the gate electrodes 66 .

Referring to Figure 48, a circuit diagram for various embodiments of the three-dimensional memory device of the present invention is illustrated. Each source layer 24 , 22 may be laterally bounded by a respective neighboring pair of backside trenches 79 , and includes a source line 22 , 122 (“SL”). The source lines SL are arranged as a three-dimensional array extending along a vertical direction and a horizontal direction parallel to the longitudinal direction of the backside trenches 79 . As such, the source lines SL may be numbered in two-dimensional coordinates (i, j), where i refers to the level of the respective source line and j is the respective neighboring pair of backside trenches 79 . It refers to a space determined by For example, (n+1) source layers 24 , 22 and (n+1) drain layers at respective distances from substrate 9 and between each neighboring pair of backside trenches 79 . If (26, 28) is present, the index i may range from 0 to n. When (m+2) backside trenches 79 are present, (m+1) source layers 24, 22 are provided for each source level and (m+1) drain layers 26, 28 ) is provided for each drain level. The index j may range from 0 to m.

Each drain layer 26 , 28 may be laterally bounded by a respective neighboring pair of backside trenches 79 and includes a bit line 28 , 128 (“BL”). The bit lines BL are arranged as a three-dimensional array extending along a vertical direction and a horizontal direction parallel to the longitudinal direction of the backside trenches 79 .

As such, the bit lines BL may be numbered with the same two-dimensional coordinates (i, j) as the corresponding source line SL (i, j).

The gate electrodes 66 may be arranged as a two-dimensional array and may function as control gate electrodes of the memory vertical field effect transistors. Each transistor is a respective semiconductor channel, which may include a portion of the semiconductor channel layer 60L, may include a separate semiconductor channel 60 , 360 , or may include a semiconductor that is part of the semiconductor channel material layer 460 . It may include a channel 60'. The gate electrodes 66 may be arranged as a two-dimensional array, which may be a hexagonal array or a rectangular array. Gate electrodes 66 extending through the same set of source lines SL and bit lines BL positioned between respective neighboring pairs of backside trenches 79 in the same memory block are a group of gate electrodes. make up Each gate electrode 66 within the same group (ie, within the same memory block) is in electrical contact with a different word line 98 (WL).

The word lines 98 (WL) extend along a horizontal direction perpendicular to the longitudinal direction of the backside trenches 79 (and perpendicular to the directions of the source lines SL and bit lines BL). arranged as a dimensional array. The total number of groups may be (m+1). Each gate electrode 66 within a group of gate electrodes may be individually numbered. If there are (x+1) gate electrodes in each group of electrodes, the gate electrodes can be labeled employing a two-dimensional coordinate system (k, j), where k is an index running from 0 to x and within the group. Individual gate electrodes are identified, where j is an index from 0 to m and identifies the group to which the gate electrode belongs. Thus, the three-dimensional coordinates (i, j, k) can uniquely identify a memory cell.

In the first embodiment, the semiconductor channel is continuous in the vertical direction. Thus, activating one word line 98 activates respective gate electrodes 66 electrically connected to the activated word line 98 . A portion of the memory film 54 adjacent to a portion of the semiconductor channel layer 60L between the pair of activated source and drain regions is activated (eg, programmed, erased, or read). The pair of source and drain regions can be activated by applying a different voltage to the source region than the drain region. The remaining, unselected source and drain regions (and their optional respective source and drain lines) are set to the source voltage of the selected memory cell to avoid activation of the unselected memory cells.

In the second to fourth embodiments, the semiconductor channels are discontinuous in the vertical direction. In these embodiments, one word line 98 is activated to activate respective gate electrodes 66 electrically connected to the activated word line 98 . All memory films 54 can be activated in these embodiments.

Embodiments of the present invention provide a bit-addressable, high-density three-dimensional memory array. The semiconductor channel can be made wider, which provides a tighter threshold voltage distribution. Separate source lines 22, 122 and bit lines 28, 128 for each memory cell provide higher cell current for increased memory speed.

While the foregoing refers to certain preferred embodiments, it will be understood that the invention is not so limited. It will occur to those skilled in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the present invention. Compatibility is assumed between all embodiments that are not alternatives to each other. The word “comprise or include” means that, unless explicitly stated otherwise, the word “consist essentially of” or the word “consisting of” replaces the word “comprise”. All embodiments are considered. When an embodiment employing a particular structure and/or configuration is illustrated in the present invention, the present invention relates to any other functionally equivalent compatible structures and It is understood that/or configurations may be implemented. All publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.

Claims (40)

A three-dimensional memory device comprising:
an alternating stack of source and drain layers positioned over the substrate; gate electrodes extending vertically through each of the source and drain layers of the alternating stack;
memory films that laterally surround respective gate electrodes of the gate electrodes; and semiconductor channels laterally surrounding a respective one of the memory films and in contact with a respective vertically neighboring pair of sidewalls of a source layer of the source layers and a drain layer of the drain layers. 3D memory device. According to claim 1,
word lines positioned over said gate electrodes and over said alternating stack of source and drain layers, said word lines electrically connected to said gate electrodes; and
and an array of memory openings extending vertically through the alternating stack, each of the gate electrodes located within a respective memory opening of the memory openings. The three-dimensional memory device of claim 1 , further comprising insulating layers positioned between each vertically neighboring pair of the source layer and the drain layer. The three-dimensional memory device of claim 3 , wherein the insulating layers have the same dielectric material composition throughout. 4. The method of claim 3, wherein the insulating layers are
channel level insulating layers in contact with a respective semiconductor channel of the semiconductor channels and having a first dielectric material composition; and
and inter-transistor level insulating layers not in contact with any of the semiconductor channels and having a second dielectric material composition different from the first dielectric material composition. 2. The semiconductor channel of claim 1, wherein each of the semiconductor channels includes a respective portion of a continuous semiconductor channel layer having a hollow cylinder shape and extending through a respective source layer and a respective drain layer in the alternating stack. A three-dimensional memory device. The three-dimensional memory device of claim 1 , wherein each of the semiconductor channels comprises one of a set of individual semiconductor channels spaced apart vertically from each other and each having a hollow cylindrical shape. 8. The method of claim 7, wherein each of the individual semiconductor channels has an annular top surface in contact with a bottom surface of a respective overlying inter-transistor insulating layer and an annular top surface in contact with a respective underlying inter-transistor insulating layer. A three-dimensional memory device comprising a bottom surface. The three-dimensional memory device of claim 1 , wherein each of the semiconductor channels is in contact with a cylindrical sidewall of a respective channel level insulating layer positioned between the source and drain layers of a respective vertically neighboring pair. According to claim 1,
each of the source layers comprises a doped semiconductor source layer and a vertical stack of metal source lines;
wherein each of the drain layers comprises a doped semiconductor drain layer and a vertical stack of metal bit lines. The method of claim 1 , wherein each of the memory films comprises a layer stack, the layer stack comprising:
tunneling dielectric layer;
a charge storage layer in contact with the tunneling dielectric layer; and
and a blocking dielectric layer in contact with the charge storage layer. The three-dimensional memory device of claim 1 , wherein each of the memory films comprises a layer of ferroelectric material. According to claim 1,
source layer contact via structures in contact with a respective source layer of the source layers; and
and drain layer contact via structures in contact with a respective drain layer of the drain layers. 14. The method of claim 13,
the source layers in the alternating stack have different lateral extents that decrease with vertical distance from the substrate;
the drain layers in the alternating stack have different lateral extents that decrease with vertical distance from the substrate;
a first reverse-stepped dielectric material portion contacts horizontal surfaces of the source layers in the alternating stack and laterally surrounds the source layer contact via structures;
and a second portion of reverse-stepped dielectric material contacts horizontal surfaces of the drain layers in the alternating stack and laterally surrounds the drain layer contact via structures. According to claim 1,
the gate electrodes are vertically spaced from the substrate by horizontal portions of the memory films;
each of the gate electrodes laterally surrounds a respective dielectric core; and contact pad structures contacting a top end of a respective gate electrode of the gate electrodes. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of doped semiconductor source layers and doped semiconductor drain layers over a substrate;
forming memory openings extending vertically through the alternating stack; forming a continuous semiconductor channel layer within each memory opening - a respective vertically neighboring pair of a doped one of the doped semiconductor source layers and a doped one of the doped semiconductor drain layers semiconductor channels formed on the sidewalls;
forming memory films over the semiconductor channels; and
forming gate electrodes over the memory films, each of the gate electrodes extending vertically through each of the doped semiconductor source layers and the doped semiconductor drain layers of the alternating stack. 17. The method of claim 16, further comprising, prior to formation of the memory openings, forming channel level insulating layers between each vertically neighboring pair of the doped semiconductor source layer and the doped semiconductor drain layer. , Way. 17. The method of claim 16, further comprising forming contact via structures on top surfaces of the gate electrodes, wherein each of the semiconductor channels comprises a respective doped semiconductor source layer and a respective doped semiconductor source layer in the alternating stack. portions of the continuous semiconductor channel layer extending through a doped semiconductor drain layer that remain after formation of the contact via structures. 17. The method of claim 16,
forming an inter-transistor level sacrificial material layer between vertically adjacent pairs of doped semiconductor source and doped semiconductor drain layers prior to formation of the memory openings;
forming backside recesses by removing the inter-transistor level sacrificial material layers selectively with respect to the doped semiconductor source layers and the doped semiconductor drain layers;
dividing each of the successive semiconductor channel layers into a set of discrete semiconductor channels vertically spaced apart from each other by removing portions of each successive semiconductor channel layer that are physically exposed to the backside recesses; and
and depositing an inter-transistor level insulating layer in each of the backside recesses. 17. The method of claim 16,
forming word lines positioned over the gate electrodes and over the alternating stack, the word lines electrically connected to the gate electrodes;
forming source level sacrificial material layers and drain level sacrificial material layers prior to formation of the memory openings such that each of the source level sacrificial material layers is formed under a respective doped semiconductor source layer of the doped semiconductor source layers and a drain causing each of the level sacrificial material layers to be formed over a respective doped semiconductor source layer of the doped semiconductor source layers; and
and replacing the source level sacrificial material layers and drain level sacrificial material layers with metal source lines and metal drain lines, respectively. A three-dimensional memory device comprising:
an alternating stack of source and drain layers positioned over the substrate;
an array of memory openings extending vertically through the alternating stack; gate electrodes, each gate electrode positioned within one of the array of memory openings and extending vertically through each of the source and drain layers of the alternating stack;
memory films, each memory film positioned within one of the array of memory openings and laterally surrounding a respective gate electrode of the gate electrodes; and
vertical stacks of semiconductor channels laterally surrounding a respective memory film of said memory films, each of said vertical semiconductor channels being a respective vertically neighboring one of said source layers and a respective one of said drain layers. A three-dimensional memory device comprising: in contact with a pair of horizontal surfaces. 22. The method of claim 21, further comprising word lines positioned over the gate electrodes and over the alternating stack of source and drain layers, wherein the word lines are electrically connected to the gate electrodes. dimensional memory device. 22. The three-dimensional memory device of claim 21, further comprising insulating layers positioned between each vertically neighboring pair of the source layer and the drain layer. 24. The method of claim 23, wherein the insulating layers comprise:
channel level insulating layers in contact with respective semiconductor channels of the semiconductor channels; and
and inter-transistor level insulating layers not in contact with any of the semiconductor channels. 25. The method of claim 24, wherein the sidewalls of the channel level insulating layers are laterally ripped out to the sidewalls of the inter-transistor level insulating layers and to the sidewalls of the source layers and the drain layers around each memory opening. Accessed, three-dimensional memory device. 25. The three-dimensional memory device of claim 24, wherein each of the channel level insulating layers is in direct contact with horizontal surfaces of a respective source layer of the source layers and a respective drain layer of the drain layers. 25. The three-dimensional memory of claim 24, wherein each of the channel level insulating layers is not in contact with the source layers and the drain layers and is spaced vertically from the source layers and the drain layers at least by a respective semiconductor channel material layer. device. 22. The three-dimensional memory device of claim 21, wherein each of the vertical stacks of semiconductor channels comprises a set of individual semiconductor channels spaced vertically from each other without direct contact with each other. 29. The three-dimensional (3D) of claim 28, wherein the entirety of the outer sidewall of each semiconductor channel is in contact with the cylindrical sidewall of a respective channel level insulating layer positioned between the source and drain layers of a respective vertically neighboring pair. memory device. 30. The pair of claim 29, wherein the outer sidewall includes an upper perimeter in contact with a horizontal surface of one of the source layer and the drain layer in the respective vertically neighboring pair, the respective vertically neighboring pair. and a lower perimeter in contact with a horizontal surface of the other of the source layer and the drain layer within. 30. The method of claim 29, wherein each of the semiconductor channels comprises a hollow cylindrical segment of a layer of semiconductor channel material, the hollow cylindrical segment of the layer of semiconductor channel material comprising:
an upper semiconductor channel material layer segment adjacent an upper end of each semiconductor channel; and
and a lower semiconductor channel material layer segment adjacent a lower end of the respective semiconductor channel. 32. The three-dimensional memory device of claim 31, wherein the semiconductor channel material layer comprises a set of semiconductor channels comprising the hollow cylindrical segment and additional cylindrical segments laterally surrounding the gate electrodes. 32. The method of claim 31,
each of the source layers comprises a doped semiconductor source layer and a vertical stack of metal source lines;
wherein each of the drain layers comprises a doped semiconductor drain layer and a vertical stack of metal bit lines. 32. The method of claim 31 , wherein each of the memory films comprises a layer stack, the layer stack comprising:
tunneling dielectric layer;
a charge storage layer in contact with the tunneling dielectric layer; and
and a blocking dielectric layer in contact with the charge storage layer. 32. The three-dimensional memory device of claim 31, wherein each of the memory films comprises a layer of ferroelectric material. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of doped semiconductor source layers and doped semiconductor drain layers over a substrate;
forming memory openings extending vertically through the alternating stack; forming a memory film and a gate electrode in each memory opening, the memory film and the gate electrode extending vertically through each of the doped semiconductor source layers and the doped semiconductor drain layers of the alternating stack; and
Each vertically adjacent pair of a doped one of the doped semiconductor source layers and a doped one of the doped semiconductor drain layers before or after formation of the memory film and the gate electrode forming a vertical stack of semiconductor channels on the horizontal surfaces of
and each vertical stack of semiconductor channels laterally surrounds the respective memory film and the respective gate electrode. 37. The method of claim 36, further comprising: forming insulating layers between each vertically neighboring pair of a doped one of the doped semiconductor source layers and a doped one of the doped semiconductor drain layers. Further comprising, the insulating layers comprising:
channel level insulating layers formed at the levels of the semiconductor channels; and inter-transistor level insulating layers spaced vertically from the semiconductor channels. 38. The method of claim 37,
the inter-transistor level insulating layers and the channel level insulating layers are formed prior to the formation of the memory openings;
The method is
forming annular cavities by laterally recessing sidewalls of the channel level insulating layers with respect to the sidewalls of the doped semiconductor source layers, doped semiconductor drain layers, and inter-transistor level insulating layers;
conformally depositing a semiconductor material within the annular cavities; and removing portions of the conformally deposited semiconductor material from outside the annular cavities, wherein the remaining portions of the conformally deposited semiconductor material within the annular cavities are the vertical stack of semiconductor channels. How to organize them. 38. The method of claim 37,
forming the inter-transistor level insulating layers and the channel level sacrificial material layers occurs prior to the formation of the memory openings, the channel level sacrificial material layers being formed at levels at which the channel level insulating layers are subsequently formed; ;
The method is
selectively with respect to the doped semiconductor source layers, doped semiconductor drain layers, and the inter-transistor level insulating layers
forming backside recesses by removing the channel level sacrificial material layers; and
depositing a layer of semiconductor channel material in each backside recess, wherein each cylindrical portion of the layers of semiconductor channel material laterally surrounding the memory film constitutes a semiconductor channel of one of the semiconductor channels. How to. 40. The method of claim 39, wherein the channel level insulating layers are formed by depositing insulating material in the unfilled volumes of the backside recesses after formation of the semiconductor channel material layers.

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