CN111463219A - 3D NAND memory device and manufacturing method thereof - Google Patents
3D NAND memory device and manufacturing method thereof Download PDFInfo
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- CN111463219A CN111463219A CN202010311133.6A CN202010311133A CN111463219A CN 111463219 A CN111463219 A CN 111463219A CN 202010311133 A CN202010311133 A CN 202010311133A CN 111463219 A CN111463219 A CN 111463219A
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The invention provides a 3D NAND memory device and a method for manufacturing the same, wherein a sacrificial layer and a stack layer are formed on a substrate, a channel hole and a grid line gap are formed in the stack layer, a memory function layer and a channel layer are formed in the channel hole, the sacrificial layer on the substrate and the memory function layer on the side wall of the sacrificial layer are removed by using the grid line gap, a first opening including the channel layer is formed, an epitaxial layer is formed at the bottom of the first opening, the formed epitaxial layer is contacted with the channel layer, and an insulating layer is formed on the surface of the epitaxial layer and the surface of the channel layer by using a deposition process, the method forms the insulating layer on the surface of the epitaxial layer and the surface of the channel layer by depositing the deposition process, avoids the problem that the top of the exposed channel layer is completely oxidized to cause interruption when the insulating layer is formed on the surface of, thereby improving the reliability of the device.
Description
Technical Field
The invention relates to the field of semiconductor technology and manufacturing thereof, in particular to a 3D NAND memory device and a manufacturing method thereof.
Background
In the manufacturing process of the 3D NAND memory, a stacked layer of a silicon nitride layer and a silicon oxide layer is formed on a substrate, a channel hole is formed in the stacked layer, and a storage function layer and a channel layer are sequentially formed in the channel hole; then, a gate line seam (gate line seam) is formed on the stacked layer, an epitaxial structure is grown on the substrate through the gate line seam, and then an oxide layer is formed above the epitaxial structure.
Disclosure of Invention
In view of the above, the present invention is directed to a 3D NAND memory device and a method for manufacturing the same, which improves the performance of the device.
In order to achieve the purpose, the invention has the following technical scheme:
a method of manufacturing a 3D NAND memory device, comprising:
providing a substrate, wherein a sacrificial layer and a stacking layer are formed on the substrate;
a channel hole and a grid line gap are formed in the stacked layer, the channel hole penetrates through the sacrificial layer to the substrate, and a storage function layer and a channel layer are sequentially formed in the channel hole;
removing the sacrificial layer and the memory function layer on the side wall of the sacrificial layer by using the grid line gap to form a first opening exposing the channel layer;
forming an epitaxial layer at the bottom of the first opening, the epitaxial layer being in contact with the channel layer;
and forming an insulating layer on the surface of the epitaxial layer and the surface of the channel layer by using a deposition process.
Optionally, the deposition process is atomic layer deposition.
Optionally, the insulating layer is a silicon oxide layer.
Optionally, the thickness of the insulating layer ranges from 150 to 200 angstroms.
Optionally, the forming an insulating layer on the surface of the epitaxial layer and the surface of the channel layer by using a deposition process includes:
depositing an insulating material to form insulating layers on the side wall of the grid line gap, the surface of the epitaxial layer and the surface of the channel layer;
forming a filling layer in the first opening;
removing the insulating material on the side wall of the grid line gap;
and removing the filling layer formed in the first opening.
Optionally, before the removing the sacrificial layer and the memory function layer on the sidewall of the sacrificial layer by using the gate line slit, the method further includes:
forming a protective layer on the side wall of the grid line gap;
after removing the insulating material on the side wall of the gate line gap, the method further comprises the following steps:
and removing the protective layer.
Optionally, the protective layer includes a first dielectric layer and a second dielectric layer outside the first dielectric layer, and if the material of the filling layer is the same as that of the first dielectric layer, the removing the protective layer includes:
removing the second dielectric layer;
and removing the first dielectric layer when the filling layer formed in the first opening is removed.
Optionally, the stacked layer is a stacked layer of a third dielectric layer and a fourth dielectric layer, and if the material of the fourth dielectric layer is the same as that of the first dielectric layer, the removing the first dielectric layer and the filling layer further includes:
and removing the fourth dielectric layer in the stacked layers.
Optionally, the method further includes:
and forming a gate layer in the second opening formed after removing the filling layer and the fourth dielectric layer in the stacking layer.
Optionally, the sacrificial layer is a polysilicon layer, and a boron-doped silicon oxide layer is further formed between the substrate and the sacrificial layer.
A 3D NAND memory device comprising:
a substrate having a laminated structure formed thereon;
a channel structure and a grid line structure are formed in the laminated structure, the channel structure penetrates through the laminated structure to the substrate, and a storage function layer and a channel layer are sequentially formed in the channel structure;
the epitaxial layer connected with the channel layer is formed at the bottom of the grid line structure, and the epitaxial layer is located between the substrate and the laminated structure;
and insulation layers are formed on the surface of the epitaxial layer and the surface of the channel layer.
Optionally, a bottom gate layer is further formed between the epitaxial layer and the insulating layer.
Optionally, the storage function layer includes:
the device comprises a blocking layer, a charge storage layer and a tunneling layer.
In the method for manufacturing a 3D NAND memory device according to an embodiment of the present invention, a sacrificial layer and a stack layer are formed on a substrate, a channel hole and a gate line slit are formed in the stack layer, a memory function layer and a channel layer are formed in the channel hole, the sacrificial layer on the substrate and the memory function layer on a sidewall of the sacrificial layer are removed by using the gate line slit, a first opening exposing the channel layer is formed, an epitaxial layer is formed at a bottom of the first opening, the formed epitaxial layer is in contact with the channel layer, and an insulating layer is formed on a surface of the epitaxial layer and a surface of the channel layer by using a deposition process, the method deposits and forms the insulating layer on the surface of the epitaxial layer and the surface of the channel layer by using the deposition process, thereby avoiding a problem that the exposed channel layer is completely oxidized to cause channel layer interruption when the insulating layer is formed on, thereby improving the reliability of the device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 shows a flow chart of a method of manufacturing a 3D NAND memory device in accordance with an embodiment of the invention;
fig. 2 to 13 are schematic structural views illustrating the formation of a 3D NAND memory device according to a manufacturing method of an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
In the existing manufacturing process of the 3D NAND memory, a stacked layer of a silicon nitride layer and a silicon oxide layer is formed on a substrate, a channel hole is formed in the stacked layer, and then an epitaxial structure grows on the surface of the substrate at the bottom of the channel hole, but with the improvement of the requirement of integration level, the number of stacked layers is continuously increased, the appearance of the epitaxial structure formed on the surface of the substrate at the bottom of the channel hole is poor, and the performance of the device is affected, so that a storage function layer and a channel layer can be sequentially formed in the channel hole after the channel hole is formed; then, a gate line seam (gate line seam) is formed on the stacked layer, the gate line seam is used to remove the sacrificial layer on the substrate and the memory function layer on the sidewall of the sacrificial layer, the channel layer is exposed after the sacrificial layer and the memory function layer on the sidewall of the sacrificial layer are removed, an opening is formed, then a semiconductor material is epitaxially grown at the bottom of the opening to form an epitaxial structure, and then an oxide layer is formed on the surface of the epitaxial structure and the exposed sidewall of the channel layer by oxidizing the surface of the epitaxial structure and the exposed surface of the channel layer.
To this end, the present application provides a method of manufacturing a 3D NAND memory device, in which a sacrificial layer and a stack layer are formed on a substrate, a channel hole and a gate line slit are formed in the stack layer, a memory function layer and a channel layer are formed in the channel hole, the sacrificial layer and the memory function layer on a sidewall of the sacrificial layer on the substrate are removed by the gate line slit, a first opening exposing the channel layer is formed, an epitaxial layer is formed at a bottom of the first opening, the formed epitaxial layer is in contact with the channel layer, and an insulating layer is formed on a surface of the epitaxial layer and a surface of the channel layer by a deposition process, the method of depositing the insulating layer on the surface of the epitaxial layer and the surface of the channel layer by the deposition process avoids a problem of completely oxidizing a top of the exposed channel layer to cause channel layer interruption in a process of oxidizing a portion of the exposed channel layer, thereby improving the reliability of the device.
For a better understanding of the technical solutions and effects of the present application, the following detailed description of specific embodiments of the present application will be made with reference to the accompanying drawings.
Referring to fig. 1, in step S01, a substrate 100 is provided, and a sacrificial layer 122 and a stack layer 130 are formed on the substrate 100.
In the embodiment of the present application, the substrate 100 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator). In other embodiments, the semiconductor substrate may further include a substrate of other element semiconductor or compound semiconductor, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as a Si/SiGe substrate, or the like, and may also be other epitaxial structure, such as SGOI (silicon germanium on insulator) or the like. In the present embodiment, the substrate 100 is a bulk silicon substrate.
In an embodiment of the present application, a sacrificial layer 122 is formed on the substrate 100, and the sacrificial layer 122 can be used to occupy a position for a lower select device that subsequently forms a memory cell string. The material of the sacrificial layer 122 may be, for example, polysilicon.
In this embodiment, the doped layer 110 may be formed between the substrate 100 and the sacrificial layer 122, and the doped layer 110 isolates the substrate 100 from the sacrificial layer 122 to perform an electrical regulation function. The doped layer 110 may be, for example, a boron doped silicon oxide layer to improve the current turn-off capability of the device.
In a specific embodiment, a first isolation layer 121 may be formed between the doped layer 110 and the sacrificial layer 122, and the first isolation layer 121 separates the doped layer 110 from the sacrificial layer 122, so as to avoid damage to the doped layer 110 when the sacrificial layer 122 is removed. A second isolation layer 123 may also be formed on the surface of the sacrificial layer 122 to separate the sacrificial layer 122 from the stack layer 130 formed subsequently, so as to avoid damage to the bottom of the stack layer 130 when the sacrificial layer 122 is removed. The materials of the first isolation layer 121 and the second isolation layer 123 may be the same or different, for example, the first isolation layer 121 may be silicon oxide or silicon nitride; the material of the second isolation layer 123 may be silicon nitride.
In the embodiment of the present application, a stack layer 130 may be formed on the sacrificial layer 122, the stack layer 130 is used to form a memory cell string perpendicular to the substrate direction, the memory cell string has a memory function, and the number of layers of the stack layer 130 is determined by the number of layers of the memory cells of the formed 3DNAND memory. The greater the number of layers of the stacked layer 130, the more memory cells included in the memory cell string are formed, and the higher the integration degree of the device is.
The stack layer 130 may include a third dielectric layer 131 and a fourth dielectric layer 132, the fourth dielectric layer 132 occupies a position for a subsequent gate layer formation, the third dielectric layer 131 isolates the fourth dielectric layer 132, and after the fourth dielectric layer 132 is replaced with a sacrificial layer, the third dielectric layer 131 isolates the gate layer to prevent the gate layer from contacting. The third dielectric layer 131 may be, for example, a silicon oxide layer, and the fourth dielectric layer 132 may be, for example, a silicon nitride layer.
The stack layer 130 may be formed of a single stack (single stack), for example, by alternately stacking the third dielectric layers 131 and the fourth dielectric layers 132, or may be formed of a plurality of sub-stacks (multi stacks) stacked in sequence, for example, by alternately stacking portions of the third dielectric layers 131 and the fourth dielectric layers 132 first. In a specific embodiment, the third dielectric layer 131 and the fourth dielectric layer 132 may be alternately deposited in sequence by using chemical vapor deposition, atomic layer deposition or other suitable deposition method to form the stacked layer 130.
In step S02, a channel hole 133 and a gate line slit 150 are formed in the stacked layer 130, the channel hole 133 penetrates the sacrificial layer 122 to the substrate 100, and a storage function layer and a channel layer 144 are sequentially formed in the channel hole 133, as shown in fig. 2 to 4.
In the embodiment of the present application, after forming the stack layer 130 on the sacrificial layer 122, the stack layer 130 may be etched to form a channel hole 133, and the channel hole 133 is used for forming a memory cell string subsequently, as shown in fig. 2. Specifically, the method of forming the channel hole 133 may be: forming a hard mask layer on the surface of the stack layer 130, wherein the hard mask layer may be, for example, a silicon oxide layer or a silicon nitride layer; then spin-coating a photoresist layer on the surface of the hard mask layer, forming a patterned photoresist layer through steps of exposure, development and the like, wherein the pattern of the photoresist can be determined by a mask plate used for forming a channel hole in the 3DNAND memory manufacturing process; transferring the pattern to a hard mask layer; then, the stack layer 130 is etched using the hard mask layer as a mask, so as to form a channel hole 133 penetrating through the stack layer 130, wherein the channel hole 133 may penetrate into the substrate 100. After the channel hole 133 is formed, the hard mask layer and the photoresist layer may be removed. In an implementation, the channel hole 133 may penetrate through the stack layer 130 and the sacrificial layer 122 into the substrate 100, and when the doped layer 110 is formed on the substrate, the channel hole 133 may penetrate through the stack layer 130, the sacrificial layer 122 and the doped layer 110.
Then, a memory function layer and a channel layer 144 are sequentially formed in the channel hole 133, and the memory function layer may include a barrier layer 141, a charge storage layer 142, and a Tunneling (Tunneling) layer 143, which are sequentially stacked, as shown with reference to fig. 3. In a specific embodiment, the blocking layer 141, the charge storage layer 142, and the tunneling layer 143 may be an ONO (Oxide-Nitride-Oxide) stack, i.e., a stack of Oxide, Nitride, and Oxide, and the channel layer 144 may be a polysilicon layer.
In this embodiment, the blocking layer 141, the charge storage layer 142, and the tunneling layer 143 may be sequentially stacked in the trench hole 133 to form a storage function layer, and then the channel layer 144 may be formed on the sidewall of the storage function layer, and a filling layer 145 of an insulating material may be formed between the channel layers 144, where the filling layer 145 may be a silicon oxide layer. In a specific embodiment, a conductive layer may be formed over the memory cell strings, the conductive layer being used to form the upper gate devices of the memory cell strings, the conductive layer also forming the interconnect structure to further form the bit lines. Then, a dielectric layer 134 may be formed over the stacked layer 130, wherein the dielectric layer 134 is used to protect the formed memory function layer and the conductive layer, and the dielectric layer 134 may be, for example, silicon oxide, silicon nitride, or the like. In a specific embodiment, a dielectric layer material may be deposited over stack 130 and then a planarization process may be performed to form a uniform thickness of dielectric layer 134 over the stack, for example, planarization of dielectric layer 134 may be performed using chemical mechanical polishing.
In the embodiment of the present application, after the memory function layer in the channel hole 133 and the channel layer 144 are formed, the stacked layer 130 may be etched to form the gate line slit 150. In this embodiment, the stacked layer 130 may be etched by an etching technique, for example, reactive ion etching, until the stack layer is etched to the upper portion of the sacrificial layer 122, so as to form a gate line gap 150, as shown in fig. 4.
In step S03, the sacrificial layer 122 and the memory function layer on the sidewall of the sacrificial layer 122 are removed by using the gate line slit 150, and a first opening exposing the channel layer 144 is formed, as shown in fig. 5 to 7.
In this embodiment, before the sacrificial layer 122 and the memory function layer on the sidewall of the sacrificial layer 122 are removed by using the gate line gap 150, a protective layer may be formed on the sidewall of the gate line gap 150, as shown in fig. 5, to protect the stack layer 130 on the sidewall of the gate line gap 150 in a process of subsequently removing the sacrificial layer 122 and the memory function layer on the sidewall of the sacrificial layer 122. The protective layer may be a single layer or a stacked structure, in this embodiment, the protective layer is a stacked structure, and may include a first dielectric layer 151 and a second dielectric layer 152 other than the first dielectric layer 151, in this embodiment, the first dielectric layer 151 may be a silicon nitride layer, and the second dielectric layer 152 may be a silicon oxide layer.
Specifically, a first dielectric layer material may be deposited to form a first dielectric layer 151 on the sidewall and the bottom of the gate line gap 150, and then a second dielectric layer material is deposited to form a second dielectric layer 152 on the first dielectric layer 151, and then the second dielectric layer 152 and the first dielectric layer 151 on the bottom of the gate line gap 150 are etched to form a protective layer on the sidewall of the gate line gap 150. In this embodiment, in the process of removing the second dielectric layer 152 and the second dielectric layer 151 at the bottom of the gate line gap 150 by etching, the first dielectric layer 151 and the second dielectric layer 152 at the bottom of the gate line gap 150 may be removed by dry etching, for example, the protective layer may be removed by selecting a dry etching selection ratio of 1: 1.
Then, the sacrificial layer 122 and the memory function layer on the sidewall of the sacrificial layer 122 are removed by using the gate line gap 150, specifically, the sacrificial layer 122 may be removed by etching by using wet etching or gas etching, and then the memory function layer on the sidewall of the sacrificial layer 122 is further removed by etching, so as to form a first opening exposing the channel layer 144, as shown in fig. 6.
In step S04, an epitaxial layer 160 is formed at the bottom of the first opening, and the epitaxial layer 160 is in contact with the channel layer 144, as shown with reference to fig. 7.
In this embodiment, an epitaxial growth process may be adopted to epitaxially grow a semiconductor material at the bottom of the first opening to form an epitaxial layer 160, and the epitaxial layer 160 may connect the channel layer 144 and the doped layer 110 to form a channel path. In a specific embodiment, the epitaxial layer 160 may be formed on the surface of the doped layer 110 above the substrate 100, and since the first opening exposes the channel layer 144 formed in the channel hole, the epitaxial layer 160 is brought into contact with the exposed bottom sidewall of the channel layer 144 while the epitaxial layer 160 is formed on the surface of the doped layer 110 above the substrate.
In step S05, an insulating layer 161 is formed on the surface of the epitaxial layer 160 and the surface of the channel layer 144 by a deposition process, as shown in fig. 8-12.
In the embodiment of the present application, the insulating layer 161 is formed on the surface of the sidewall region (Side wall surface) in the first opening by a deposition process, wherein the surface of the sidewall region includes the upper surface of the epitaxial layer 160, the sidewall surface of the channel layer 144, and the lower surface of the lowest third dielectric layer 131 in the stack layer 130. The insulating layer 161 may serve as a gate oxide layer between a channel of a lower gate device of the memory cell string and an underlying gate, and the insulating layer 161 may be made of silicon oxide, for example.
In the embodiment of the present application, the insulating layer 161 is directly formed on the surface of the epitaxial layer 160 and the surface of the channel layer 144, so that the channel layer 144 is prevented from being interrupted due to damage to the channel layer 144 in the process of forming the insulating layer 161, and the performance of the device is prevented from being affected.
In this embodiment, the deposition process may be Atomic layer deposition (a L D), specifically, an insulating material may be deposited to form the insulating layer 161 on the sidewalls of the gate line slit 150, the surface of the epitaxial layer 160, and the surface of the channel layer 144, as shown in fig. 8, the formed insulating layer 161 may be a silicon oxide layer, in a specific embodiment, the thickness of the insulating layer 161 may be in a range of 150 and 200 angstroms, for example, 200 angstroms, so that the formed insulating layer 161 can well block the channel and the bottom gate of the lower gate device.
In the embodiment of the present invention, a filling layer 162 may be formed in the first opening, as shown in fig. 10, so that the filling layer 162 can protect the surface of the epitaxial layer 160 and the insulating layer 161 on the surface of the channel layer 144 during the process of removing the insulating layer 161 on the sidewall of the gate line gap 150. Specifically, a filling material may be deposited to form a filling material in the first opening and on the sidewall of the gate line slit 150, as shown with reference to fig. 9, and then, the filling layer of the sidewall of the gate line slit 150 may be removed to form a filling layer 162 in the first opening. The material of the filling layer 162 may be silicon nitride, and the filling layer on the sidewall of the gate line gap 150 may be removed by using a phosphoric acid solution, as shown in fig. 10.
Then, the insulating material on the sidewall of the gate line slit 150 is removed, and referring to fig. 11, in the case where the protective layer is formed on the sidewall of the gate line slit 150, the protective layer on the sidewall of the gate line slit 150 may be removed after the insulating material on the sidewall of the gate line slit 150 is removed. In a specific embodiment, the material of the insulating layer 160 may be the same as the material of the second dielectric layer 152 on the sidewall of the gate line gap 150, for example, the insulating layer 160 and the second dielectric layer 152 on the sidewall of the gate line gap 150 may be removed by using the same process, which simplifies the process and improves the efficiency, for example, a hydrofluoric acid solution may be used to remove the insulating layer 160 and the second dielectric layer 152 on the sidewall of the gate line gap 150; of course, the material of the insulating layer 160 may be different from that of the second dielectric layer 152 of the gate line slit 150, and is not limited herein. In this embodiment, the filling layer 162 formed in the first opening is removed, in a specific embodiment, the material of the filling layer 162 may be the same as that of the first dielectric layer 152, for example, the filling layer 162 may be a silicon nitride layer, and the first dielectric layer 151 may be removed at the same time when the filling layer 162 formed in the first opening is removed, for example, a phosphoric acid solution is used, so that the process is simplified and the efficiency is improved.
In this embodiment, the material of the fourth dielectric layer 132 in the stacked layer 130 may be the same as the material of the first dielectric layer 151 in the protective layer, for example, both the materials may be silicon nitride layers, so that the fourth dielectric layer 132 in the stacked layer 130 is removed while the first dielectric layer 151 and the filling layer 162 are removed, as shown in fig. 12, thereby simplifying the etching process, improving the efficiency, and reducing the manufacturing cost.
In this embodiment, the gate layer is formed in the second opening formed after the filling layer 162 and the fourth dielectric layer 132 in the stacked layer 130 are removed, it is understood that the gate layer formed in the position of the original filling layer 162 serves as the gate layer of the lower select transistor, and the gate layer formed in the position of the original fourth dielectric layer 132 serves as the gate layer of the memory cell string. The gate layer may be a conductive material, such as a metal material, such as W or Co, and a barrier layer may be formed before filling the metal material, such as TiN.
After that, other processing processes of the device, such as filling of the gate line gap, formation of a contact of the gate electrode layer, and the like, may be completed.
The manufacturing method of the embodiment of the present application is described in detail above, and the manufacturing method of the embodiment of the present application forms the insulating layer on the surface of the epitaxial layer and the surface of the channel layer by deposition through a deposition process, so as to avoid the problem of device failure caused by cracking or interruption of the channel layer in the process of forming the insulating layer, and improve the performance of the device.
An embodiment of the present application also provides a 3D NAND memory device, shown with reference to fig. 13, including:
a substrate 100, a stacked structure 130 being formed on the substrate 100;
a channel structure and a gate line structure are formed in the laminated structure 130, the channel structure penetrates through the laminated structure 130 to the substrate 100, and a storage function layer and a channel layer 144 are sequentially formed in the channel structure;
the epitaxial layer 160 connected to the channel layer 144 is formed at the bottom of the gate line structure, and the epitaxial layer 160 is located between the substrate 100 and the stacked structure 130;
an insulating layer 161 is formed on the surface of the epitaxial layer 160 and the surface of the channel layer 144.
In the embodiment of the present application, the 3D NAND memory device may be formed according to the above-described manufacturing method, and the insulating layer 161 is formed on the surface of the epitaxial layer 160 and the channel layer 144 through a deposition process, so that the 3D NAND memory device has high performance.
In this embodiment, an underlying gate layer 163 may be formed between the epitaxial layer 160 and the insulating layer 161, and the underlying gate layer 163 may serve as a gate layer of the lower select transistor. In a particular embodiment, the storage function layer may include a blocking layer 141, a charge storage layer 142, and a tunneling layer 143. The blocking layer 141, the charge storage layer 142, and the tunneling layer 143 may be an ONO (Oxide-Nitride-Oxide) stack, i.e., a stack of Oxide, Nitride, and Oxide.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (13)
1. A method of manufacturing a 3D NAND memory device, comprising:
providing a substrate, wherein a sacrificial layer and a stacking layer are formed on the substrate;
a channel hole and a grid line gap are formed in the stacked layer, the channel hole penetrates through the sacrificial layer to the substrate, and a storage function layer and a channel layer are sequentially formed in the channel hole;
removing the sacrificial layer and the memory function layer on the side wall of the sacrificial layer by using the grid line gap to form a first opening exposing the channel layer;
forming an epitaxial layer at the bottom of the first opening, the epitaxial layer being in contact with the channel layer;
and forming an insulating layer on the surface of the epitaxial layer and the surface of the channel layer by using a deposition process.
2. The method of claim 1, wherein the deposition process is atomic layer deposition.
3. The method of claim 1, wherein the insulating layer is a silicon oxide layer.
4. The method as claimed in claim 1, wherein the insulating layer has a thickness in the range of 150-200 angstroms.
5. The method of any of claims 1-4, wherein forming an insulating layer on the surface of the epitaxial layer and the surface of the channel layer using a deposition process comprises:
depositing an insulating material to form insulating layers on the side wall of the grid line gap, the surface of the epitaxial layer and the surface of the channel layer;
forming a filling layer in the first opening;
removing the insulating material on the side wall of the grid line gap;
and removing the filling layer formed in the first opening.
6. The method of claim 5, wherein before the removing the sacrificial layer and the memory function layer on the sidewall of the sacrificial layer by using the gate line slit, the method further comprises:
forming a protective layer on the side wall of the grid line gap;
after removing the insulating material on the side wall of the gate line gap, the method further comprises the following steps:
and removing the protective layer.
7. The method of claim 6, wherein the protection layer comprises a first dielectric layer and a second dielectric layer other than the first dielectric layer, and the filling layer is made of a material identical to that of the first dielectric layer, and the removing the protection layer comprises:
removing the second dielectric layer;
and removing the first dielectric layer when the filling layer formed in the first opening is removed.
8. The method of claim 7, wherein the stack layer is a stack of a third dielectric layer and a fourth dielectric layer, and the fourth dielectric layer and the first dielectric layer are of the same material, and when the first dielectric layer and the filling layer are removed, the method further comprises:
and removing the fourth dielectric layer in the stacked layers.
9. The method of claim 8, further comprising:
and forming a gate layer in the second opening formed after removing the filling layer and the fourth dielectric layer in the stacking layer.
10. The method according to any one of claims 1 to 4, wherein the sacrificial layer is a polysilicon layer, and a boron-doped silicon oxide layer is further formed between the substrate and the sacrificial layer.
11. A 3D NAND memory device, comprising:
a substrate having a laminated structure formed thereon;
a channel structure and a grid line structure are formed in the laminated structure, the channel structure penetrates through the laminated structure to the substrate, and a storage function layer and a channel layer are sequentially formed in the channel structure;
the epitaxial layer connected with the channel layer is formed at the bottom of the grid line structure, and the epitaxial layer is located between the substrate and the laminated structure;
and insulation layers are formed on the surface of the epitaxial layer and the surface of the channel layer.
12. The memory device of claim 11, wherein a bottom gate layer is further formed between the epitaxial layer and the insulating layer.
13. The memory device of claim 11, wherein the storage function layer comprises:
the device comprises a blocking layer, a charge storage layer and a tunneling layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010311133.6A CN111463219A (en) | 2020-04-20 | 2020-04-20 | 3D NAND memory device and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112185977A (en) * | 2020-09-27 | 2021-01-05 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN112466887A (en) * | 2020-11-17 | 2021-03-09 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN112951839A (en) * | 2021-02-22 | 2021-06-11 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device and 3D memory device thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140094012A1 (en) * | 2010-08-20 | 2014-04-03 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices |
| US20160293621A1 (en) * | 2015-03-31 | 2016-10-06 | Sandisk Technologies Inc. | Bridge line structure for bit line connection in a three-dimensional semiconductor device |
| US20190319100A1 (en) * | 2018-04-12 | 2019-10-17 | Sandisk Technologies Llc | Three-dimensional memory device including germanium-containing vertical channels and method of making the same |
-
2020
- 2020-04-20 CN CN202010311133.6A patent/CN111463219A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140094012A1 (en) * | 2010-08-20 | 2014-04-03 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices |
| US20160293621A1 (en) * | 2015-03-31 | 2016-10-06 | Sandisk Technologies Inc. | Bridge line structure for bit line connection in a three-dimensional semiconductor device |
| US20190319100A1 (en) * | 2018-04-12 | 2019-10-17 | Sandisk Technologies Llc | Three-dimensional memory device including germanium-containing vertical channels and method of making the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112185977A (en) * | 2020-09-27 | 2021-01-05 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN112185977B (en) * | 2020-09-27 | 2021-10-19 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN112466887A (en) * | 2020-11-17 | 2021-03-09 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN112951839A (en) * | 2021-02-22 | 2021-06-11 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device and 3D memory device thereof |
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