CN112018129A - 3D NAND memory device and manufacturing method thereof - Google Patents
3D NAND memory device and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The application provides a 3D NAND memory device and a manufacturing method thereof, the manufacturing method can include providing a substrate, forming a stack layer with insulating layers and gate layers alternately stacked on the substrate, wherein the side wall of the stack layer is of a step structure, a first dielectric layer and a second dielectric layer are sequentially formed on the step structure, the upper surface of the first dielectric layer is arranged along the step structure, the upper surface of the second dielectric layer is arranged along the plane direction of the substrate, therefore, the thicknesses of the first dielectric layer at different positions are basically consistent, the thicknesses of the second dielectric layer are different, the first dielectric layer is used as an etching stop layer, the second dielectric layer is etched at the step structure to form a step contact opening, then, the first dielectric layer at the bottom of the step contact opening can be etched, the damage to the gate layer caused by excessive etching of the dielectric layer at the position of the step surface far away from the substrate is avoided, or the gate layer is not exposed because the etching of the position of the step surface close to the substrate is insufficient, and reliable extraction of the grid layer is realized.
Description
Technical Field
The invention relates to the field of semiconductor devices and manufacturing thereof, in particular to a 3D NAND memory device and a manufacturing method thereof.
Background
In the 3D NAND memory device structure, a mode of vertically stacking a plurality of layers of grids is adopted, the central area of a stacking layer is a core storage area, the edge area of the stacking layer is of a step structure, the core storage area is used for forming a memory cell string, a grid layer in the stacking layer is used as a grid line of each layer of memory cells, and the grid line is led out through contact on the step, so that the stacking type 3D NAND memory device is realized.
Specifically, a dielectric layer can be formed on the step structure, a step contact hole penetrating through the step structure can be obtained by etching the dielectric layer, and the step contact hole can expose a gate layer in the step structure, so that after the step contact hole is filled with a conductive material, a lead-out wire in the step contact hole can be formed, and the lead-out of a gate line at the step can be realized. However, in practical operation, the gate layer may be damaged in the process of etching the dielectric layer to obtain the step contact hole, and when the gate layer is thin, the gate layer may penetrate through the gate layer, and even the wrong connection between different gate layers may be caused, which affects the device performance. How to realize reliable grid extraction is an important problem in the field.
Disclosure of Invention
In view of this, an object of the present application is to provide a 3D NAND memory device and a method for manufacturing the same, which can effectively control the process quality and ensure the device performance.
In order to achieve the purpose, the technical scheme is as follows:
a method of manufacturing a 3D NAND memory device, comprising:
providing a substrate; a stacked layer formed by alternately stacking insulating layers and gate electrode layers is formed on the substrate, and the side wall of the stacked layer is of a step structure; a first dielectric layer and a second dielectric layer are sequentially formed on the step structure, the upper surface of the first dielectric layer is along the step structure, and the upper surface of the second dielectric layer is along the plane direction of the substrate;
etching the second dielectric layer at the step structure by taking the first dielectric layer as an etching stop layer to form a step contact opening;
and etching the first dielectric layer at the bottom of the step contact opening to form a step contact hole penetrating to the step structure.
Optionally, the first dielectric layer is silicon nitride, and the second dielectric layer is silicon oxide.
Optionally, the second dielectric layer is silicon oxide based on TEOS.
Optionally, the method further includes a third dielectric layer between the step structure and the first dielectric layer, and etching the first dielectric layer at the bottom of the step contact opening to form a step contact hole penetrating through the step structure, including:
etching the first dielectric layer at the bottom of the step contact opening by taking the third dielectric layer as an etching stop layer so as to deepen the step contact opening;
and etching the third dielectric layer or the third dielectric layer and the insulating layer by taking the gate layer as an etching stop layer to form a step contact hole penetrating through the step structure.
Optionally, the third dielectric layer is high-density plasma silicon oxide or atomic layer deposition silicon oxide.
Optionally, after the step contact hole is formed, the method further includes:
and forming a step contact portion in the step contact hole.
Embodiments of the present application also provide a 3D NAND memory device, including:
a substrate;
the insulating layers and the grid electrode layers on the substrate are stacked alternately, and the side wall of the stacked layer is of a step structure; the step structure is sequentially provided with a first medium layer, a second medium layer and a step contact part penetrating through the first medium layer and the second medium layer, the upper surface of the first medium layer is along the step structure, and the upper surface of the second medium layer is along the plane direction of the substrate.
Optionally, the first dielectric layer is silicon nitride, and the second dielectric layer is silicon oxide.
Optionally, the second dielectric layer is silicon oxide based on TEOS.
Optionally, the step structure further includes a third dielectric layer between the step structure and the first dielectric layer, and the step contact portion penetrates through the third dielectric layer.
Optionally, the third dielectric layer is high-density plasma silicon oxide or atomic layer deposition silicon oxide.
The embodiment of the application provides a 3D NAND memory device and a manufacturing method thereof, the manufacturing method can include providing a substrate, forming a stacked layer with alternately stacked insulating layers and gate layers on the substrate, wherein the side wall of the stacked layer is of a step structure, the step structure is sequentially provided with a first dielectric layer and a second dielectric layer, the upper surface of the first dielectric layer is arranged along the step structure, and the upper surface of the second dielectric layer is arranged along the plane direction of the substrate, so the thicknesses of the first dielectric layer at different positions are basically consistent, the thicknesses of the second dielectric layers are different, the first dielectric layer is used as an etching stop layer, the second dielectric layer is etched at the step structure to form a step contact opening, and the first dielectric layer is used as the etching stop layer to enable the etching of the second dielectric layer at each position to be sufficient without damaging the gate layer below, the first dielectric layer at the bottom of the step contact opening can be etched, and the condition that the etching degrees of different positions are different due to the fact that the thicknesses of the first dielectric layers are basically consistent does not exist, so that damage to the gate layer caused by excessive etching of the dielectric layer at the position, far away from the substrate, of the step surface can be avoided, or the gate layer is not exposed due to insufficient etching of the dielectric layer at the position, close to the substrate, of the step surface, and therefore reliable leading-out of the gate layer can be achieved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 shows a schematic of the structure of a current 3D NAND memory device;
FIG. 2 shows a contact schematic in a current 3D NAND memory device;
FIG. 3 is a flow chart showing a method of manufacturing a 3D NAND memory device according to an embodiment of the present application;
FIGS. 4-17 are schematic diagrams illustrating device structures during formation of a memory device according to an embodiment of the present disclosure;
fig. 18 shows a contact schematic diagram in a 3D NAND memory device of an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background art, a dielectric layer may be formed on the step structure, and a step contact hole penetrating through the step structure may be obtained by etching the dielectric layer, and the step contact hole may expose the gate layer in the step structure, so that after the step contact hole is filled with a conductive material, a lead-out line in the step contact hole may be formed, thereby realizing the lead-out of the gate line at the step.
However, in actual operation, the gate layer may be damaged in the process of etching the dielectric layer to obtain the step contact hole, and when the gate layer is thin, the gate layer may penetrate through the gate layer, and even the wrong connection between different gate layers may be caused, which affects the device performance. This is because, usually, the lower surface of the dielectric layer is in contact with the step structure, and the upper surface of the dielectric layer is flush, that is, the dielectric layer is thinner at a position where the step surface of the step structure is far away from the substrate, and the depth of the formed step contact hole is smaller, and the dielectric layer is thicker at a position where the step surface of the step structure is near the substrate, and the depth of the formed step contact hole is larger, as shown in fig. 1, referring to a structural schematic diagram of a current 3D NAND memory device, the gate layer 1103 is in contact with the step contact hole 201 to achieve the leading-out of the gate layer 1103.
Under the condition that etching of step contact holes at different positions is carried out simultaneously, a dielectric layer (shallow hole) at a position, far away from a substrate, of a step surface is etched in advance, damage to a step structure, especially a gate layer, can be caused in the thickness etching process, as shown in fig. 2, even gate layer through etching (punch through) is caused in the etching process, the bottom surface of a subsequently filled conductive material is lower than the lower surface (reference area in an elliptical ring) of the gate layer, and if the etching time is reduced for protecting the upper gate layer, incomplete etching (under etch) can be caused on the dielectric layer (deep hole) at a position, close to the substrate, of the step surface, so that the gate layer cannot be effectively exposed to realize smooth leading-out of the gate layer.
In view of the above technical problems, embodiments of the present application provide a 3D NAND memory device and a method for manufacturing the same, which may include providing a substrate, forming a stack layer in which insulating layers and gate layers are alternately stacked on the substrate, wherein sidewalls of the stack layer have a step structure, and a first dielectric layer and a second dielectric layer are sequentially formed on the step structure, an upper surface of the first dielectric layer is disposed along the step structure, and an upper surface of the second dielectric layer is along a substrate plane direction, such that thicknesses of the first dielectric layer at different positions are substantially the same, and thicknesses of the second dielectric layer are different, etching the second dielectric layer at the step structure to form a step contact opening using the first dielectric layer as an etch stop layer, such that the etching of the second dielectric layer at each position is sufficient without damaging the gate layer below, the first dielectric layer at the bottom of the step contact opening can be etched, and the condition that the etching degrees of different positions are different due to the fact that the thicknesses of the first dielectric layers are basically consistent does not exist, so that damage to the gate layer caused by excessive etching of the dielectric layer at the position, far away from the substrate, of the step surface can be avoided, or the gate layer is not exposed due to insufficient etching of the dielectric layer at the position, close to the substrate, of the step surface, and therefore reliable leading-out of the gate layer can be achieved.
In order to better understand the technical solution and technical effects of the present application, the following detailed description of specific embodiments will be made with reference to the flowchart 3 and the accompanying fig. 4-17.
Referring to fig. 3, a flow chart of a method for manufacturing a 3D NAND memory device according to an embodiment of the present application is provided, the method including the steps of:
s01, providing a substrate 100, on which a stacked layer 110 formed by alternately stacking an insulating layer 1102 and a gate layer 1103 is formed, a sidewall of the stacked layer 110 is a step structure 111, and the step structure 111 is sequentially formed with a first dielectric layer 122 and a second dielectric layer 130, as shown in fig. 4-13.
In the embodiment of the present application, the substrate 100 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like. In the present embodiment, the substrate 100 is a bulk silicon substrate.
The stack layer 110 may be formed on a well region (not shown) formed in the substrate 100. The stacked layer 110 is formed by alternately stacking the gate layer 1103 and the insulating layer 1102, and the sidewall of the stacked layer may be a step structure 111, and the step structure 111 is covered with the first dielectric layer 122 and the second dielectric layer 130 on the first dielectric layer 122.
Forming a stacked layer 110 in which an insulating layer 1102 and a gate layer 1103 are alternately stacked on a substrate 100, which may be specifically, forming a stacked layer 110 in which an insulating layer 1102 and a sacrificial layer 1101 are alternately stacked on a substrate 100, as shown with reference to fig. 4; forming a step structure 111 on the sidewall of the stack layer 110, as shown with reference to fig. 5; covering the first dielectric layer and the second dielectric layer 130 on the first dielectric layer on the step structure 111, as shown in fig. 6-12; the sacrificial layer 1101 is replaced with a gate layer 1103, as shown with reference to fig. 13.
Specifically, in the via etching of a channel hole in a direction perpendicular to the substrate, the sacrificial layer 1101 and the insulating layer 1102 have a dry etching selection ratio of almost 1: 1; when the sacrificial layer 1101 parallel to the substrate 100 is replaced with the gate layer 1103, the sacrificial layer 1101 and the insulating layer 1102 have a high wet etching selectivity, which may be 30:1 or even higher, for example, and the number of layers of the stacked layer 110 may be determined according to specific needs. In this embodiment, the sacrificial layer 1101 may be, for example, silicon nitride (Si)3N4) The insulating layer 1102 can be, for example, silicon oxide (SiO)2) The gate layer 1103 may be tungsten (W) metal.
The stack layer 110 includes a core storage region and a step region, the core storage region is usually in a middle region of the stack layer 110 and is used for forming a memory cell string, the step region is usually around the core storage region and is used for Contact (Contact) of the gate layer 1103, steps on two sides of the core storage region in one direction may be used for forming a gate Contact, and steps in the other direction may not be used for forming a Contact and are dummy steps. Note that, in the drawings of the embodiments of the present application, only the step structure 111 on one side of the stack layer 110 is illustrated.
The step structure 111 may be a single step structure sequentially increasing in one direction in a plane in which the substrate is located, and the single step structure may be formed by an alternating trimming (Trim) of photoresist and a stack layer etching process; the step structure 111 may also be a Stage Divider Scheme (SDS), where the SDS is formed with steps in two orthogonal directions along a plane of the substrate, and the SDS may have different partitions, for example, 3 partitions, 4 partitions, or more partitions, for example, different partition plates may be used, and the SDS is formed by trimming the photoresist in the two orthogonal directions multiple times, and etching the stack layer is performed next to each trimming.
In the embodiment of the present application, one insulating layer 1102 and one sacrificial layer 1101 may form a composite layer, and a step structure 111 may be formed between adjacent composite layers. Specifically, the step surface of the step structure 111 may be the insulating layer 1102 or the sacrificial layer 1101, and the step surface will be described as the insulating layer 1102. A sacrificial layer 1102 may be provided as a protective layer on the uppermost layer of the step structure, and an insulating layer 1101 may be provided as an isolation layer on the lowermost layer of the step structure.
Thereafter, a first dielectric layer 122 may be formed on the step structure 111, and the first dielectric layer 122 may cover the step surface and the sidewall of the step structure 111, so as to protect the step structure 111, as shown in fig. 7. Specifically, the upper surface of the first dielectric layer 122 may follow the step structure, that is, the thickness of the first dielectric layer 122 at each step surface may be approximately uniform. The first dielectric layer 122 may be formed by a deposition process, such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or the like. In operation, the first dielectric material may be deposited first, and then the first dielectric material of the core storage region may be removed.
Before forming the first dielectric layer 122 on the step structure 111, a third dielectric layer 121 may be further formed on the step structure 111, where the third dielectric layer 121 has better step coverage to improve the filling capability of the first dielectric layer 122 and the second dielectric layer 130, as shown in fig. 6. Specifically, the third dielectric layer 121 may be HDP (High Density Plasma) silicon oxide or ALD (atomic layer deposition) silicon oxide.
After forming the first dielectric layer 122 on the step structure 111, a second dielectric layer 130 may be formed on the first dielectric layer 122, the second dielectric layer 130 may cover the step structure 111, and an upper surface of the second dielectric layer 130 is along a substrate plane direction, as shown in fig. 8 to 11. In addition, second dielectric layer 130 may cover both the core storage region and the stepped region of stack layer 110 such that the stepped region is substantially flush with the upper surface of the core storage region. The second dielectric layer 130 may be TEOS-based silicon oxide (TEOS-based SiO)2) And the like,the forming speed is high, and the filling of the step structure can be rapidly carried out. The first dielectric layer 122 is a material having a high etching selectivity with respect to the second dielectric layer 130, and when the second dielectric layer 130 is a silicon oxide layer, the first dielectric layer 122 may be silicon nitride.
In operation, the second dielectric material 130' may be deposited first, as shown with reference to FIG. 8; the second dielectric material 130 'of the core storage region is then removed, and the first dielectric layer of the core storage region may also be trimmed when the second dielectric material 130' of the core storage region is removed, as shown with reference to FIG. 9; the stepped region of the second dielectric material 130' may then be planarized such that the stepped region is flush with the core storage region, and with reference to fig. 10, a portion of the first dielectric layer may be removed during planarization; then, processing the core memory area, specifically, removing the top sacrificial layer of the core memory area and the insulating layer under the top sacrificial layer, as shown in fig. 11; a second dielectric material may then be deposited and planarized to form a second dielectric layer 130 that covers both the core storage region and the plateau region of stack 110, as shown with reference to fig. 12.
The processing of the core storage area may further include forming a memory cell string in the core storage area, where the memory cell string is a memory cell layer along a direction perpendicular to the substrate, and each layer of the gate layer 1103 and the memory cell string form one memory cell. The memory cell string comprises a memory function layer and a channel layer which are sequentially formed in a channel hole, the memory function layer plays a role in charge storage, and comprises a barrier layer, a charge storage layer and a Tunneling (Tunneling) layer memory function layer which are sequentially stacked, the channel layer is formed on the side wall of the memory function layer and the bottom of the channel hole and is in contact with an epitaxial structure at the bottom of the channel hole, and a filling layer made of an insulating material can be further formed between the channel layers.
After the step structure is covered by the second dielectric layer 130, the sacrificial layer 1101 may be removed to obtain a gate gap, and a conductive material is filled in the gate gap to obtain a gate layer 1103, as shown in fig. 13, where the material of the gate layer may be tungsten or the like.
S02, using the first dielectric layer 122 as an etching stop layer, the second dielectric layer 130 is etched at the step structure 111 to form a step contact opening 131', as shown in fig. 14.
After forming the first dielectric layer 122 and the second dielectric layer 130 on the step structure, the first dielectric layer 122 may be used as an etching stop layer to etch the second dielectric layer 130 at the step structure 111 to form a step contact opening 131 ', and the step contact opening 131' is aligned with the step surface of the step structure 111, as shown in fig. 14. For example, RIE etching method can be used, and the etching gas can include C4F8/C4F6Or a mixture of any one or more of them.
This is because the upper surface of the second dielectric layer 130 is substantially parallel to the plane of the substrate 100, so that the thicknesses of the second dielectric layer 130 at different positions are different, and the thickness of the second dielectric layer 130 is smaller in the region where the step surface of the step structure 111 is far from the substrate, and the depth of the step contact opening 131 'formed by etching is smaller, and in the region where the step surface of the step structure 111 is close to the substrate, the thickness of the second dielectric layer 130 is larger and the depth of the step contact opening 131' formed by etching is larger, so that there is a difference in etching time, that is, when the shallow hole has been completely etched, the deep hole is only partially etched, so if there is no first dielectric layer 122 as an etching stop layer, and the gate layer 1103 as an etching stop layer, after the second dielectric layer 122 at the shallow hole is completely etched, the gate layer 1103 is damaged, and there is a possibility that the gate layer 1103 is etched through. When the second dielectric layer 130 is etched by using the first dielectric layer 122 as an etching stop layer, the gate layer 1103 will not be affected even if the first dielectric layer 122 is damaged at the shallow hole.
S03, the first dielectric layer 122 at the bottom of the step contact opening 131' is etched to form a step contact hole 131 penetrating to the step structure 111, as shown in fig. 15-17.
After the second dielectric layer 130 is etched to form the step contact opening 131 ', the first dielectric layer 122 at the bottom of the step contact opening 131' may be etched to form the step contact hole 131 penetrating to the step structure 111. When the step surface of the step structure 111 is the gate layer 1103, the first dielectric layer 122 may be etched to form a step contact hole 131 exposing the gate layer 1103, and when the step surface of the step structure 111 is the insulating layer 1102, the first dielectric layer 122 and the insulating layer 1102 may be etched to form the step contact hole 131 exposing the gate layer 1103.
When the third dielectric layer 121 is formed between the step structure 111 and the first dielectric layer 122, the first dielectric layer 122 at the bottom of the step contact opening 131 ' is etched, which may specifically be that the third dielectric layer 121 is used as an etching stop layer, the first dielectric layer 122 at the bottom of the step contact opening 131 ' is etched to deepen the step contact opening 131 ', as shown in fig. 15, and then the gate layer 1103 is used as an etching stop layer, the third dielectric layer 121, or the third dielectric layer 121 and the insulating layer 1102 are etched to form the step contact hole 131 penetrating to the step structure 111, as shown in fig. 16. Thus, the etching of the stepped contact hole 131 can be divided into a plurality of steps, the first step has less damage to the first dielectric layer 122 in the step of etching the second dielectric layer 130, thereby reducing the etching difference of the contact holes 131 with different steps, reducing the damage to the third dielectric layer 121 in the second step of etching the first dielectric layer 122, further reducing the etching difference of the contact holes 131 with different steps, reducing the damage to the gate layer 1103 in the third step of etching the third dielectric layer 121 and the insulating layer 1102, so that the etching of the dielectric layer at each position is sufficient without damaging the underlying gate layer 1103, thereby avoiding the damage to the gate layer 1103 caused by excessive etching of the dielectric layer at a position far away from the substrate 100, or the gate layer 1103 is not exposed due to insufficient etching of the dielectric layer at a position close to the substrate 100, so that reliable extraction of the gate layer 1103 can be realized.
Then, step contact hole 131 filling may be performed, and step contact portion 132 is formed in step contact hole 131, as shown with reference to fig. 17. Specifically, the step contact hole 131 may be filled with a conductor material, followed by planarization to remove the conductor material outside the step contact hole 131, thereby forming the step contact portion 132 formed only in the step contact hole 131. Referring to fig. 18, the step contact hole 131 preferably stops on the gate layer, and thus the bottom of the step contact portion 132 is preferably combined with the gate layer, thereby providing reliable gate lead-out.
And finally, finishing other processing processes of the device, and further forming interconnection structures such as word lines, bit lines and the like.
The embodiment of the application provides a manufacturing method of a 3D NAND memory device, which can comprise the steps of providing a substrate, forming a stacked layer on the substrate, wherein the stacked layer is formed by alternately stacking insulating layers and gate layers, the side wall of the stacked layer is of a step structure, sequentially forming a first dielectric layer and a second dielectric layer on the step structure, the upper surface of the first dielectric layer is arranged along the step structure, and the upper surface of the second dielectric layer is arranged along the plane direction of the substrate, so that the thicknesses of the first dielectric layers at different positions are basically consistent, the thicknesses of the second dielectric layers are different, etching the second dielectric layer at the step structure by taking the first dielectric layer as an etching stop layer to form a step contact opening, and because the thicknesses of the second dielectric layers at all steps are different, the first dielectric layer as the etching stop layer can enable the etching of the second dielectric layers at all positions to be sufficient without damaging the gate layers below, the first dielectric layer at the bottom of the step contact opening can be etched, and the condition that the etching degrees of different positions are different due to the fact that the thicknesses of the first dielectric layers are basically consistent does not exist, so that damage to the gate layer caused by excessive etching of the dielectric layer at the position, far away from the substrate, of the step surface can be avoided, or the gate layer is not exposed due to insufficient etching of the dielectric layer at the position, close to the substrate, of the step surface, and therefore reliable leading-out of the gate layer can be achieved.
Based on the above manufacturing method of the 3D NAND memory device, an embodiment of the present application also provides a 3D NAND memory device, shown with reference to fig. 11, including:
a substrate;
the insulating layers and the grid electrode layers on the substrate are stacked alternately, and the side wall of the stacked layer is of a step structure; the step structure is sequentially provided with a first medium layer, a second medium layer and a step contact part penetrating through the first medium layer and the second medium layer, the upper surface of the first medium layer is along the step structure, and the upper surface of the second medium layer is along the plane direction of the substrate.
Optionally, the first dielectric layer is silicon nitride, and the second dielectric layer is silicon oxide.
Optionally, the second dielectric layer is silicon oxide based on TEOS.
Optionally, the step structure further includes a third dielectric layer between the step structure and the first dielectric layer, and the step contact portion penetrates through the third dielectric layer.
Optionally, the third dielectric layer is high-density plasma silicon oxide or atomic layer deposition silicon oxide.
The embodiment of the application provides a 3D NAND memory device, which comprises a substrate, wherein a stacked layer formed by alternately stacking insulating layers and gate layers is formed on the substrate, the side wall of the stacked layer is of a step structure, a first dielectric layer, a second dielectric layer and a step contact part penetrating through the first dielectric layer and the second dielectric layer are sequentially formed on the step structure, the upper surface of the first dielectric layer is arranged along the step structure, and the upper surface of the second dielectric layer is arranged along the plane direction of the substrate, so that the thicknesses of the first dielectric layers at different positions are basically consistent, the thicknesses of the second dielectric layers are different, the etching of the second dielectric layers at each position can be sufficient, the gate layers below are not damaged, the condition that the etching degrees of different positions are different due to the inconsistent etching thickness of the first dielectric layers is avoided, and the damage to the gate layers caused by excessive etching of the step surfaces at the positions far away from the substrate can be avoided, or the gate layer is not exposed due to insufficient etching of the dielectric layer at the position of the step surface close to the substrate, so that reliable extraction of the gate layer can be realized.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the memory device embodiments, since they are substantially similar to the method embodiments, they are described relatively simply, and reference may be made to some of the descriptions of the method embodiments for their relevance.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (10)
1. A method of manufacturing a 3D NAND memory device, comprising:
providing a substrate; a stacked layer formed by alternately stacking insulating layers and gate electrode layers is formed on the substrate, and the side wall of the stacked layer is of a step structure; a first dielectric layer and a second dielectric layer are sequentially formed on the step structure, the upper surface of the first dielectric layer is along the step structure, and the upper surface of the second dielectric layer is along the plane direction of the substrate;
etching the second dielectric layer at the step structure by taking the first dielectric layer as an etching stop layer to form a step contact opening;
and etching the first dielectric layer at the bottom of the step contact opening to form a step contact hole penetrating to the step structure.
2. The method of claim 1, wherein the first dielectric layer is silicon nitride and the second dielectric layer is silicon oxide.
3. The method of claim 2, wherein the second dielectric layer is a TEOS based silicon oxide.
4. The method of claim 1, further comprising a third dielectric layer between the step structure and the first dielectric layer, wherein etching the first dielectric layer at the bottom of the step contact opening to form a step contact hole penetrating to the step structure comprises:
etching the first dielectric layer at the bottom of the step contact opening by taking the third dielectric layer as an etching stop layer so as to deepen the step contact opening;
and etching the third dielectric layer or the third dielectric layer and the insulating layer by taking the gate layer as an etching stop layer to form a step contact hole penetrating through the step structure.
5. The method of claim 4, wherein the third dielectric layer is high density plasma silicon oxide or atomic layer deposition silicon oxide.
6. The method of any of claims 1-5, further comprising, after forming the step contact hole:
and forming a step contact portion in the step contact hole.
7. A 3D NAND memory device, comprising:
a substrate;
the insulating layers and the grid electrode layers on the substrate are stacked alternately, and the side wall of the stacked layer is of a step structure; the step structure is sequentially provided with a first medium layer, a second medium layer and a step contact part penetrating through the first medium layer and the second medium layer, the upper surface of the first medium layer is along the step structure, and the upper surface of the second medium layer is along the plane direction of the substrate.
8. The memory device of claim 7, wherein the first dielectric layer is silicon nitride and the second dielectric layer is silicon oxide.
9. The memory device of claim 7, further comprising a third dielectric layer between the stair step structure and the first dielectric layer, the stair step contact extending through the third dielectric layer.
10. The memory device of claim 9, wherein the third dielectric layer is a high density plasma silicon oxide or an atomic layer deposition silicon oxide.
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