GB2302987A - Method for analyzing failure in semiconductor device - Google Patents

Description

14ZTROD rOR AIMYZING FAILURE IN SEMICONDUCTOR DEVICE 2302987 The present

invention relates to a method for analyzing a failure occurring in a semiconductor device during its manufacture, and, more particularly, to a deprocessing method for exposing a polysilicon contact in a semiconductor device for the purpose of confirming a failure due to an open-contact occurring in the polysilicon contact.

As a result of the large increase in the integration of components in semiconductor devices, the structure of the elements formed in semiconductor devices has become three- dimensionally very complicated, particularly in obtaining sufficient capacitance in a limited volume. These structures require high-level deprocessing techniques in order to expose failures that occur in a stacked structure, which is necessary to provide the high level of integration required.

In a previously proposed technique employed for the purpose of analyzing an open circuit failure of a contact in a polysilicon layer of a semiconductor device, a sample is fabricated and sectioned, in order that it may thereby be observed. However, this method, which involves making a section in order to observe the failure, has the problem that it is difficult in making the section to approach the failure site, because the polysilicon layers are covered by overlayers such as metal and oxide passivation layers etc., and because the area in which the failure has occurred and can be analyzed is very small.

In the case of contact failure analysis, there has previously been proposed a deprocessing method, in which stacked layers are sequentially removed, starting from the top layer, the failure sites of the layers being sequentially observed. In this method a polysilicon layer which comes into contact with a silicon substrate is etched, and then pits, generated in the substrate, are observed, thereby enabling it to be confirmed whether the contact is open or not. However, it is not possible with this method to observe directly whether the contact is open or not. Also, the contact pits are enlarged more than their actual size during the etch of the polysilicon layer, as will be seen from Fig. 1 of the accompanying drawings. Accordingly, it is difficult to confirm the actual contact size and the aligned contact location. Furthermore, in the analysis of a failing mechanism, which can be produced in an identical failure mode, the analysis procedure cannot be carried out correlatedly. A feature of a deprocessing method for analyzing a polysilicon open-contact failure in a semiconductor device, to be described below, by way of example, is that it is capable of detecting more precisely than by previously proposed methods whether a polysilicon contact 5 is open or not, and of establishing its location.

A particular deprocessing method for analyzing a polysilicon contact open circuit failure in a semiconductor device to be described belowe by way of example, includes the steps of removing a passivation layer and a double metal layer placed on a wafer having a memory cell thereon, selectively removing the upper portions of polysilicon material forming a capacitor and polysilicon material forming a bit line employing a dry plasma etch, and carrying out a wet etch using an etchant including HF to expose a field oxide layer, and to leave the lower portions of the polysilicon layer forming the bit line, and a polysilicon layer forming a capacitor storage node on the wafer.

A previously proposed method will now be illustrated, and a method, given by way of example, and illustrative of the present invention will be described with reference to the accompanying drawings, in which:- Fig. 1 is a micrograph illustrating a sample obtained for use in analyzing a polysilicon contact open failure in a semiconductor device by means of the previously proposed technique mentioned above and showing a trace of a polysilicon contact, Figs. 2A and 2B are cross-sectional views showing a deprocessing method illustrative of the present invention, and 5 Fig. 3 is a micrograph showing a plan view of a sample in which a deprocessing method illustrative of the present invention has been carried out. Referring to Figs. 2A and 2B there are shown crosssectional views illustrating a deprocessing procedure for analyzing a failure in a capacitor contact and a bit line contact of a semiconductor device. Fig. 2A shows a structure formed in a manner suitable for making a DRAM, and having had its passivation layer and metal layer removed by means of a previously proposed deprocessing method, in order to form a failure analyzing sample. In. this figure, reference numeral 21 designates a silicon substrate 22 a field oxide layer, 23 a gate oxide layer, 24 a polysilicon layer for forming a gate electrode, 25 an insulating layer spacer, 26 source and drain regions,

27 a first interlevel insulating layer, 28 a polysilicon layer for forming a bit line, 29 a second interlevel insulating layer, 30 a polysilicon layer for forming a capacitor storage node, 31 a capacitor dielectric layer, and 32 a polysilicon layer for forming a capacitor plate electrode, respectively. As shown in Fig. 2A, the polysilicon layer 28 and the polysilicon layer 30 come into contact with source and drain regions 26 of the silicon substrate 21.

Then, as shown in Fig. 2B, the upper portions of a polysilicon layer forming wings (a) (shown in Fig. 2A) of the capacitor, and the bit line polysilicon layer 28 are selectively etched by means of a plasma dry etch using CF4 and 02 in an RIE(Reactive Ion Etcher). Thereafter, a wet etchis carried out using an etchant containing about 49% HF to expose the field oxide layer, and to leave the lower portion (28a) of the bit line polysilicon layer 28 and the storage node 30a of the polysilicon layer 30 on the silicon substrate 21. By doing so, the polysilicon remnant 28a, 30a is left on the contact region of the substrate 21.

The arrangement shown in Fig. 2B enables the failure in the polysilicon contact to be confirmed by observing the structure of Fig. 2B. That is, it is possible easily to analyze the degree of contact'superposition, and to confirm whether the contact is open or not by observing the polysilicon remnant left on the contact region. Also, it is possible to analyze the failure mechanism produced in the substrate. Fig. 3 is a micrograph illustrative of the present invention and showing a sample in which a storage node contact is exposed. The bottom of the charge storage electrode contact and of the bit line are shown. By means of the disclosure provided by the method described, it is possible to confirm precisely the location of the contact as well as to - 6 measure Its size, as is clear from the illustration. Although the method has been Illustrated by reference to a particular arrangementi by way of example. it will be understood that variations and modifications thereof# as well as other methods may be employed within the scope of the protection sought by the appended claims.

Claims (4)

1. A deprocessing method for analyzing a polysilicon contact open failure in a semiconductor device, said method comprising the steps of:

removing a passivation layer and double metal layer placed on a wafer, said wafer including a memory cell thereon; selectively removing the upper portions of a polysilicon forming a capacitor and polysilicon forming a bit line through plasma dry etch; and carrying out wet etch using an etchant including HF to expose a field oxide layer, and at the same time, to leave the lower portions of said polysilicon layer forming said bit line, and a polysilicon layer forming a capacitor storage node on said wafer.

2. The deprocessing method for analyzing a failure in a semiconductor device, wherein said plasma dry etch uses a gas containing at least CF4 and 02 as a source gas.

3. The deprocessing method for analyzing a failure in a semiconductor device, wherein said HF content of said etchant is about 49%.

4. A deprocessing method as claimed in claim I substantially as described herein with reference to Figs. 2A, 2B and 3 of the accompanying drawings.