Α7 Β7 經濟部中央標準局員工消費合作社印製 五、發明説明（ 1明範圍 本發明係相關於一方法，其用來分析半導體裝置在它的 形成過程中所產生的故障，且特定於一解處理方法，用來 暴露出半導體裝置的多晶矽接觸，目的在確認在多晶碎接 觸中所產生的接觸開路故障。 . 根據半導體裝置上大量增加的整合，形成半導體裝置的 元件結構·變成了三維.性的複雜度，以獲得在有限區域内的 足夠容量。這需要高水準的解處理技術來暴露出在造成高 度整合之半導體裝置的堆疊結構中所產生的故障。 在傳統技術中，爲了分析在半導體裝置的多晶矽接觸中 產生的接觸開路故障，會製造並分割一樣品？以便觀察。 然而，這種分割觀察法有以下的問題。也就是，很難去接 近故障點。因爲多晶矽層被如金屬及氧化保護層等等的覆 蛊層所覆蓋住，且被分析的故障面積很小。 因此，在接觸故障分析的情形下，使用解處理的方法， 〃中依序的彳文頂層開始移除堆疊層，而可以依序觀察到層 的故障點。這方法之架構方式爲把與矽基質接觸的多晶矽 層做蝕刻，接著觀察基質中產生的凹洞，藉之確認接觸是 否開路；而，這種方法並不能直接的觀察到接觸是否開 路了目爲與基負接觸之多晶矽層已完全被移除。同樣 也々圖I中所顯不的，在多晶矽層蝕刻期間，由於該多 晶矽層之移除所產生之接觸凹洞被擴大到超過它們實際的 大】因此，經由傳統（解處理方法，難以確認實際的接 觸大小與對齊的接觸位置。再者，這種傳統的解處理方法 CNsTa^S- ( 210 x 297^ I---------裝〆------ΐτ------.^ (請先閲讀背面之注意事is.l .^'«)本頁) 一 A7 B7 故障模式 318S5〇 五、發明説明（ 1 & 即爲每一個分析程序不能有效地使用在相同之 發明概要 - 本毛明之目的在提供一解處理方法，來分析半導體裝置 中的多晶矽的接觸開路故障，其可以準確的偵測出多晶矽 接觸是否開路了，以.及分析出它的對齊位置。 若要達到本發明的這個目的，提供一種方法來分析在半 料裝£之接觸區域中的故障’纟中該半導體裝置包括一 與基只接觸之導電層，—圍繞該導電看之下層部分的絕緣 2 ’及—覆蓋該導電層及該絕緣層之較上層·，且其中該導 電層之―較上方的部分，在該絕緣層之上表面作延伸，该 、匕括步展有·去除該導電層之較上方部分，留下該絕 緣層，與該基質接觸之該導電層之較下方部分；同時以灌 :刻劑’蝕刻該絕緣層及該導電層之較下方部分，直至基 質暴露’丨中該独刻劑對該絕緣層具有—較高的選擇择 =速率’所以該導電層之殘留物形成於該接觸區域，.真 覜察該導電層之該殘留物以分析一接觸故障。 要説明 - 一本《明特徵所堅信的新奇特性，如同其他的特性與優點 樣可I皆由參考下列與附圖一起讀取之特定具體實例以 詳細描述獲得最好的理解，其中： 圖1是—顯微圖片，顯示根據傳統技術來分析半 本紙張尺度適( CNS ) 裝，ir# (靖先閱讀背面之注意事項一本頁) 〆 經濟部中央標準局員工消費合作社印製 經濟部中央標準局員工消費合作社印裳 五、發明説明（3 ) 置中多晶矽接觸開路故障的樣品； 圖2A及2D是-剖面圖觀點，顯示根據本發明的具體實例 的解處理方法；及 圖3是一顯微圖片，顯示一樣品的平面觀點，其中實現 根據本發明的解處理。 . 鼓進具體實例的詳細部日Η 卜 本發明的較佳具體實例會在下面參考附圖加以解釋。 圖2Α至2D爲剖面圖觀點，顯示一用來分析半導體裝置的 電容器接觸及位元線接觸中之故障的解處理程序。圖2Α及 顯示製造DRAM方式的形成結構，接著以傳統技術方㈣ 除其保護層及金屬以便形成—故障分析樣品。在此圖 示中，個別的，參考號碼21標記矽基質，22爲一場氧化 層，23爲—閘極氧化層’ 24爲一閘電極，乃爲 '絕緣層間 隔，26爲源極與汲極區域，27爲_第—中間層絕緣層，μ 爲一位元線，29爲一第二中間層絕緣層，3〇爲—電荷儲存 電接’ 31爲-介電質層，及32爲—平板電極。如圖从中所 顯示，.多晶矽層28及多晶矽層30，會與形成於矽基質以中 的源.極與汲極區域26接觸。 首先，本發明之解處理方法，去除在多晶矽層32上之較 上層，暴露出平板電極3 2及位於平板電極3 2和位元線2 8 間之第二中間絕緣層29之一部分。在—根據本發明之較佳 實施例中，該電荷儲存電極32及平板電極3〇由多晶矽層 製成，且第一及第二中間層絕緣層2 7及2 9由矽氧化層 ______ -6- 本紙張尺度適用中國國家襟準（CNS ) A4規格（210X297公釐） ^— (請先閱讀背面之注意事反 i.k本頁)·Α7 Β7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (1. Scope of the invention The present invention is related to a method, which is used to analyze the failures of semiconductor devices during its formation, and is specific to a solution The processing method is used to expose the polysilicon contacts of the semiconductor device. The purpose is to confirm the open contact failures generated in the polycrystalline broken contacts. According to the increased integration of the semiconductor device, the structure of the element forming the semiconductor device has become three-dimensional. Complexity to obtain sufficient capacity in a limited area. This requires a high level of solution processing technology to expose the failures that occur in the stacked structure of highly integrated semiconductor devices. In traditional technology, in order to analyze the Open contact faults generated in the polysilicon contact of semiconductor devices, will a sample be manufactured and divided? For observation. However, this segmented observation method has the following problems. That is, it is difficult to approach the fault point. Because the polysilicon layer is made of metal And the protective coating layer, such as the oxidation protection layer, is covered and analyzed The product is very small. Therefore, in the case of contact failure analysis, using the solution processing method, the top layer of the text in order begins to remove the stacked layers, and the layer failure points can be observed in sequence. The architectural way of this method In order to etch the polysilicon layer in contact with the silicon substrate, and then observe the cavity formed in the substrate to confirm whether the contact is open; however, this method cannot directly observe whether the contact is open. The polysilicon layer has been completely removed. Also, as shown in Figure I, during the etching of the polysilicon layer, the contact holes created by the removal of the polysilicon layer were enlarged to exceed their actual size] Therefore, via Traditional (solution processing method, it is difficult to confirm the actual contact size and aligned contact position. Furthermore, this traditional solution processing method CNsTa ^ S- (210 x 297 ^ I --------- 装 〆- ----- Ιτ ------. ^ (please read the notes on the back is.l. ^ '«) first page) A7 B7 Failure Mode 318S5〇 5. Description of invention (1 & Each analysis program cannot be effectively used in the same summary of invention -The purpose of this Maoming is to provide a solution to analyze the open contact failure of polysilicon in semiconductor devices, which can accurately detect whether the polysilicon contact is open, and analyze its alignment position. To achieve The object of the present invention is to provide a method to analyze faults in the contact area of a half-pack. The semiconductor device includes a conductive layer that is only in contact with the substrate,-the insulation of the underlying layer around the conductive layer 2 ' And-covering the upper layer of the conductive layer and the insulating layer, and wherein the upper part of the conductive layer extends on the upper surface of the insulating layer, and the step is to remove the conductive layer The upper part, leaving the insulating layer, the lower part of the conductive layer in contact with the substrate; at the same time with potting: Etching 'etching the insulating layer and the lower part of the conductive layer until the substrate is exposed' The engraving agent has a relatively high selectivity = rate for the insulating layer, so the residue of the conductive layer is formed in the contact area. Really look at the residue of the conductive layer to analyze a Touch fault. To explain-a novel feature that "Bright Features firmly believes, like other features and advantages, can be best understood by referring to the following specific specific examples read with the drawings for a detailed description, in which: Figure 1 Yes—micrograph showing the analysis of half-size paper (CNS) packs according to traditional techniques, ir # (Jingxian read the notes on the back page of this page) 〆 Printed by the Ministry of Economic Affairs Central Bureau of Standards Employees Consumer Cooperative Printed by the Ministry of Economic Affairs Printed by the Bureau of Standards and Staff Consumer Cooperative V. Description of the invention (3) Centering the sample of the polysilicon contact open circuit failure; Figures 2A and 2D are cross-sectional views, showing the solution processing method according to the specific example of the present invention; and Figure 3 is a Micrograph showing a planar view of a sample in which the solution processing according to the invention is realized. .Details of the specific examples of drumming. The preferred specific examples of the present invention will be explained below with reference to the drawings. Figs. 2A to 2D are cross-sectional views showing a solution processing procedure for analyzing a fault in a capacitor contact and a bit line contact of a semiconductor device. Figure 2Α and shows the formation structure of the DRAM manufacturing method, and then remove its protective layer and metal by conventional techniques to form-failure analysis samples. In this figure, individually, the reference number 21 marks the silicon substrate, 22 is a field oxide layer, 23 is a gate oxide layer, 24 is a gate electrode, which is the insulating layer interval, and 26 is the source and drain. Region, 27 is the first interlayer insulating layer, μ is a bit line, 29 is a second interlayer insulating layer, 30 is the charge storage electrical connection, 31 is the dielectric layer, and 32 is the Flat electrode. As shown in the figure, the polysilicon layer 28 and the polysilicon layer 30 will be in contact with the source and drain regions 26 formed in the silicon matrix. First, the solution processing method of the present invention removes the upper layer on the polysilicon layer 32, exposing the plate electrode 32 and a part of the second intermediate insulating layer 29 between the plate electrode 32 and the bit line 28. In a preferred embodiment according to the present invention, the charge storage electrode 32 and the plate electrode 30 are made of polysilicon layer, and the first and second intermediate insulating layers 27 and 29 are made of silicon oxide layer 6- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ^ — (please read the notes on the back of this page first)
*1T 線 經濟部中夬榡準局負工消費合作社印製 五、發明説明（ 成。 接著下來，如圖2B所示，依序移除該平板電極32，該 ;|电層3 1及該第二中間層絕緣層2 9。此時，乃利用稀釋 t氣化氫（HF)溶液移除該第二中間層絕緣層29，該氣化 氯洛液對於矽氧化層而言，有一高選擇性蝕刻速率。 如圖2 C所示，在移除該第二中間層絕緣層2 9之後，在 RIE(Ilea_ctive I〇n Etchiivg)密閉室中，藉由使用匸匕 及0 2之電漿蝕刻方法，選擇性地移除，該電荷儲存電極 3 〇之鳍狀結構（如圖2B之"a"所示）及位元線28。在根據本 發明之較佳.'實施例中，藉由C L : I爲丨〇 : 2之蝕刻氣 ’钱刻該鰭狀結構中之多晶矽；對於該多晶矽層3 〇之選 擇性蚀刻速率，大約爲對於該矽氧化層的數十倍；結果， 孩多晶矽層3 〇及該第一中間層絕緣層2 7可以暴露於，以 相同方式拓撲而實施之伴隨的解處理所用之下述蝕刻劑。 最後’如圖2 D所示，藉由使用4 9 〇4之氟化氫溶液，施 行渔姓刻程序於電荷儲存電極3 〇及第一矽氧化層2 7，直 到暴露出矽基質，而產生一觀察用之樣品，在此時，該氟 化氫溶，液對於由矽氧化物製成之第一中間層絕緣層2 7，具 有一.高選擇性蝕刻速率，且該氟化氫溶液同樣對該第一中 間屬絕緣層2 7，即使該層很小，有著該選擇性蝕刻速率； 另一方面’該閘氧化層之移除，導致能移除閘電極2 4之舉 升程序°由於此溼蚀劑形成了該電荷儲存電極3 0之;殘留物 於接觸區域上，所以該實際接觸可以被精確地觀察。 結果’本發明藉由觀察圖2D的結構，來確認多晶矽接觸 各纸狀度適用中國國家縣（CNS〉A4規格（21Qx 297公疫） — 拉衣 、1τ------線 (請先閱讀背面之注意事項ί 弯本頁) < 、 A7 A7 五、 發明説明（ 勺故障。也就是説，可以輕易的分析出接觸疊加的等 、’'’以及藉由觀察留在接觸區域的多晶矽殘留物，來確認 接觸是否開路。同樣地，可以分析產生在基質中的故障結 =。圖3是一顯微圖片，顯示一樣品，其中根據本發明暴 出儲存節點的接觸。如圖3所顯示的，可以精確地確認 出接觸的位置，以及測量它的大小。 〜因此，應理解到，.本發明並不限制在這裡所揭示爲考量 、本發月的最佳模式之特定具體實例，但除了接下來的 申請專利範圍所定義的以外，本發明並不限制在本説明書 中所描述的特定具體實例。. ---------t-- (請先閲讀背面之注意事反 VW本頁) 線 經濟部中央標準局員工消費合作社印製 Μ氏張尺度適财_家縣（CNS ) Λ4規格（2iqx 297公瘦）* 1T Printed by the Ministry of Economic Affairs of the Ministry of Economic Affairs, Central Bureau of Preservation and Consumer Cooperatives 5. Description of the invention (completed. Next, as shown in FIG. 2B, remove the flat electrode 32 in sequence, the; | electric layer 3 1 and the The second interlayer insulating layer 29. At this time, the second interlayer insulating layer 29 is removed by using a diluted t gasified hydrogen (HF) solution, and the vaporized clorol solution has a high choice for the silicon oxide layer As shown in FIG. 2C, after removing the second interlayer insulating layer 29, in a sealed chamber of RIE (Ilea_ctive I〇n Etchiivg), the plasma etching using a dagger and 0 2 Method, selective removal, the fin-like structure of the charge storage electrode 30 (as shown in " a " of FIG. 2B) and the bit line 28. In the preferred embodiment according to the present invention. From CL: I is an etching gas of 〇〇: 2 to engrave polysilicon in the fin structure; the selective etching rate for the polysilicon layer 30 is about tens of times that for the silicon oxide layer; as a result, The polysilicon layer 30 and the first interlayer insulating layer 27 can be exposed to the concomitant implementation of the topology in the same way The following etchant used in the treatment. Finally, as shown in FIG. 2D, by using a hydrogen fluoride solution of 4 9 〇4, the fish etching process is performed on the charge storage electrode 30 and the first silicon oxide layer 27 until exposed A silicon matrix is produced and a sample for observation is produced. At this time, the hydrogen fluoride is dissolved, and the liquid has a high selective etching rate for the first interlayer insulating layer 27 made of silicon oxide. The hydrogen fluoride The solution also has a selective etching rate for the first intermediate insulating layer 27, even if the layer is small; on the other hand, the removal of the gate oxide layer results in a lifting procedure that can remove the gate electrode 24 ° Since this wet etchant forms the charge storage electrode 30; the residue is on the contact area, so the actual contact can be accurately observed. Results' The present invention confirmed the polysilicon contact by observing the structure of FIG. 2D The paper degree is applicable to China's national counties (CNS> A4 specifications (21Qx 297 epidemic)-pull-up, 1τ ------ line (please read the precautions on the back first) Bend this page) <, A7 A7 V. Description of invention (Spoon failure. That is to say, may Easily analyze the contact superposition, '', and confirm whether the contact is open by observing the polysilicon residue left in the contact area. Similarly, the fault junction generated in the matrix can be analyzed =. Figure 3 is a significant The micro picture shows a sample in which the contact of the storage node is exposed according to the present invention. As shown in FIG. 3, the position of the contact can be accurately confirmed and its size can be measured. ~ Therefore, it should be understood that the present invention It is not limited to the specific specific examples disclosed here for consideration and the best mode of this month, but the invention is not limited to the specific specifics described in this specification except as defined by the scope of the subsequent patent application Examples. . --------- t-- (please read the notes on the back of the VW page first) The Ministry of Economic Affairs Central Standards Bureau employee consumer cooperatives printed M's Zhang scale suitable money_ 家 县 （CNS） Λ4 Specifications (2iqx 297 male thin)