TWI220548B - Method for detecting defect of semiconductor device - Google Patents

Abstract

A method for detecting defect of semiconductor device is provided. The semiconductor device is consisted of substrate, gate, plug, insulating layer and conductive layer, wherein the plug connects the source/drain region in the substrate beside the gate electrically and covers over a part of gate. A defect is found between the plug and the gate. First, a polishing step is performed for polishing the semiconductor device until the plug didn't covers over a part of gate. Then a clean step is performed for cleaning the semiconductor device. After the insulating layer between the plug and the gate is removed, a detecting step is performed for detecting the defect between the plug and the gate.

Description

1220548

V. Description of the invention (l) The technical field to which Deng J belongs The present invention relates to a semiconductor element. It relates to a method and a method for detecting a semiconductor element defect, and in particular iJLiOs: Go. The so-called integrated circuit is to reduce and produce a specific circuit ^ circuit to a size of only 2 cm or various components and electronic products required. Because integrated circuits are mostly solid-state electronic components that can be viewed by a microscope over an area of 3 / ^, the size needs to be called a microelectronic component. The above-mentioned microelectronics—, β ’s, if there is a defect in the device, will cause this microelectronic device to be rectified: and when the semiconductor design specification is reduced, the electronic device will fail. Cheng Yi's rate is more difficult 'and Defect is the key point of the' m system '. Therefore, the identification and analysis of defects: Yiyi has a significant relationship with the improvement of circuit manufacturing yield ^ and the reduction of 'integral method = second measurement of defects in semiconductor components, using the order of engraving: division Each layer on the semiconductor element and sequentially analyzes each layer μ That is, when performing defect detection of semiconductor elements, it is performed from the upper layer according to its ^ 4tier by layer #, and the underlying layers are layered. The knife layer exits, and the observation and analysis of each layer are performed until the bottom layer is reached. With the increase in the degree of semiconductor accumulation, it will be more difficult to use the above method to detect: analysis of semiconductor device defects, especially for defects such as short-circuiting of the gate and plug caused by the previous process). This is because the application of the above-mentioned detection methods requires layer-by-layer corrosion »Ο

1220548

V. Description of the invention (2) It takes time to produce the defects until the defects are exposed in a long process, and the defects or contents are actually detected. In addition, such square ill grains also have the disadvantage of being moved particles due to > § insect engraving. In the test method for exposing defects, it is impossible to be sure when performing the wet-type surrogation. In view of this, one object of the present invention is to provide a semiconductor detection method that can detect defects quickly and accurately. The invention provides a method for detecting a semiconductor element defect. The semiconductor device is at least composed of a substrate, a gate, a plug, an insulating layer, and a wire. The plug electrically connects the source in the substrate on both sides of the gate. The pole / drain region 2 is above the gate, and there is a defect between the plug and the gate. This is a grinding step to at least grind the semiconductor device until the plug does not cover the second pole. Then, a cleaning step is performed to clean the semiconductor device. After the insulating layer between the y-pole and the plug is moved, a defect between the plug and the gate is detected. In the method described above, the grinding step further includes grinding to approximately expose the gate. The washing step includes washing the semiconductor device with deionized water, and drying the rabbits. The steps of removing the insulating layer between the gate electrode and the plug include a ””, etch-off process, and a dry etching process.

The plug is not released, and the semiconductor element is ground directly to the plug insulation by grinding, covering the upper part of the gate electrode, and then removing the exact I, between the gate electrode and the plug, which can not only avoid defects due to wet etching. Removal allows you to pinpoint, detect defects, and saves time. The invention provides a semiconductor element defect detection method.

--- —I. V. Description of the invention (3) The body element includes at least " between adjacent conductor layers :: 目 Neighborhood :? Layer and an insulating layer. This insulating layer fills the gap. This method is based on a method in which two adjacent conductor layers have an exposed two conductor layer. Following the grinding step, the semiconductor element is ground to approximately a defect between the two conductor layers. The insulation layer between the two conductor layers is removed, and the insulation layer in the above method is detected. After the grinding step, the In addition to cleaning between the two conductor layers with deionized water, the following steps are performed: a cleaning step. This cleaning step is immediate. The method of insulating layer can be wet engraving or dry type. The present invention uses grinding to slightly expose the sound of the two conductors. In the style, the semiconductor element is directly ground to about but can avoid the lack of the insulating layer between the two conductor layers, which is not defective. Moreover, it can also save K from being removed, and can accurately detect the SS and make the above and other objectives of this Maoming #, features, and advantages 浐 -Β Β is easy to make M, the following is a better one A more detailed description is as follows: 1. Another example is Jiabei, and the accompanying drawings are used for detailed implementation. Referring to FIGS. 1A to 1C, it illustrates a semiconductor device according to a preferred embodiment of the present invention. Flow chart of defect detection method. Please refer to FIG. 1A, a semiconductor device 100 is provided. The semiconductor device includes a substrate 102, a gate electrode 104, a protective layer 106, a plug 108, a terminal 110, a bit line 112, and Stacked layer workers i 4. The q plug 108 is, for example, electrically connected to the base 102 on both sides of the gate 104.

Page 7 11535twf.ptd 1220548 V. Description of the invention (4) The source / non-electrode area 1 1 6 covers part of the gate electrode 104. There is a defect 1 18 between the plug 108 and the gate 104. The defect 1 1 8 is, for example, a conductor particle 'that causes a short between the plug 108 and the gate 104, and the defect π 8 includes a nano-scale defect. The protective layer 106 is composed of, for example, a TEOS silicon oxide layer and a silicon nitride layer. The material of the insulating layer 1 10 is, for example, TE0S silicon oxide. The stacked layer 1 1 4 includes a capacitor, an insulating layer, a plug, and a wiring layer disposed above the bit line 1 12. In this embodiment, for the sake of simplicity, only the stacked layers 114 are used to replace each subsequent film layer formed above the bit line.

Next, referring to FIG. 1B, a polishing step is performed to polish the semiconductor device 100 until the plug 106 does not cover the gate electrode 104. In this polishing step, the polishing machine used is, for example, a MODEL manufactured by JOEL LTD. For example, it is washed with deionized water for a half. This cleaning step usually takes ‘Please refer to Figure 1C. Protective layer 106 and insulating layer 11 〇. Carved steps using hydrofluoric acid (HF) silicon. Reactive ionized silicon is then performed. In this step, it will not be removed. In addition, after moving the layer 106 and the insulating layer 丨 丨 0, a 6 5 6N dimple grinder is measured between the plug 108 and the gate electrode 104. Of course, in this step, the semiconductor wafer can also be polished until the gate electrode 4 is exposed. After the grinding step, a cleaning step is performed to clean the semiconductor element. This cleaning step of the conductor element, followed by a drying step, takes about 5 to 10 seconds.

'Remove between gate 1 〇4 and plug 1 〇 ί In this step, for example, first perform a wet ^ solution as an etchant, remove TE0S oxygen ^ remove the silicon nitride layer and TE in the remaining process. The sj defect 11 8 is usually a conductive particle, so a cleaning step is also performed in addition to the protection between the gate 104 and the plug 108. After that, the defects 1 1 8. The instrument used is, for example, 1220548 V. Description of the invention (5) Scanning electron microscope. In the above-mentioned embodiments of the present invention, the detection between the plug and the gate is used as an example for illustration. Of course, the method of the present invention can also be applied to detect the defects between the conductor layers (wires). For example, to detect defects between three adjacent conductors (such as bit lines), you can first grind to approximately expose the surface of two adjacent conductive layers, and then remove the insulating layer between the conductor layers (remove the insulating layer). = Method can use dry etching or wet etching), and then use the scanning electronic display test mirror 'to detect defects between adjacent conductor layers. Next, Experimental Example 1, Experimental Example 2 and Comparative Example 丨 are used to illustrate the points of the present invention. Experimental Example 1, Experimental Example 2 and Comparative Example 1 use dynamic random access memory as an example. Experimental Example 1 Provides a fU with a line width of 0.15 micrometers, and handles this “Far Haruka” (Dynamic Random Access Memory). The dagger + conductor chip enters a grinding step W, and the grinding base is not Cover the gate until it ’s over. Grind it here. ^ Fortunately, in this grinding step, the grinding time is, for example, 22: 1. After the semiconductor wafer is cleaned, remove the gate ^ ^ ^ ^ S-here For example, in step V, wet etching is first performed, and etching is performed for 1 minute using a lice acid (HF) solution as an etchant. Then, the reactive ion name is engraved. After the insulating layer between the polar spot plugs, ^ 2ΓΗ: ΛΛ detection of the semiconductor wafer is also performed. The results are shown in Figure 2A and Figure Ϊ :: 2, which are divided into the memory cell area of the dynamic random memory.) Provide the line Semiconductor chip (dynamic random access memory) with a width of 0.13 micrometers,

1220548 V. Description of the invention (6) = After the semiconductor wafer is subjected to the same process steps as in Experimental Example 1, a scanning electron microscope is used to detect the semiconductor wafer. The results are shown in Figure 3 and Figure 3B (the part of the figure is the cell area of the dynamic random memory). Comparative Example 1, mention, see 0.15 micron semiconductor device (Dynamic Random Access Memory), =, hydrofluoric acid was used as an etchant for wet etching for 3 minutes to remove the lead, and then a cleaning step was performed. . Then, the sulfuric acid is used as an etchant for etching for a minute to remove the electrode layer layer (CeU p layer) on the memory cell, and then the storage node layer is moved to the silicon / Λ step. Reactive ion etching was performed for 2 minutes to remove the nitrogen dielectric layer = minutes to remove the nitride layer / oxide stone " nitride layer capacitor etchant, and then remove the insulating layer. Domain, with potassium hydroxide as the etch: ;;: 5 shift eight ^ clean. Enter the room for 5 knives and 1 mile. After removing the lower electrode plate, perform a bit line engraving agent to engrav the surname for 2G seconds. Then, use potassium hydroxide as the contact engraving agent, and perform ㈣5 minutes. VV / hydrofluoric acid was used as the semiconductor wafer; cat-type electron microscope, phase " ,,,. As shown in Figure 4A and Figure 4B (the part of the figure 11535twf.ptd page 10 1220548 V. Description of the invention (7) divided into the memory cell area of dynamic random memory). Among them, after the removal process of each layer, a cleaning step is performed. According to the results of Experimental Example 1 and Experimental Example 2, as shown in Figs. 2B and 3B, defects between the gate and the plug can be clearly found. Moreover, the method of the present invention can also be applied to a device having a small line width. However, from the results of Comparative Example 1, as shown in Fig. 4B, a defect between the gate and the two plugs could not be found. This is because the defects that cause the short-circuit between the gate and the plug are conductor particles. In the process of removing the entire plug by wet etching, the defect is also removed at the same time. Therefore, in Figure 4B, defects cannot be detected. …, In addition, from the above results, experimental examples are shown! The time required for Experimental Example 2 is about 15 minutes, while the time required for Comparative Example i is at least 30 minutes. Therefore, the method of the present invention can save time compared with the conventional method. ^ "In addition, Figures 5A and 5B are scanning electron microscope photographs of other experimental examples of the present invention. As shown in Figures 5A and 5B, the defects between the gate and the plug can be clearly seen. It was detected. 〃Toryu The above-mentioned Experimental Example 1, Experimental Example 2 and Comparative Example 1 of the present invention are described by taking the memory cell area of the dynamic random access memory as an example. Of course, the method of the present invention can also be applied to dynamic random access The peripheral circuit area of the memory is accessed to detect defects of other types of semiconductor elements. 1. According to the above embodiment of the present invention, the present invention adopts a grinding method, and the semiconductor element is directly ground until the plug does not cover the upper part of the gate, and then the insulation layer between the gate and the plug is removed. Can be avoided

1220548 V. Description of the invention (8) The defect is removed due to wet etching, and the defect can be accurately detected. It also saves time. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

11535twf.ptd Page 12 1220548 Brief description of drawings Figures 1A to 1C are cross-sectional views illustrating a method for detecting a defect of a semiconductor device according to a preferred embodiment of the present invention. Figures 2A and 2B are photographs of a scanning electron microscope of a semiconductor device according to Experimental Example 1 of the present invention. 3A and 3B are scanning electron microscope photographs of a semiconductor device according to Experimental Example 2 of the present invention. 4A and 4B are scanning electron microscope photographs of a semiconductor device according to Comparative Example 1 of the present invention. 5A and 5B are photographs of a scanning electron microscope of a semiconductor device according to another experimental example of the present invention. Description of the drawings 100 semiconductor element 102 substrate 104 gate 106 protective layer 108 plug 110 insulating layer 112 bit line 114 stacked layer 116 source / > and electrode region 118 defects

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Claims (1)

1220548 6. Scope of patent application1. A method for detecting defects of a semiconductor element, the semiconductor element to y includes a substrate, a gate, a plug, an insulating layer and a wire, wherein the plug is electrically connected to the gate A source / drain region in the substrate on both sides covers a portion of the gate, and there is a defect between the plug and the gate. The method includes: performing a polishing step, at least polishing the semiconductor element to The plug does not cover above the gate; a cleaning step is performed to clean the semiconductor element; the insulation layer between the gate and the plug is removed; and the detecting between the plug and the gate is performed defect. 2. The method for detecting a semiconductor element defect according to item 1 of the scope of the patent application, wherein the grinding step further comprises grinding to approximately expose the gate electrode. 3. The method for detecting a semiconductor element defect as described in item 1 of the scope of the patent application, wherein the cleaning step includes: cleaning the semiconductor element with deionized water; and drying the semiconductor element. 4. The method for detecting a semiconductor element defect according to item 1 of the scope of the patent application, wherein the step of removing the insulating layer between the gate electrode and the plug includes: performing a wet etching process; and performing a dry type Engraving process. 5. The method for detecting a semiconductor element defect as described in item 4 of the scope of the patent application, wherein the material of the insulating layer includes silicon oxide, and the wet etching process includes using a hydrofluoric acid (HF) solution as an etching solution. 11535twf.ptd 1220548 6. Scope of patent application Test method 6 · Semiconductor element defect inspection method as described in item 4 of the scope of patent application, the dry etching process includes a reactive ion etching process. Test method 7. Inspection of semiconductor element defects as described in item 4 of the patent claim. The method of detecting the defect between the plug and the gate includes using an f-eye seedling electron microscope. w, 勹 8 · A semiconductor element defect detection method, the semiconductor element includes two adjacent conductor layers and an insulating layer, and the insulating layer fills a gap between the adjacent conductors, wherein the two phases There is a method between adjacent conductor layers. The method includes: conducting a grinding step of the conductor, grinding the conductor element to approximately expose the insulation layer between the two removed conductor layers; and detecting the two conductor layers. Between the defects. 9 · According to the method for inspecting semiconductor device defects as described in item 8 of Shenjing's patent scope, f tb 4 * /, t after the grinding step and removing the ^, ,, and e-layers between the two conductor layers This step is preceded by a perform / wash step. 10 • The method for detecting a semiconductor element defect as described in item 9 of the scope of the patent application, wherein the cleaning step includes: washing the semiconductor element with deionized water; and drying the semiconductor element. The testing method, the method for detecting semiconductor element defects as described in the eighth patent claim, wherein the method of removing the insulation layer between the two conductor sounds includes ζ,, and engraving. 1 2 · Inspection of semiconductor element defects as described in item 8 of the scope of patent application U535twf .ptd No. 15 tribute 1220548 6. Method of scope of patent application testing, wherein the method of removing the insulation layer between the two conductor layers includes Dry etching. 1 3. The method for detecting a semiconductor device defect as described in item 12 of the scope of patent application, wherein the dry etching includes a reactive ion etching process. 1 4. The method for detecting a semiconductor element defect as described in item 8 of the scope of patent application, wherein the step of detecting the defect between the two conductor layers includes using a scanning electron microscope. 11535twf.ptd Page 16